JP3130803B2 - Remote control signal receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a remote control (hereinafter, simply referred to as "remote control") signal receiving apparatus.
In particular, the present invention relates to a remote control signal receiving device with reduced disturbance noise.

[0002]

2. Description of the Related Art The waveform of a remote control signal will be described with reference to FIG. As shown in FIG. 9A, the period is 108 ms.
Is used as a remote control signal, and this remote control signal has a different waveform between the first transmission and the second and subsequent transmissions.

At the time of the first transmission, as shown in FIG. 9B and an enlarged view of FIG. 9C, a 9 ms mark and a 4.5 ms space are followed by an 8-bit custom code CC. An 8-bit data code DC is used as complement data (positive and inverted data) for a total of 3 bits.
It is a signal synthesized with 2-bit time-series data, and is hereinafter referred to as a one-shot code.

FIG. 9A shows inverted data with respect to FIGS. 9B to 9D.

At the time of the second and subsequent transmissions, as shown in FIG. 9D, the signal includes a 9 ms mark, a 2.2 ms space, and a 0.56 ms mark, and is hereinafter referred to as a repeat code. .

A remote control signal having such a waveform is 38 KHz.
Is modulated and transmitted. Various noises are mixed in the remote control signal. In particular, the discharge noise of the fluorescent lamp has a frequency component of just 38 KHz,
Since the noise waveform is as shown in FIG. 1, this noise mixes with the remote control signal, making it difficult to determine the code.

In order to solve this problem, Japanese Patent Laid-Open No.
JP-A-162189 proposes a remote control signal receiving device as shown in FIG.

In FIG. 10, after a remote control signal from a remote control transmitter 1 is received by a light receiving element 2, 38
The signal is amplified and detected by the amplifier / detector 3 through the KHz band-pass filter 4 and input to the pulse width discriminating circuit 7.

The pulse width of the code of the remote control signal is 0.5
Focusing on 6 ms (see FIG. 9), a pulse width of 0.
The pulse width up to 2 ms (200 μs) is cut off and 0.5
By providing the pulse width discriminating circuit 7 that passes a pulse width of ms (500 μs) or more, discharge noise is removed.

That is, in the pulse width discrimination circuit 7,
The input remote control signal is a sawtooth wave, and a pulse signal is generated by comparing the magnitude of the sawtooth wave with a certain threshold level.

[0011]

Such a conventional circuit configuration has a drawback that the pulse width of the finally obtained remote control signal varies. The reason is that the received remote control signal is converted into a sawtooth wave by an analog circuit and is converted into a pulse in comparison with a fixed threshold level, so that the pulse width is not stable due to variations in components and the like.

Further, the pulse width of noise that can be removed is 10
There is a disadvantage that the width is limited to a narrow width of 0 μs to 200 μs. The reason is that it is necessary to reduce the pulse width of the noise that can be removed due to variations in the threshold level and the integration circuit for converting the signal into a sawtooth wave.

An object of the present invention is to provide a remote control signal receiving device capable of preventing malfunction due to disturbance noise.

[0014]

SUMMARY OF THE INVENTION A remote control signal receiving apparatus according to the present invention is a remote control signal receiving apparatus for receiving a remote input signal and outputting a received remote control signal from which noise has been removed. A monostable multivibrator that generates a pulse of a predetermined width in response to a level transition of the control signal; and an interrupt processing routine that is activated in response to the received remote control signal. 8 ms from the leading edge of the leader code indicating the start of the input remote control signal in response to the received remote control signal, which is the start of the 9 ms mark.
Pulse generation means for generating a gate pulse for a certain period during which a subsequent custom code and data code exist after the lapse of time; and fetching and latching the input remote control signal in response to the sampling pulse to output a latch output to the monostable multi A latch circuit serving as a reset input of the vibrator, an OR gate for generating a logical sum of a pulse output of the monostable multivibrator and the input remote control signal, and a monostable multivibrator for outputting the latch output during a period of the gate pulse And an AND gate that supplies the OR output as a reset input, and the OR output is used as the reception remote control signal.

[0015]

[0016]

[0017]

The input remote control signal is sampled with a sampling signal that matches the timing of a prescribed remote control signal code, and a pulse is generated at the timing of the input remote control signal by pulse generation means such as an MMV, and the timing of the sampled signal By resetting the pulse, a signal free of noise is generated.

Further, since the noise component is canceled by performing an OR operation on the input remote control signal and the pulse, it is possible to reproduce a waveform having a pulse width that matches the input remote control signal at the correct timing. .

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention, and the same parts as those in FIG. 10 are denoted by the same reference numerals. In this example, the remote control signal IN which is the output of the amplification / detector 4
And a pulse forming circuit 5 which takes in the input remote control signal IN with a sampling pulse from the remote control signal determination unit 6 and shapes the waveform to obtain a received remote control signal OUT.

Further, based on the received remote control signal OUT, it is determined whether the one-shot code shown in FIGS. 9B and 9C or the repeat code shown in FIG. 9D is used. And a remote control signal discriminating unit 6 that generates a sampling pulse at a predetermined timing (see FIG. 9).

FIG. 2 is a circuit block diagram showing an example of the pulse generation circuit 5 of FIG. In FIG. 2, an input remote control signal IN is one input of an OR gate 51, and an output of the OR gate 51 is a remote control signal determination unit (CPU).
6 P0 input.

The sampling pulse Q1 from the remote control signal discriminating section 6 becomes a clock input to a D-FF (D-type flip-flop) 52 which is a latch circuit.
The input remote controller signal IN is applied to the input, so that the input remote controller signal IN is taken in and latched by the sampling signal Q1.

The latch output Q2 is used as one input of an AND gate 53. The output of the AND gate 53 is a retriggerable MMV (monostable multivibrator) 54.
Reset input. Trigger input B of this MMV54
Is supplied with the input remote control signal IN,
The MV 54 is triggered by the input remote control signal IN, generates a pulse having a constant pulse width, and is reset by the latch output Q2 by the D-FF 52.

The pulse Q3 from the MMV 54 becomes the other input of the OR gate 51 and is ORed with the input remote control signal IN to derive the reception remote control signal OUT. The D-FF 52 is reset by the reception remote control signal OUT.

As a gate signal applied to the other input of the AND gate 53, a gate pulse Q4 generated from the remote control signal discriminating section 6 is used. This gate pulse Q4 is
As shown in the waveform example of FIG. 3, the signal rises from the initial period 8 ms of the 9 ms mark (see FIG. 9), and has a pulse width slightly larger than the period in which the custom code or the data code exists.

Remote control signal I received by light receiving element 2
N is usually inverted as shown in FIG. The disturbance noise is mixed in the H level period in FIG. Now, the remote control signal OUT is connected to P0 of the remote control signal discriminating unit 6, and a state in which the L level continues for 8 ms from the falling edge is detected. When this state is detected, the remote control signal determining section 6 determines that the remote control signal has arrived, as shown in the waveform examples of FIGS.
4 is set to the H level, and the gate signal Q4 of the H level is continuously output for 66 ms from the next rising edge of the remote control signal, and supplied to the other input of the AND gate 53.

FIG. 3 is an operation waveform diagram when the input remote control signal IN is a repeat code, and FIG. 4 is an operation waveform diagram when the input remote control signal IN is a one-shot code including a custom code and a data code.

The remote control signal determining section 6 determines whether the input remote control signal IN is a repeat code or a one-shot code, at a timing 2.25 ms after the next rising edge of the state where the L level continues for 8 ms of the remote control signal. Generates a sampling pulse Q1.

Then, at the rising edge of the pulse Q1, the remote control signal IN input to the input D of the flip-flop 52 is sampled and latched for decoding. If the input signal is the repeat code signal of FIG.
Is at L level, and the output Q2 is at L level.

If the input signal is the one-shot code signal of FIG. 4A, the D terminal of the flip-flop 52 is at the H level, and the output Q2 is held at the H level. Then, 4.5 ms after the rise, L
Since the level is at the level, the output Q2 becomes L.

Since the output Q2 is supplied to the reset input R of the MMV 54, a signal having a certain pulse width is obtained as the output signal Q3 of the MMV 54 by inputting the L level to the reset input R. The MMV 54 outputs a pulse with the rising edge of the remote control signal IN as a trigger. Therefore, the repeat code or the leader code (the high-level portion in FIG. 4 preceding the custom code) is reproduced.

Similarly, if the data of the subsequent custom code is 0, 0.56 m from the rising edge of P0
After s, the remote control signal IN is at the L level,
The output Q2 becomes L level. If the data is 1,
The H level is at 0.56 ms, and the output Q2 is at L level after 1.7 ms. Therefore, the pulse width of the data corresponding to the input signal is obtained.

In this manner, a signal having a signal timing suitable for the remote control code and a pulse width equivalent to the input signal can be obtained. Disturbance noise due to a fluorescent lamp or the like mixed during the period when the output Q3 of the MMV 54 is at the H level is output by the OR gate 51.
And the remote control signal OUT having no noise component is reproduced. Malfunction due to disturbance noise by decoding by inputting the signal to the P0 of the remote control signal determination unit 6 Ru is reduced.

Next, the operation of the remote control signal discriminating section 6 will be described in detail with reference to the flowcharts of FIGS. The remote control signal discriminating unit 6 can be realized by a computer using a CPU (processor) that operates according to the flowcharts shown in FIGS.

FIG. 5 is a flowchart of an interrupt processing routine started by using a signal input to the P0 terminal as an interrupt signal, and FIG. 6 is a flowchart of timer interrupt processing using a 10 μs timer. "
7 is a flowchart for determining the repeat code and the repeat code and the leader code.

FIG. 7 is a flowchart of a timer interrupt process using a 1 ms timer.
It is a flowchart for determination of the L period of ms, and determination of the H period of 66 ms until the end of a custom data code.

FIG. 8 is a flowchart of the event processing, and is a flowchart for generating a sampling signal Q1 which is a clock input of the D-FF 52.

Prior to the description of FIGS. 5 to 8, the following counters are defined. Counter A has data code "0"
And a 0.56 ms (56 in 10 μs timer conversion) counter. The counter B is for determining the data code "1", and is 1.7 ms.
(170 in terms of a 10 μs timer).

The counter C is for determining a repeat code, and is a 2.25 ms (225 in terms of a 10 μs timer) counter. The counter D is for discriminating a leader code, and is a 4.5 ms (450 in terms of a 10 μs timer) counter.

The counter E is for detecting an 8 ms period (referred to as an 8 ms flag), and the counter F is set to 6
This is for detecting a 6 ms period (referred to as a 66 ms flag).

Referring to FIG. 5, when the interrupt signal is input to the terminal P0, it is determined whether the determination is 8ms period L level ended in 8ms flag (step 101, step term below will be omitted). In this case, an 8 ms flag is provided in a memory or a register (not shown) in advance,
If the 8 ms flag is on, it indicates "end", if it is off, it indicates "not completed", and the same applies to other flags.

In the case of "not completed" (No), 1 ms in FIG.
Each counter value required to shift to the timer interrupt process is set in each counter in process A1 (102 to 10).
4). Then, in step 105, the 1 ms timer interrupt process of FIG. 7 is started, and the process returns to the beginning.

In the case of "end" (Yes) in step 101, it is determined whether or not the repeat code / leader code has been determined by the data code flag (10).
6). In the case of "not completed" (Yes), the respective counter values required to shift to the 10 μs timer interrupt processing of FIG. 6 are set in the respective counters (107 to 109), and the interrupt processing is terminated.

Also in the case of "end" (No) in step 106, each counter value necessary for shifting to the 10 μs timer interrupt processing of FIG. 6 is set in each counter (110 to 112), and End the interrupt processing.

In the 10 μs counter interrupt process of FIG. 6, the 10 μs timer is subtracted by the count value set by the flowchart of FIG. 5 (201, 202, 2).
05, 206, 209, 210, 213, 214), when the count value becomes 0 (203, 207, 211, 214).
15), the process proceeds to the event process of FIG. 8 (204, 20)
8, 212, 216).

As described above, the values measured by the 10 μs timer are 225 (counter C) for the repeat code, 450 (counter D) for the reader code, and 56
(Counter A), 170 of data 1 (counter B), and these values correspond to the timing specified in advance as the remote control signal, and the event that generates the sampling signal Q1 in accordance with the respective timings The processing shifts to the processing (FIG. 8).

Referring to the flowchart of the event processing shown in FIG. 8, this event processing generates a sampling clock Q1 for the D-FF 52, latches the remote control signal IN to the D-FF 52, and outputs the signal at the latch timing. This is a process of creating a timing specified in the remote control signal in order to create a signal containing no noise by resetting the MMV 54.

First, when entering the event processing, the sampling pulse Q1 is set to the H level for 0.2 ms (301
To 303). As a result, the remote control signal IN containing noise is fetched into the D-FF 52, and if the fetched data is 0, L is output, and if it is 1, H is output from the Q2 of the D-FF 52.

In the case of L, the reset input of the MMV 54 is L
Is applied to generate a pulse. The generated pulse is input to P0 of the CPU 6 again (304). At this time, if the determination of the leader code / repeat code is not completed (305), the reader code / repeat code is checked in process A4, and the data code flag is turned on (307, 308).

If it is determined in step 305 that the data code flag is on, the process proceeds to process A5, where data 0, 1
Is determined (306).

FIG. 7 shows a flowchart of the 1 ms timer interrupt process. As shown in process A2, the counter E set in FIG. 5 is counted and measured by eight counts, and the level of P0 is maintained for 8 ms. If L, it is determined that the signal is a remote control signal, and the 8 ms flag indicating the end of 8 ms measurement is turned on (401 to 407), and at the same time, Q4 is set to the H level (408). Then, the interrupt signal input to P0 is changed from falling to rising (A3).

If P0 goes high during the 8 ms measurement, it is not a remote control signal, so that all counters are reset to 0 during the measurement to prepare for the 8 msL period (4).
15).

After 66 ms, the processing of the ordinary remote control signal ends, so the count value of the counter F (initial value 6
When 6) becomes 0 (409 to 411), Q4 is set to L (412), and the 8 ms flag and the data flag are respectively turned off (413, 414) to prepare for the input of the next remote control signal. Naturally, remote control interrupt (P0)
Is changed to the falling edge (416).

[0056]

According to the present invention, a remote control signal containing disturbance noise due to a fluorescent lamp or the like is received, and the remote control signal is decoded by a flip-flop at a signal timing suitable for the remote control code. The signal of the pulse width of the received remote control signal can be recreated at the same timing, and the remote control signal without disturbance noise can be reproduced, thereby reducing erroneous determination. Also, since the received signal is decoded at the timing corresponding to the remote control signal, the pulse width of the noise is 100 μm.
It is not limited to a narrow range of ~ 200μ.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of a pulse generation circuit 5 of the block in FIG.

FIG. 3 is an operation waveform diagram of each part when an input remote control signal is a repeat code.

FIG. 4 is an operation waveform diagram of each unit when an input remote control signal is a single-shot code including a data code.

FIG. 5 is a flowchart showing an interrupt processing routine when the CPU 6 interrupts the P0 terminal.

FIG. 6 is a flowchart showing a 10 μs timer interrupt processing routine of a CPU 6;

FIG. 7 is a flowchart showing a 1 ms timer interrupt processing routine of a CPU 6;

FIG. 8 is a flowchart illustrating an event processing routine of the CPU 6;

FIG. 9 is a diagram illustrating a waveform example of a remote control signal.

FIG. 10 is a diagram illustrating an example of a conventional remote control signal receiving device.

FIG. 11 is a diagram illustrating an example of a noise waveform due to a fluorescent lamp.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 remote control transmitter 2 light receiving element 3 amplifier / detector 4 bandpass filter 5 pulse creation circuit 6 remote control signal discriminator (CPU) 51 OR gate 52 D-FF 53 AND gate 54 MMV

Continuation of the front page (56) References JP-A-58-162189 (JP, A) JP-A-60-237737 (JP, A) JP-A-61-284130 (JP, A) JP-A-7-336325 (JP) JP-A-8-65771 (JP, A) JP-A-5-22778 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04Q 9/00-9/16 H03J 9/00-9/06

Claims (3)

(57) [Claims] 1. A remote control signal receiving apparatus for receiving a remote input signal and outputting a received remote control signal from which noise has been removed, comprising: a pulse having a predetermined width in response to a level transition of the remote control signal; A monostable multivibrator to be generated, an interrupt processing routine started in response to the reception remote control signal, and a sampling pulse of a predetermined timing of the remote control signal generated according to the interrupt processing routine; 9 ms of a leader code indicating the start of the input remote control signal in response to the signal.
Pulse generating means for generating a gate pulse for a certain period during which a subsequent custom code and data code exist after a lapse of 8 ms from the leading edge of the start of the mark, and capturing the input remote control signal in response to the sampling pulse A latch circuit that latches and sets a latch output as a reset input of the monostable multivibrator;
An OR gate that generates a logical sum output of the pulse output of the monostable multivibrator and the input remote control signal, and an AND gate that supplies the latch output as a reset input of the monostable multivibrator during the existence of the gate pulse. A remote control signal receiving apparatus, wherein the logical sum output is used as the reception remote control signal. 2. The remote control signal receiving device according to claim 1, wherein said pulse generating means is configured to generate said sampling pulse in response to said OR output. 3. The pulse generating means receives the logical sum output as input and detects a state of a constant level for a fixed period indicating the start of a remote control signal, and the sampling of the prescribed timing in response to the detection. 3. The remote control signal receiving device according to claim 2, further comprising means for sequentially generating pulses.