JP3128205B2 - Flattening pattern generation method, flattening pattern generation device, and semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for easily generating a flattening pattern for flattening a wiring layer when forming a multilayer wiring layer in a semiconductor integrated circuit device such as an LSI. And a semiconductor integrated circuit device manufactured using the method for generating a flattening pattern.

[0002]

2. Description of the Related Art In recent years, multi-layered wiring layers have been used for high integration of VLSI.

However, when the wiring layers are multilayered, the unevenness of the lower wiring pattern affects the interlayer insulating film formed on the wiring layer on which the lower wiring pattern is formed. Also, uneven portions appear. The projections and depressions in the interlayer insulating film cause poor step coverage during printing of the upper wiring layer (printing error due to the formation of a step with a depth of focus or more on the wafer during pattern exposure using a mask). Problems such as disconnection and failure occur in the wiring layer. Therefore, planarization of the surface of the interlayer insulating film is a technique necessary for realizing a highly reliable multilayer wiring structure.

[0004] A resin coating method or the like has been used as a typical technique for flattening an interlayer insulating film in the past, but this method has a problem that sufficient flattening cannot be obtained. Therefore, a method of flattening an interlayer insulating film by generating a flattening pattern (auxiliary pattern) using a CAD technique in a gap between wirings has been proposed.

As a method of generating a flattening pattern using the CAD technique, for example, a method disclosed in Japanese Patent Application Laid-Open No. 5-267460 is known.

Hereinafter, a conventional method for generating a flattening pattern will be described with reference to the drawings. FIG. 41 (a)-
(D) and FIGS. 42 (a) and 42 (b) are process diagrams for explaining a method of generating a flattening pattern in the vicinity of a wiring pattern for transmitting an LSI signal by a conventional flattening pattern generating method. .

First, a wiring pattern 1 shown in FIG.
41b to generate an inverted wiring pattern 2 shown in FIG. 41 (b), and then perform a graphic reduction process for reducing the inverted wiring pattern 2 to perform a reduced inverted wiring pattern 3 as shown in FIG. 41 (c). Generate In this case, the amount by which the inverted wiring pattern 2 is reduced is approximately equal to the minimum distance among the distances between the wiring patterns 1 on the chip plane shown in FIG.

Next, as shown in FIG. 41 (d), after generating a dummy original pattern 5 which is a graphic pattern in which simple figures are repeatedly arranged, a graphic logical difference between the reduced inverted wiring pattern 3 and the dummy original pattern 5 is obtained. By performing the operation, FIG.
A flattening pattern 6 as shown in FIG. Thereafter, a graphic OR operation of the wiring pattern 1 and the flattening pattern 6 is performed to generate a final pattern as shown in FIG.

[0009]

However, according to the above-described flattening pattern generation method, the flattening pattern 6 generated in the vicinity of the wiring pattern 1 includes the positions of the wiring pattern 1 and the dummy original pattern 5. Due to the relationship, the original shape of the dummy original pattern 5 is not maintained, that is, a minute flattened pattern 6a greatly reduced from the shape of the dummy original pattern 5 may be generated. There is a problem that there is a minute thing that does not satisfy the design rule of the layout design of the wiring pattern 1.

Further, as a result of generating the flattening pattern 6, there is a problem that the number of figures of the flattening pattern 6 becomes enormous and the data amount increases.

In view of the above, the present invention provides a flattening pattern that satisfies the design rules of the layout design of the wiring pattern and that can reduce the number of figures and the data amount of the flattening pattern. It is an object to provide a method and an apparatus for generating a pattern and a semiconductor integrated circuit device.

[0012]

According to a first method of generating a flattening pattern according to the present invention, a simple pattern set is formed in a region of a wiring layer at a predetermined distance or more from a wiring pattern forming region where a wiring pattern is formed. And a flattening pattern generating step of generating a flattening pattern by reducing the dummy pattern and then enlarging the remaining figure pattern.

According to the first method for generating a flattening pattern, after a dummy pattern consisting of a set of simple figures is reduced, the remaining figure pattern is enlarged to generate a flattening pattern. Since a simple figure that does not exist is eliminated by the reduction process, the flattening pattern is composed of only a simple figure having a predetermined size or more.

In the first flattening pattern generating method, the dummy pattern generating step includes a step of enlarging the wiring pattern by a first predetermined amount to generate an enlarged wiring pattern, and a step of repeatedly arranging simple figures to form a dummy element. The flattening pattern generation step includes a step of generating a dummy pattern by performing a graphic logical difference operation process of removing an overlapping portion of the dummy wiring pattern with the enlarged wiring pattern from the dummy original pattern. It is preferable to include a step of generating a reduced dummy pattern by reducing the reduced dummy pattern by a predetermined amount and a step of generating a flattened pattern by expanding the reduced dummy pattern by a second predetermined amount.

In the first flattening pattern generating method, the dummy pattern generating step includes a step of generating an inverted wiring pattern by graphically inverting the wiring pattern, and reducing the inverted wiring pattern by a first predetermined amount. And generating a dummy original pattern by repeatedly arranging a simple figure, and a graphic AND operation process of leaving only an overlapping portion of the dummy original pattern with the reduced inverted wiring pattern. Generating a dummy pattern, wherein the flattening pattern generating step includes the step of reducing the dummy pattern by a second predetermined amount to generate a reduced dummy pattern, and expanding the reduced dummy pattern by a second predetermined amount. And generating a flattening pattern.

According to a second method of generating a flattening pattern according to the present invention, the first flat pattern is formed from a set of simple figures in a region at least a first predetermined distance from a wiring pattern forming region where a wiring pattern is formed in a wiring layer. A first dummy pattern generating step of generating the dummy pattern of the above, a second dummy pattern generating step of generating a second dummy pattern by reducing the first dummy pattern and then enlarging the remaining figure pattern, A third dummy pattern composed of a set of parallel simple figures is generated in a region of the wiring layer that is at least a first predetermined distance from the wiring pattern formation region and at least a second predetermined distance from the first dummy pattern. A third dummy pattern generation step, and a fourth dummy pattern for generating a fourth dummy pattern by reducing and then expanding the third dummy pattern; A generation step, and a flattening pattern generation step of synthesizing the second dummy pattern and the fourth dummy patterns to generate a flattened pattern.

According to the second method for generating a flattening pattern, similar to the first method for generating a flattening pattern, a first or third set of simple figures or a set of simple figures that have been translated.
After the dummy pattern is reduced, the remaining graphic pattern is enlarged to generate a flattened pattern. Therefore, the flattened pattern is composed of only a simple figure having a predetermined size or more or a simple figure that has been translated. Further, since the flattening pattern is formed by using the second dummy original pattern in addition to the first dummy original pattern, the wiring patterns are compared with each other as compared with the case where the flattening pattern is generated only by the first dummy original pattern. The area that is not filled by the flattening pattern during the period is reduced.

In the second flattening pattern generating method, the first dummy pattern generating step includes a step of enlarging the wiring pattern by a first predetermined amount to generate an enlarged wiring pattern, and a step of repeatedly arranging simple figures. Generating a first dummy original pattern by performing a graphic logical difference operation process of removing an overlapping portion of the first dummy original pattern with the enlarged wiring pattern, thereby generating a first dummy pattern. The second dummy pattern generation step includes a step of reducing the first dummy pattern by a second predetermined amount to generate a first reduced dummy pattern, and a step of enlarging the first reduced dummy pattern by a second predetermined amount. Generating a second dummy pattern by performing a third dummy pattern generation step, wherein the third dummy pattern generation step includes: Generating an original pattern; enlarging the second dummy pattern by a third predetermined amount to generate an enlarged dummy pattern; and overlapping an enlarged wiring pattern and an enlarged dummy pattern from the second dummy original pattern. Generating a third dummy pattern by means of a graphic logical difference operation process for removing the third dummy pattern. The fourth dummy pattern generating step includes reducing the third dummy pattern by a fourth predetermined amount to perform a second reduction. Generating a dummy pattern; and enlarging the second reduced dummy pattern by a fourth predetermined amount to generate a fourth dummy pattern.
It is preferable that the flattening pattern generating step includes a step of generating a flattening pattern by a graphic OR operation for superimposing the second dummy pattern and the fourth dummy pattern.

According to a third method of generating a flattening pattern according to the present invention, the first flat pattern is separated from the wiring pattern forming region in the wiring layer by a first predetermined distance or more and the first predetermined distance or more.
A first dummy pattern generating step of generating a first dummy pattern composed of a set of simple figures in an area within a second predetermined distance larger than the predetermined distance, and a second predetermined pattern from a wiring pattern forming area in the wiring layer. A second dummy pattern generating step of generating a second dummy pattern composed of at least one graphic larger than a simple graphic in an area separated by a distance or more, and combining the first dummy pattern and the second dummy pattern; And a flattening pattern generating step of generating a flattening pattern.

According to the third method of generating a flattening pattern, the first flattening pattern consisting of a set of simple figures is located in a region apart from the wiring pattern forming region by a first predetermined distance or more and within a second predetermined distance. On the other hand, in a region separated from the wiring pattern formation region by a second predetermined distance or more,
Instead of the flattening pattern consisting of a set of simple figures, a second flattening pattern consisting of at least one figure larger than the simple figure is generated.

In the third method of generating a flattening pattern, the first dummy pattern generating step includes a step of expanding the wiring pattern by a first predetermined amount to generate a first enlarged wiring pattern; A step of generating a second enlarged wiring pattern by enlarging by a second predetermined amount larger than the first predetermined amount; a step of inverting the second enlarged wiring pattern to generate an inverted pattern; A process of repeatedly generating a dummy original pattern by arranging the dummy original pattern, and a process of generating a first dummy pattern by a graphic logical difference operation process of removing an overlapping portion of the first enlarged wiring pattern and the inverted pattern from the dummy original pattern. The second dummy pattern generation step includes a step of generating a second dummy pattern made of an inverted pattern, and the flattening pattern generation step includes a first dummy pattern. Preferably includes the step of generating a flattened pattern by pattern and a second graphic logical sum operation to superimpose the dummy pattern.

In the third flattening pattern generating method, the first dummy pattern generating step includes a step of enlarging the wiring pattern by a first predetermined amount to generate an enlarged wiring pattern, and a step of inverting the wiring pattern. A step of generating an inverted pattern; a step of reducing the inverted pattern by a second predetermined amount larger than the first predetermined amount to generate a reduced inverted pattern; and a method of repeatedly arranging simple figures to generate a dummy original pattern. And a step of generating a first dummy pattern by a graphic logical difference operation process of removing an overlapping portion of the enlarged wiring pattern and the reduced inversion pattern from the dummy original pattern. The method includes a step of generating a second dummy pattern composed of an inverted pattern, and the step of generating a planarization pattern includes the step of generating the first dummy pattern and the second dummy pattern. Preferably includes the step of generating a flattened pattern by figure logical sum operation to superimpose and over pattern.

In the third flattening pattern generating method, the first dummy pattern generating step includes a step of expanding the wiring pattern by a first predetermined amount to generate a first enlarged wiring pattern; A step of generating a second enlarged wiring pattern by enlarging by a second predetermined amount larger than the first predetermined amount; a step of generating a first inverted pattern by inverting the second enlarged wiring pattern; A step of generating a reduced inverted pattern by reducing the first inverted pattern by a third predetermined amount; a step of generating a second inverted pattern by expanding the reduced inverted pattern by a third predetermined amount; Generating a dummy original pattern by repeatedly arranging
From the dummy original pattern to the first enlarged wiring pattern and the second
Generating a first dummy pattern by a graphic logical difference operation process of removing an overlapped portion with the inverted pattern of the second dummy pattern. It is preferable that the flattening pattern generating step include a step of generating a flattening pattern by a graphic OR operation for overlapping the first dummy pattern and the second dummy pattern.

According to a fourth flattening pattern generation method according to the present invention, the first flattening pattern is separated from the wiring pattern forming region in the wiring layer by the first predetermined distance or more and the first predetermined distance or more.
A first dummy pattern generation step of generating a first dummy pattern composed of a set of first simple figures in an area within a second predetermined distance larger than a predetermined distance of A second dummy pattern generating step of generating a second dummy pattern comprising a set of second simple figures larger than the first simple figure in an area separated by at least two predetermined distances; A flattening pattern generating step of generating a flattening pattern by combining the dummy pattern with the second dummy pattern.

According to the fourth method for generating a flattening pattern, a first set of simple figures consisting of a first set of simple figures is located in a region apart from a wiring pattern forming region by a first predetermined distance or more and within a second predetermined distance. While a flattening pattern is generated, a second flattening pattern composed of a set of second simple figures larger than the first simple figure is located in an area at least a second predetermined distance from the wiring pattern formation area. Generated.

In the fourth flattening pattern generating method, the first dummy pattern generating step includes a step of expanding the wiring pattern by a first predetermined amount to generate a first enlarged wiring pattern; A step of generating a second enlarged wiring pattern by enlarging by a second predetermined amount larger than the first predetermined amount; a step of inverting the second enlarged wiring pattern to generate an inverted pattern; Generating a first dummy original pattern by repeatedly arranging the first dummy original pattern, and performing a graphic logical difference calculation process of removing an overlapping portion between the first enlarged original wiring pattern and the inverted pattern from the first dummy original pattern; Generating a
The second dummy pattern generation step includes a step of repeatedly arranging a simple figure larger than the simple figure to generate a second dummy original pattern, and leaving only an overlapping portion of the second dummy original pattern with the inverted pattern. Generating a second dummy pattern by a graphic logical product operation process for causing the first dummy pattern and the second dummy pattern to overlap each other. Preferably, the method includes a step of generating a pattern.

According to a fifth aspect of the present invention, there is provided a method for generating a flattening pattern, comprising: From a second wiring pattern formation region in which a second wiring pattern is formed within a second predetermined distance which is larger than the first predetermined distance and which is an upper layer or a lower layer of the first wiring layer. A first dummy pattern generating step of generating a first dummy pattern composed of a set of simple figures in a region of the first wiring layer at a third predetermined distance, and forming a first wiring pattern in the first wiring layer A second dummy pattern formed of at least one graphic larger than a simple graphic in a first wiring layer area separated from the area by a second predetermined distance or more and separated from the second wiring pattern formation area by a third predetermined distance or more; And it includes a second dummy pattern generating step of generating, a flat pattern generating step of generating a first dummy pattern and the flat pattern by synthesizing the second dummy patterns.

According to the fifth method of generating a flattening pattern, the distance from the first wiring pattern formation region to the third wiring is not less than the first predetermined distance and not more than the second predetermined distance, and the third wiring pattern is formed from the second wiring pattern formation region to the third wiring line. A first flattening pattern composed of a set of simple figures is generated in an area within a predetermined distance from the first wiring pattern formation area, and a second wiring pattern formation area separated from the first wiring pattern formation area by a second predetermined distance or more. A second flattening pattern composed of at least one graphic larger than the simple graphic is generated in the area at least a third predetermined distance away from the flat graphic instead of the flattening pattern composed of the set of simple graphics.

In the fifth flattening pattern generating method, the first dummy pattern generating step includes a step of generating a first enlarged wiring pattern by expanding the first wiring pattern by a first predetermined amount; A step of generating a second enlarged wiring pattern by enlarging the second wiring pattern by a second predetermined amount, and a graphic OR operation for overlapping the first enlarged wiring pattern and the second enlarged wiring pattern A step of generating a composite pattern, a step of inverting the composite pattern to generate an inverted pattern, a step of repeatedly arranging simple figures to generate a dummy original pattern, and a first enlarged wiring pattern and an inverted pattern from the dummy original pattern Generating a first dummy pattern by graphic logical difference operation processing for removing an overlapped portion with the first dummy pattern. Generating a second dummy pattern consisting of turns; and the flattening pattern generating step includes generating a flattening pattern by a graphic OR operation for superimposing the first dummy pattern and the second dummy pattern. It is preferable to include

According to a sixth aspect of the present invention, there is provided a method for generating a flattening pattern, wherein the first wiring layer is separated from the first wiring pattern forming region in the first wiring layer where the first wiring pattern is formed by a first predetermined distance or more, 2 and within a third predetermined distance from a second wiring pattern formation region where a second wiring pattern is formed in a second wiring layer that is an upper layer or a lower layer of the first wiring layer. In the region of the first wiring layer, the first
A first dummy pattern generating step of generating a first dummy pattern consisting of a set of simple figures, and a second wiring separated from a first wiring pattern forming region in a first wiring layer by a second predetermined distance or more. A second dummy pattern generating step of generating a second dummy pattern composed of a set of second simple figures larger than the first simple figure in an area at least a third predetermined distance from the pattern formation area; A flattening pattern generating step of generating a flattening pattern by synthesizing the dummy pattern and the second dummy pattern.

According to the sixth flattening pattern generation method, the third wiring pattern forming area is separated from the first wiring pattern forming area by a first predetermined distance or more and within a second predetermined distance and is separated from the second wiring pattern forming area by the third wiring pattern. Area within a predetermined distance of
A first flattening pattern composed of a set of simple figures is generated, while being separated from the first wiring pattern formation region by a second predetermined distance or more and separated from the second wiring pattern formation region by a third predetermined distance or more In the region, a second flattening pattern including a set of second simple figures larger than the first simple figure is generated.

In the sixth flattening pattern generating method, the first dummy pattern generating step includes a step of expanding the first wiring pattern by a first predetermined amount to generate a first enlarged wiring pattern; A step of generating a second enlarged wiring pattern by enlarging the second wiring pattern by a second predetermined amount, and a graphic OR operation for overlapping the first enlarged wiring pattern and the second enlarged wiring pattern A step of generating a combined pattern, a step of inverting the combined pattern to generate an inverted pattern, a step of repeatedly arranging simple figures to generate a first dummy original pattern, and a step of generating a first dummy original pattern from the first dummy original pattern. Generating a first dummy pattern by a graphic logical difference operation process of deleting an overlapping portion between the enlarged wiring pattern and the inverted pattern, and generating a second dummy pattern. The steps are as follows: a step of repeatedly arranging a simple figure larger than the simple figure to generate a second dummy original pattern; and a figure AND operation processing of leaving only an overlapping portion of the second dummy original pattern with the inverted pattern. Generating a second dummy pattern according to
The flattening pattern generating step includes a step of generating a flattening pattern by a graphic OR operation for superimposing the first dummy pattern and the second dummy pattern.

A first flattening pattern generating apparatus according to the present invention comprises: a first graphic enlarging processing means for enlarging a wiring pattern in a wiring layer by a first predetermined amount to generate an enlarged wiring pattern; A dummy original pattern generation processing unit for generating a dummy original pattern by repeatedly arranging the dummy pattern, a graphic logical difference operation processing unit for generating a dummy pattern by removing an overlapping portion of the dummy original pattern with the enlarged wiring pattern, A graphic reduction processing means for reducing the dummy dummy pattern by a second predetermined amount to generate a reduced dummy pattern; and a second graphic expansion processing means for generating a flattened pattern by expanding the reduced dummy pattern by a second predetermined amount. ing.

A second flattening pattern generating apparatus according to the present invention includes a first graphic enlarging processing means for generating an enlarged wiring pattern by enlarging a wiring pattern in a wiring layer by a first predetermined amount; Are repeatedly arranged to generate a first dummy original pattern, and a first dummy pattern is generated by removing an overlapping portion of the first dummy original pattern with the enlarged wiring pattern. Graphic logical difference operation processing means; first graphic reduction processing means for reducing the first dummy pattern by a second predetermined amount to generate a first reduced dummy pattern; And a second figure enlargement processing means for enlarging the second dummy pattern by a predetermined amount, and moving the simple figure constituting the first dummy original pattern in parallel to form the second dummy original pattern. A second dummy original pattern generating unit, a third figure enlarging processing unit for enlarging the second dummy pattern by a third predetermined amount to generate an enlarged dummy pattern, and enlarging the second dummy original pattern. Remove the overlapping part with the wiring pattern and the enlarged dummy pattern
A graphic logical difference operation processing means for generating a dummy pattern, a second graphic reduction processing means for reducing a third dummy pattern by a fourth predetermined amount to generate a second reduced dummy pattern, A fourth figure enlargement processing means for enlarging the reduced dummy pattern by a fourth predetermined amount to generate a fourth dummy pattern; and superimposing the second dummy pattern and the fourth dummy pattern to form a flattened pattern. Graphic OR operation processing means for generating.

A third flattening pattern generating apparatus according to the present invention includes a first figure enlarging processing means for enlarging a wiring pattern in a wiring layer by a first predetermined amount to generate a first enlarged wiring pattern. A second figure enlargement processing means for enlarging the wiring pattern by a second predetermined amount larger than the first predetermined amount to generate a second enlarged wiring pattern, and inverting and inverting the second enlarged wiring pattern Figure inversion processing means for generating a pattern, dummy original pattern generating means for generating a dummy original pattern by repeatedly arranging a simple figure, and removing an overlapping portion of the first enlarged wiring pattern and the inverted pattern from the dummy original pattern. And a pattern OR operation for generating a flattened pattern by superimposing a dummy pattern and an inverted pattern. That.

A fourth flattening pattern generating apparatus according to the present invention includes a first graphic enlarging processing means for enlarging a wiring pattern in a wiring layer by a first predetermined amount to generate a first enlarged wiring pattern. A second figure enlargement processing means for enlarging the wiring pattern by a second predetermined amount larger than the first predetermined amount to generate a second enlarged wiring pattern, and inverting and inverting the second enlarged wiring pattern Figure inversion processing means for generating a pattern, first dummy original pattern generating means for repeatedly arranging a first simple graphic to generate a first dummy original pattern, and a first enlargement from the first dummy original pattern A graphic logical difference operation processing means for generating a first dummy pattern by removing an overlapping portion between the wiring pattern and the inverted pattern, and a second simple graphic which is repeatedly arranged with a second simple graphic larger than the first simple graphic. Second dummy original pattern generating means for generating a dummy original pattern, and graphic AND operation processing means for generating a second dummy pattern by leaving only an overlapping portion of the second dummy original pattern with the inverted pattern; And a graphic OR operation processing means for generating a flattened pattern by superimposing the first dummy pattern and the second dummy pattern.

A fifth flattening pattern generating apparatus according to the present invention expands a first wiring pattern in a first wiring layer by a first predetermined amount to generate a first enlarged wiring pattern. And a second enlargement circuit for generating a second enlarged wiring pattern by enlarging a second wiring pattern in a second wiring layer that is an upper layer or a lower layer of the first wiring layer by a second predetermined amount. Figure enlargement processing means, a figure OR operation processing means for generating a composite pattern by superimposing the first enlarged wiring pattern and the second enlarged wiring pattern, and a figure for generating an inverted pattern by inverting the composite pattern Inversion processing means; dummy original pattern generation means for repeatedly arranging simple figures to generate a dummy original pattern; and removing an overlapping portion of the first enlarged wiring pattern and the inverted pattern from the dummy original pattern. And it includes a graphical logical difference calculation processing means for generating a first dummy pattern, and a graphical logical sum operation means and the first dummy pattern superposing the inverted pattern to produce a flattened pattern.

A sixth flattening pattern generating apparatus according to the present invention expands a first wiring pattern in a first wiring layer by a first predetermined amount to generate a first enlarged wiring pattern. And a second enlargement circuit for generating a second enlarged wiring pattern by enlarging a second wiring pattern in a second wiring layer that is an upper layer or a lower layer of the first wiring layer by a second predetermined amount. Figure enlargement processing means, a figure OR operation processing means for generating a composite pattern by superimposing the first enlarged wiring pattern and the second enlarged wiring pattern, and a figure for generating an inverted pattern by inverting the composite pattern Inversion processing means, first dummy original pattern generation means for repeatedly arranging the first simple figure to generate a first dummy original pattern, and a first enlarged wiring pattern and an inverted pattern from the first dummy original pattern; The first to remove the overlapping portion of the over down 1
And a second dummy original pattern generating means for repeatedly arranging a second simple graphic larger than the first simple graphic to generate a second dummy original pattern. A logical AND operation processing means for generating a second dummy pattern by leaving only an overlapping portion of the second dummy original pattern with the inverted pattern, and overlapping the first dummy pattern and the second dummy pattern; Graphic OR operation processing means for generating a flattening pattern.

A first semiconductor integrated circuit device according to the present invention is characterized in that a wiring pattern formed on a wiring layer on a semiconductor substrate is separated from a wiring pattern on the wiring layer by a first predetermined distance or more and a first predetermined distance or more. Is formed in a region within a second predetermined distance, which is also large, and is formed in a first flattening pattern composed of a set of simple figures and in a region separated from the wiring pattern in the wiring layer by a second predetermined distance or more. ,
A second flattening pattern including at least one figure larger than the simple figure, and an interlayer insulating film formed on the wiring pattern, the first flattening pattern, and the second flattening pattern are provided.

A second semiconductor integrated circuit device according to the present invention comprises a first wiring pattern formed on a first wiring layer on a semiconductor substrate, and a first wiring pattern formed on the first wiring layer on the semiconductor substrate. A second wiring pattern formed on the located second wiring layer; and a second wiring pattern on the first wiring layer, the second wiring pattern being separated from the first wiring pattern by a first predetermined distance or more and larger than the first predetermined distance. A first flattening pattern formed of a set of simple figures and a first flattening pattern formed of a set of simple figures, the first flattening pattern being formed in a region within a predetermined distance and within a third predetermined distance from the second wiring pattern; A third predetermined distance from the wiring pattern and a third distance from the second wiring pattern;
A second flattening pattern formed of at least one figure larger than the simple figure, and a first wiring pattern formed on the first wiring layer, And a second flattening pattern, and an interlayer insulating film formed between the second wiring pattern formed in the second wiring layer.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method for generating a flattening pattern according to the present invention, an apparatus for generating a flattening pattern used in each embodiment, and manufacturing using the method for generating a flattening pattern according to each embodiment A semiconductor integrated circuit device will be described with reference to the drawings.

(First Embodiment) Hereinafter, a method of generating a flattening pattern according to a first embodiment of the present invention will be described with reference to FIG.
(A) to (d), FIGS. 2 (a) to (c), and a flowchart shown in FIG. 28, and a first method used in the method of generating a flattening pattern according to the first embodiment. The flattening pattern generation device will be described with reference to FIG.

First, in step SA1, after inputting a wiring pattern, in step SA2, the wiring pattern shown in FIG.
As shown in (a), a first dummy original pattern 10 which is a figure pattern in which a simple figure, for example, a square is repeatedly arranged.
Generate In this case, the value of the length A of one side of the square constituting the first dummy original pattern 10 is set to a value not less than the minimum value satisfying the rules of the wiring pattern in the semiconductor manufacturing process, and the first dummy The value of the distance a between the rectangles forming the original pattern 10 is set to a value equal to or larger than the minimum value that satisfies the rule of the distance between the wiring patterns in the semiconductor manufacturing process.

Next, in step SA3, the wiring pattern 11 shown in FIG. 1B is enlarged by a predetermined amount B by the graphic enlargement processing means 100 shown in FIG. 35, and the enlarged wiring pattern 12 shown in FIG. Generate In this case, the value of the predetermined amount B is a value of an interval that must be at least satisfied between the wiring pattern 11 and the finally obtained flattening pattern 15 (see FIG. 2B). The enlarged wiring pattern 12 means an area where the flattening pattern 15 is prohibited in the vicinity of the wiring pattern 11.

Next, at step SA4, the figure logical difference calculating means 101 shown in FIG. 35 performs a figure logical difference calculation process for deleting the overlapping portion of the first dummy original pattern 10 with the enlarged wiring pattern 12. , FIG.
A dummy pattern 13 is generated as shown in FIG.

Next, in step SA5, the graphic pattern reduction processing means 102 shown in FIG.
3 is reduced by a predetermined amount C to generate a reduced dummy pattern 14. In this case, the value of the predetermined amount C is 最小 of the minimum value that satisfies the rules of the wiring pattern in the semiconductor manufacturing process, and is smaller than 値 of the value of the length A of one side of the rectangle. Set to a value.

Next, in step SA6, the flattening pattern 15 is generated by enlarging the reduced dummy pattern 14 by a predetermined amount C by the graphic enlargement processing means 103 shown in FIG. The flattening pattern 15 is a pattern obtained by deleting figures that do not satisfy the wiring pattern rules in the semiconductor manufacturing process from the dummy pattern 13.

Next, in step SA7, the graphic OR operation of the wiring pattern 11 and the flattening pattern 15 is performed by the graphic OR operation processing means 104 shown in FIG. Generate such a final pattern.

As described above, according to the first embodiment,
In the step of generating the flattening pattern 15, the dummy pattern 13 is reduced by a predetermined amount C to generate a reduced dummy pattern 14, and then the remaining reduced dummy pattern 14 is expanded by a predetermined amount C to generate the flattening pattern 15. Therefore, the flattening pattern 15 that does not satisfy the wiring pattern rule in the semiconductor manufacturing process is not generated.

Further, the value of the length A of one side of the first dummy original pattern 10 is set to be equal to or larger than the minimum value that satisfies the rule of the wiring pattern in the semiconductor manufacturing process, and the above-described reduction step and enlargement step are performed. Since the size of the flattening pattern 15 can be increased, the number of figures and the data amount of the flattening pattern 15 can be suppressed.

Instead of the first embodiment, after inverting the wiring pattern 11 to generate an inverted wiring pattern, the inverted wiring pattern is reduced by a predetermined amount to generate a reduced inverted wiring pattern. Alternatively, a dummy pattern 13 as shown in FIG. 1D may be generated by performing a logical difference operation of a graphic for removing an overlapping portion with the reduced inverted wiring pattern from the first dummy original pattern 10.

(Second Embodiment) Hereinafter, a method of generating a flattening pattern according to a second embodiment of the present invention will be described with reference to FIGS. 1 (a), 3 (a) to 3 (d), and 4 (a). )-(D),
5A to 5D, 6A to 6D, and 7A.
-(D), FIGS. 8 (a)-(d) and 9 (a)-
(D) and a flowchart of FIGS. 29 and 30. FIG. 36 shows a second flattening pattern generating apparatus used in the flattening pattern generating method according to the second embodiment. It will be described with reference to FIG.

First, after inputting a wiring pattern in step SB1, a first dummy original pattern 10 is generated in step SB2.

Next, in step SB3, FIG.
The first dummy original pattern 10 shown in FIG. 3A is moved by a different amount of movement in the x direction or the y direction, respectively.
FIG. 3B shows the second dummy original pattern 21 shown in FIG.
3D, the fourth dummy original pattern 23 shown in FIG. 3C, and the fifth dummy original pattern 23 shown in FIG.
Are generated respectively. The first to fifth dummy original patterns 10, 21 to 24 are switched and output by the use data switching means 200 shown in FIG.

Next, in step SB4, the wiring pattern 25 shown in FIG. 4A is enlarged by a predetermined amount B by the graphic enlargement processing means 201 shown in FIG. 36, and the enlarged wiring pattern 26 shown in FIG. Is generated, and the generated enlarged wiring pattern 26 is used as the use data switching unit 2 shown in FIG.
02 is output. The value of the predetermined amount B is
And the finally obtained flattening pattern (see FIG. 9D). The enlarged wiring pattern 26 means an area where the placement of the flattening pattern shown in FIG. 9D is prohibited in the vicinity of the wiring pattern 25.

Next, at step SB5, the graphic logical difference operation processing means 203 shown in FIG.
4D, a first dummy pattern 27 as shown in FIG. 4D is generated by performing a logical difference operation of the graphic for removing the overlapping portion with the enlarged wiring pattern 26 from the first dummy original pattern 10 shown in FIG.

Next, in step SB6, the first reduced dummy pattern 27 is generated by reducing the first dummy pattern 27 by a predetermined amount C by the graphic reduction processing means 204 shown in FIG. In this case, the value of the predetermined amount C is の of the minimum value that satisfies the wiring pattern rule in the semiconductor manufacturing process, and is １ ／ of the value of the length A of one side of the rectangle.
Set to a smaller value.

Next, in step SB7, the figure reduction processing means 205 shown in FIG. 36 expands the first reduced dummy pattern 28 by a predetermined amount C to generate a second dummy pattern 29 shown in FIG. 5A. . The second dummy pattern 29 is a pattern obtained by deleting a figure that does not satisfy the wiring pattern rule in the semiconductor manufacturing process from the first dummy pattern 27. The second dummy pattern 29 is output to the use data switching unit 206 and is also processed by the graphic OR operation processing unit 208 via the graphic enlargement processing unit 207.
Is output to

Next, in step SB8, the figure OR operation of the wiring pattern 25 and the second dummy pattern 29 is performed by the figure OR operation processing means 208 shown in FIG. A first pattern obtained by combining the wiring pattern 25 and the second dummy pattern 29 as shown in FIG.
Generate a composite pattern.

Next, in step SB9, the figure enlargement processing means 207 shown in FIG. 36 enlarges the second dummy pattern 29 by a predetermined amount D to generate a first enlarged dummy pattern 30 shown in FIG. 5C. . In this case, the predetermined amount D
9 is the value of the wiring pattern 25 and FIG.
This is the value of the interval that must be at least satisfied with the flattening pattern shown in FIG.

Next, in step SB10, FIG.
The logical OR operation of the graphic of the enlarged wiring pattern 26 and the first enlarged dummy pattern 30 is performed by the graphic OR operation processing means 208 shown in FIG. 5 to form the first enlarged composite pattern 31 as shown in FIG. Generate. The first enlarged composite pattern 31 indicates an area in which placing the flattening pattern shown in FIG. 9D in the vicinity of each of the wiring pattern 25 and the second dummy pattern 29 is prohibited.

Next, in step SB11, FIG.
3 by means of the graphic logical difference operation processing means 203 shown in FIG.
A logical difference calculation process is performed on the graphic to delete the overlapping portion with the first enlarged composite pattern 31 from the second dummy original pattern 21 shown in (a), and the third dummy pattern 32 as shown in FIG. Generate.

Next, in step SB12, FIG.
The second dummy pattern 33 is generated by reducing the third dummy pattern 32 by a predetermined amount D by the graphic reduction processing means 204 shown in FIG.

Next, in step SB13, FIG.
The figure enlargement processing means 205 shown in FIG. 6 expands the second reduced dummy pattern 33 by a predetermined amount D to generate a fourth dummy pattern 34 shown in FIG. The fourth dummy pattern 34 is a pattern obtained by deleting a figure that does not satisfy the wiring pattern rule in the semiconductor manufacturing process from the second dummy pattern 21.

Next, in step SB14, FIG.
5 by the graphic OR operation processing means 208 shown in FIG.
The first combined pattern and the fourth dummy pattern 3 shown in FIG.
4 and the wiring pattern 25 and the second dummy pattern 2 as shown in FIG.
9 and the fourth dummy pattern 34 are combined to generate a second combined pattern.

Next, in step SB15, FIG.
The fourth dummy pattern 34 is enlarged by a predetermined amount D by the graphic enlargement processing means 207 shown in FIG.
After generating the enlarged dummy pattern 35, step SB1
In FIG. 6, the logical OR operation of the figure of the enlarged wiring pattern 26 and the second enlarged dummy pattern 35 is performed, and FIG.
A second enlarged composite pattern 36 as shown in FIG.

Next, in step SB17, FIG.
3 by means of the graphic logical difference operation processing means 203 shown in FIG.
By performing a logical difference operation of a graphic for removing an overlapping portion with the second enlarged composite pattern 36 from the third dummy original pattern 22 shown in FIG. 7B, a fifth dummy pattern 37 as shown in FIG. Generate.

Next, in step SB18, FIG.
The third reduced dummy pattern 38 is generated by reducing the fifth dummy pattern 37 by a predetermined amount C by the graphic reduction processing means 204 shown in FIG.

Next, in step SB19, FIG.
The third reduced dummy pattern 38 is enlarged by a predetermined amount C by the graphic enlargement processing means 205 shown in FIG. 8 to generate a sixth dummy pattern 39 shown in FIG.

Next, in step SB20, FIG.
6 is performed by the graphic OR operation processing means 208 shown in FIG.
The second combined pattern and the sixth dummy pattern 3 shown in FIG.
9 and a wiring pattern 25 and a second dummy pattern 29 as shown in FIG.
And the fourth dummy pattern 34 and the sixth dummy pattern 39 to generate a third combined pattern.

Next, in step SB21, FIG.
The sixth dummy pattern 39 is enlarged by a predetermined amount D by the graphic enlargement processing means 207 shown in FIG.
After generating the enlarged dummy pattern 40, step SB2
2, the figure OR operation processing means 20 shown in FIG.
8, the logical OR operation of the figure of the enlarged wiring pattern 26 and the third enlarged dummy pattern 40 is performed, and FIG.
A third enlarged composite pattern 41 as shown in (d) is generated.

Next, in step SB23, FIG.
3 by means of the graphic logical difference operation processing means 203 shown in FIG.
A logical difference operation is performed on the graphic for deleting the overlapping portion with the third enlarged composite pattern 41 from the fourth dummy original pattern 23 shown in (c), and the seventh dummy pattern 42 as shown in FIG. Generate

Next, in step SB24, FIG.
The fourth reduced dummy pattern 43 is generated by reducing the seventh dummy pattern 42 by a predetermined amount C by the graphic reduction processing means 204 shown in FIG.

Next, in step SB25, FIG.
The enlargement processing unit 205 shown in FIG. 9 enlarges the fourth reduced dummy pattern 43 by a predetermined amount C to generate an eighth dummy pattern 44 shown in FIG. 9C.

Next, in step SB26, FIG.
8 is performed by the graphic OR operation processing means 209 shown in FIG.
The third combined pattern and the eighth dummy pattern 4 shown in FIG.
4 is performed, and a wiring pattern 25 and a second dummy pattern 29 as shown in FIG.
And the fourth dummy pattern 34, the sixth dummy pattern 39, and the eighth dummy pattern 44 to generate a fourth combined pattern. This fourth synthetic pattern is shown in FIG.
3A, the second dummy original pattern 21 shown in FIG. 3A, the third dummy original pattern 22 shown in FIG. 3B, and the fourth dummy original pattern 2 shown in FIG.
3 is a final flattening pattern generated based on No. 3, but it is also possible to generate a flattening pattern taking into account the fifth dummy original pattern 23 shown in FIG. .

As described above, according to the second embodiment,
As in the first embodiment, a flattening pattern that does not satisfy the rules of the wiring pattern in the semiconductor manufacturing process is not generated. According to the second embodiment, in addition to the first dummy original pattern 10, The first dummy original pattern 1
In order to form a flattening pattern using the second to fourth dummy original patterns 21 to 23 obtained by translating 0,
Since the size of the simple figure constituting the flattening pattern is larger than in the first embodiment, the number of figures and the data amount of the flattening pattern can be suppressed.

Further, according to the second embodiment, first to
Since the flattening pattern is formed using the fourth dummy original patterns 10, 21 to 23, the area that cannot be filled with the flattening pattern between the wiring patterns can be reduced as compared with the first embodiment. A flattening pattern that satisfies the above required flatness of the wiring layer can be formed.

(Third Embodiment) Hereinafter, a method of generating a flattening pattern according to a third embodiment of the present invention will be described with reference to FIG.
0 (a) (b), FIGS. 11 (a) (b) and 12 (a)
(B) and a flow chart of FIG. 31, and a third flattening pattern generating apparatus used in the flattening pattern generating method according to the third embodiment will be described with reference to FIG. I do.

The first to fifth dummy original patterns 1 described above
0, 21 to 24 are switched and output by the use data switching means 300 shown in FIG.
In the third embodiment, the first dummy original pattern 1
A case where 0 is used will be described.

First, after inputting a wiring pattern in step SC1, a first dummy original pattern 10 is generated in step SC2.

Next, in step SC3, the figure enlargement processing means 301 shown in FIG. 37 enlarges the wiring pattern 50 shown in FIG.
The first enlarged wiring pattern 51 shown in FIG. In this case, the value of the predetermined amount B is a value of an interval that must be at least satisfied between the wiring pattern 50 and the finally obtained flattening pattern (see FIG. 12B). First
The enlarged wiring pattern 51 means a region where the placement of a flattening pattern is prohibited in the vicinity of the wiring pattern 50.

Next, in step SC4, the figure enlargement processing means 302 shown in FIG. 37 enlarges the wiring pattern 50 shown in FIG.
A second enlarged wiring pattern 52 shown in FIG. The value of the predetermined amount E is the value of the size A of one side of a rectangle, which is a simple figure of the first dummy original pattern 10 used in the first embodiment, the value of the distance a between the rectangles, and the vicinity of the wiring pattern 50. Is greater than or equal to the sum of the value of the predetermined amount B, which is the width of the area where the flattening pattern is prohibited.

Next, in step SC5, the figure inversion processing means 303 shown in FIG.
An inverted pattern 53 shown in FIG. 11B is generated.

Next, in step SC6, the graphic OR operation of the graphic of the first enlarged wiring pattern 51 and the inverted pattern 53 is performed by the graphic OR operation processing means 304 shown in FIG. Is generated. This composite pattern indicates an area in which the placement of the flattening pattern including the first dummy original pattern 10 is prohibited in an area near the wiring pattern 50. The composite pattern shown in FIG. 12A is output to the graphic logical difference calculation processing means 305 shown in FIG. 37 via the use data switching means 305 shown in FIG.

Next, in step SC7, the graphic logical difference operation processing means 305 shown in FIG.
A logical difference calculation process is performed on the first dummy original pattern 10 shown in FIG. 12A to delete the overlapping portion with the composite pattern shown in FIG. 12A, and the obtained graphic pattern is shown in FIG.
The graphic reduction processing means 306 and the graphic enlargement processing means 30 shown in FIG.
7 and to the graphic logical sum operation processing means 309 via the use data switching means 308.

Next, in step SC 7, the graphic OR operation processing means 309 shown in FIG.
12A, and a logical sum operation of the graphic pattern obtained by the logical difference operation processing of the graphic in which the overlapping portion with the combined pattern shown in FIG. 12A is deleted from the dummy original pattern 10 and the wiring pattern 50 and the inverted pattern 53 By performing the processing, a final flattening pattern shown in FIG.

The graphic reduction processing means 30 shown in FIG.
6, figure enlargement processing means 307, use data switching means 3
10, the graphic OR operation processing means 311 and the graphic enlargement processing means 312 are not used in the third embodiment, but the graphic reduction processing means 204, the graphic enlargement processing means 205 and the used data switching means shown in FIG. 202, the graphic OR operation processing means 208, and the graphic enlargement processing means 207 have the same functions.

As described above, according to the third embodiment,
Since a flattening pattern composed of a plane pattern corresponding to the inverted pattern 53 is formed in a region other than the vicinity of the wiring pattern 50, the number of figures and data of the flattening pattern are smaller than when a flattening pattern composed of simple figures is formed. The amount can be suppressed.

Instead of the third embodiment, after inverting the wiring pattern 50 to generate an inverted pattern, the inverted pattern is reduced by a predetermined amount to generate a reduced inverted pattern. The dummy pattern obtained by the graphic logical difference operation processing for removing the overlapping portion between the original enlarged wiring pattern 51 and the reduced inversion pattern from the original pattern 10 and the reduced inversion pattern are subjected to graphic OR operation processing and flattened. A pattern may be generated, or a second inverted wiring pattern 52 is inverted to generate a first inverted pattern, and then the first inverted pattern is reduced by a predetermined amount to generate a reduced inverted pattern. Thereafter, the reduced inverted pattern is enlarged by a predetermined amount to generate a second inverted pattern, and then the first enlarged wiring pattern 52 A flattening pattern may be generated by performing a graphic OR operation on the dummy pattern obtained by the graphic logical difference operation processing for removing an overlapping portion with the second inverted pattern and the second inverted pattern. .

(Fourth Embodiment) Hereinafter, a method for generating a flattening pattern according to a fourth embodiment of the present invention will be described with reference to FIG.
3 (a) (b) and FIGS. 14 (a) (b) and a flowchart shown in FIG. 32, and a fourth method used in the method of generating a flattening pattern according to the fourth embodiment. The flattening pattern generation device will be described with reference to FIG.

The first to fifth dummy original patterns 1 described above
0, 21 to 24 are switched and output by the use data switching means 400 shown in FIG.
In the fourth embodiment, the first dummy original pattern 1
A case where 0 is used will be described.

First, in step SD1, after inputting a wiring pattern, in step SD2, a first dummy original pattern 10 is generated, and a simple figure larger than the simple figure of the first dummy original pattern 10, for example, a square. The sixth dummy pattern 55 shown in FIG.
Generate

Next, as in the third embodiment, FIG.
8 is performed by the graphic enlargement processing means 401 shown in FIG.
In FIG. 3, after the wiring pattern 50 shown in FIG. 10A is enlarged by a predetermined amount B to generate a first enlarged wiring pattern 51 shown in FIG. 10B, the graphic enlargement processing means 402 shown in FIG. In step SD4, the wiring pattern 50 is enlarged by a predetermined amount to obtain a second enlarged wiring pattern 52.
Then, in step SD5, the second enlarged wiring pattern 52 is inverted by the graphic inversion processing means 403 shown in FIG. 38, and the inverted pattern 5 shown in FIG.
3 is generated.

Next, at step SD6, the graphic logical difference operation processing means 404 shown in FIG. 38 converts the sixth dummy pattern 55 into the inverted pattern 53 shown in FIG.
13 (b) by performing a logical difference operation of the graphic for removing the overlapping portion with the seventh dummy pattern 5 as shown in FIG.
6 is generated.

Next, in step SD7, the figure OR operation of the figure between the seventh dummy pattern 56 and the first enlarged wiring pattern 51 shown in FIG. And FIG. 14
A composite pattern as shown in FIG. FIG.
The composite pattern of (a) shows an area in which placing of the flattening pattern generated from the first dummy original pattern 10 in the vicinity of the wiring pattern 50 shown in FIG. 10A is prohibited. The combined pattern shown in FIG. 14A is transmitted through the use data switching unit 406 shown in FIG.
Are output to the graphic logical difference operation processing means 407 shown in FIG.

Next, at step SD8, the graphic logical difference operation processing means 407 shown in FIG.
A logical difference operation is performed on the first dummy original pattern 10 shown in FIG. 38 to remove the overlapping portion with the combined pattern shown in FIG. 14A, and the resulting graphic pattern is obtained as shown in FIG.
Graphic reduction processing means 408 and graphic enlargement processing means 40 shown in FIG.
9 and output to the graphic OR operation processing means 411 via the use data switching means 410.

Next, at step SD8, the graphic OR operation processing means 411 shown in FIG.
14A, a graphic pattern obtained by performing a logical difference operation of a graphic for removing an overlapping portion with the combined pattern shown in FIG. 14A, a graphic of the wiring pattern 50 and a graphic of the seventh dummy pattern 56. An OR operation is performed to generate a final flattened pattern shown in FIG.

The graphic reduction processing means 40 shown in FIG.
8, the graphic enlargement processing means 409, the graphic OR operation processing means 412, and the graphic enlargement processing means 413 are not used in the fourth embodiment. 205, the graphic OR operation processing means 208 and the graphic enlargement processing means 207 have the same functions.

As described above, according to the fourth embodiment,
In a region other than the vicinity of the wiring pattern 50, a flattening pattern is generated by the sixth dummy original pattern 55 composed of a simple figure larger than the simple figure of the first dummy original pattern 10. Compared to the case where the first dummy original pattern 10 is used, the number of figures and the data amount of the flattened pattern can be suppressed. In this case, since the planar pattern is not formed in the region other than the vicinity of the wiring pattern 50 as in the third embodiment, the upper surface or the lower wiring layer of the wiring layer on which the wiring pattern 50 is formed is planarized. An increase in parasitic capacitance due to the pattern can be suppressed. That is, it is possible to achieve both a reduction in the number of figures and the amount of data of the flattening pattern and a suppression of an increase in the parasitic capacitance in the upper or lower wiring layer.

(Fifth Embodiment) Hereinafter, a method of generating a flattening pattern according to a fifth embodiment of the present invention will be described with reference to FIG.
5 (a) (b), FIGS. 16 (a) (b) and 17 (a)
(B) and a flow chart of FIG. 33, and a fifth flattening pattern generating apparatus used in the flattening pattern generating method according to the fifth embodiment will be described with reference to FIG. I do.

FIG. 15A shows a wiring pattern 50 as a first wiring pattern for generating a flattening pattern,
A second-layer wiring pattern 60 as a second wiring pattern formed on an upper or lower wiring layer of the wiring pattern 50 is shown.

The above-described first to fifth dummy original patterns 1
0, 21 to 24 are switched and output by the use data switching means 500 shown in FIG.
In the fifth embodiment, the first dummy original pattern 1
A case where 0 is used will be described.

First, in step SE1, the wiring pattern 50 and the other-layer wiring pattern 60 are output, and then in step SE2, the first dummy original pattern 10 is generated.

Next, in step SE3, the other-layer wiring pattern 60 is enlarged by a predetermined amount F by the graphic enlargement processing means 501 shown in FIG. 39, and the third enlarged wiring pattern 61 shown in FIG. The first enlarged wiring pattern 51 and the second enlarged wiring pattern 52 appear first here, but are referred to as a third enlarged wiring pattern for the sake of convenience. The third enlarged wiring pattern 61 indicates a region where a flattening pattern for suppressing an increase in the parasitic capacitance of the other layer wiring pattern 60 is generated. Therefore, the value of the predetermined amount F is set to a value that can secure an area for suppressing an increase in the parasitic capacitance of the other layer wiring pattern 60 by generating a flattening pattern near the other layer wiring pattern 60.

Next, at step SE4, the wiring pattern 50 is enlarged by a predetermined amount E by the graphic enlargement processing means 502 shown in FIG. The two enlarged wiring patterns 52 are generated.

Next, in step SE5, the graphic OR operation of the graphic of the third enlarged wiring pattern 61 and the second enlarged wiring pattern 52 is performed by the graphic OR operation processing means 503 shown in FIG. A first combined pattern as shown in FIG. 16A is generated.

Next, at step SE6, the first combined pattern shown in FIG. 16A is graphically inverted by the graphic inversion processing means 504 shown in FIG.
An inverted pattern 62 shown in (b) is generated.

Next, at step SE7, the pattern enlargement processing means 505 shown in FIG. 39 enlarges the wiring pattern 50 shown in FIG. 10A by a predetermined amount B in the same manner as in the third embodiment. The first enlarged wiring pattern 51 shown in FIG.

Next, at step SE8, the inverted pattern 62 and the first enlarged wiring pattern 5 shown in FIG.
By performing a logical OR operation on the figure with 1 in FIG.
Is generated. The second composite pattern indicates a region where the placement of the flattening pattern including the first dummy original pattern 10 in the vicinity of the wiring pattern 50 is prohibited. The second combined pattern is output to the graphic logical difference processing means 508 via the use data switching means 507 shown in FIG.

Next, in step SE8, the graphic logical difference operation processing means 508 shown in FIG.
FIG. 4A is a diagram showing a logical difference calculation process of a graphic for removing an overlapping portion with the first enlarged wiring pattern 51 from the first dummy original pattern 10 shown in FIG.
0, figure enlargement processing means 5
The data is output to the graphic logical sum operation processing means 512 via the reference numeral 10 and the use data switching means 511.

Next, in step SE9, the graphic OR operation processing means 512 shown in FIG. 39 determines the overlapping portion between the first dummy original pattern 10 and the first enlarged wiring pattern 51 shown in FIG. The logical OR operation of the graphic pattern obtained by performing the logical difference operation processing of the graphic to be deleted and the first wiring pattern 50 and the inverted pattern 62 is performed, and the final OR operation is performed as shown in FIG. And generate a smooth flattening pattern.

The graphic reduction processing means 50 shown in FIG.
9, figure enlargement processing means 510, figure enlargement processing means 513
The graphic OR operation processing means 514 is not used in the fifth embodiment, but the graphic reduction processing means 204, the graphic enlargement processing means 205, the graphic enlargement processing means 207, and the graphic OR operation processing shown in FIG. Each of the means 208 has the same function.

As described above, according to the fifth embodiment,
In a region other than the vicinity of the wiring pattern 50 and in a region other than the vicinity of the other upper layer wiring pattern 60 or the lower layer, a planarization pattern composed of a plane pattern corresponding to the inversion pattern 62 is formed, thereby suppressing an increase in parasitic capacitance. While reducing the number of figures and the amount of data of the flattening pattern.

(Sixth Embodiment) Hereinafter, a method of generating a flattening pattern according to a sixth embodiment of the present invention will be described with reference to FIG.
8 (a) and (b) and a flow chart of FIG. 19 and FIG. 33, and a sixth flattening pattern generating apparatus used in the flattening pattern generating method according to the sixth embodiment. This will be described with reference to FIG.

The above-mentioned first to fifth dummy original patterns 1
0, 21 to 24 are switched and output by the use data switching means 600 shown in FIG.
In the sixth embodiment, the first dummy original pattern 1
A case where 0 is used will be described.

First, in step SF1, the wiring pattern 50 and the other-layer wiring pattern 60 are input, and then in step SF2, the first dummy original pattern 10 is generated.

Next, at step SF3, the pattern enlargement means 601 shown in FIG. 40 enlarges the wiring pattern 50 shown in FIG. 10A by a predetermined amount B in the same manner as in the third embodiment. The first enlarged wiring pattern 51 shown in FIG.

Next, in step SF4, the other-layer wiring pattern 60 is enlarged by a predetermined amount F by the graphic enlargement processing means 602 shown in FIG. 40, as in the fifth embodiment, and is shown in FIG. A third enlarged wiring pattern 61 is generated.

Next, in step SF5, the pattern enlargement unit 603 shown in FIG. 40 enlarges the wiring pattern 50 by a predetermined amount E in the same manner as in the third embodiment.
A second enlarged wiring pattern 52 shown in FIG.

Next, in step SF6, the figure logical sum operation processing means 604 shown in FIG. 40 performs the processing of the figure of the third enlarged wiring pattern 61 and the second enlarged wiring pattern 52 similarly to the fifth embodiment. To generate a first composite pattern as shown in FIG.

Next, in step SF7, the graphic logical difference operation processing means 605 shown in FIG.
FIG. 18A shows a logical difference operation of a graphic in which a graphic overlapping the first combined pattern shown in FIG. 16A is deleted from the large rectangular dummy pattern 55 shown in FIG. An eighth dummy pattern 70 is generated.

Next, in step SF8, the first enlarged wiring pattern 51 shown in FIG. 10B and the eighth dummy pattern 70 shown in FIG. By performing a logical OR operation of the figure with the above, a second composite pattern shown in FIG. 18B is generated. The second composite pattern is processed by the graphic logical difference processing means 60 through the use data switching means 607 shown in FIG.
8 is output.

Next, in step SF9, the graphic logical difference calculation processing means 608 shown in FIG.
40, a logical difference calculation process is performed on the graphic to delete the overlapping portion with the first enlarged wiring pattern 51 from the wiring pattern 10 shown in FIG. The data is output to the graphic OR operation processing means 612 via the data processing means 610 and the use data switching means 611.

Next, in step SF9, the figure OR operation processing means 612 shown in FIG.
A graphic pattern obtained by performing a logical difference operation of a graphic for removing an overlapping portion with the first enlarged wiring pattern 51 from the wiring pattern 10 shown in FIG. The final flattening pattern as shown in FIG. 19 is generated by performing a logical OR operation of the figure 70.

The graphic reduction processing means 60 shown in FIG.
9, the graphic enlargement processing means 610, the graphic OR operation processing means 613, and the graphic enlargement processing means 614 are not used in the sixth embodiment. 205, the graphic OR operation processing means 208 and the graphic enlargement processing means 207 have the same functions.

As described above, according to the sixth embodiment,
In a region other than the vicinity of the wiring pattern 50 and in a region other than the vicinity of the upper-layer or lower-layer other-layer wiring pattern 60, the sixth dummy original pattern 55 composed of a simple figure larger than the simple figure of the first dummy original pattern 10 Since such a flattening pattern is formed, it is possible to further achieve both a reduction in the number of figures and data amount of the flattening pattern and a suppression of an increase in parasitic capacitance.

In the first to sixth embodiments described above, a square is used as a simple figure, but a pattern such as a triangle, a circle, a polygon, a stripe, or a grid is used instead. It is possible to use.

(Seventh Embodiment) Hereinafter, a semiconductor integrated circuit device according to a seventh embodiment of the present invention will be described with reference to FIG.
Description will be made with reference to (a) and (b).

FIG. 20A shows a planar structure of a semiconductor integrated circuit device according to the seventh embodiment, and FIG.
The cross-sectional structure along the line XX in FIG. The semiconductor integrated circuit device includes a wiring pattern 81 formed in a wiring layer on a semiconductor substrate 80 and a second predetermined distance that is at least a first predetermined distance from the wiring pattern 81 in the wiring layer and is greater than the first predetermined distance. A first flattening pattern 82 formed of a set of simple figures, for example, squares, and a second predetermined distance or more from the wiring pattern 81 in the wiring layer; A second flattening pattern 83 composed of a planar figure and an interlayer insulating film 84 formed over the entire surface on the wiring pattern 81, the first flattening pattern 82, and the second flattening pattern 83. Although not shown, an upper layer wiring pattern is formed on the interlayer insulating film 84.

According to the seventh embodiment, since the first flattening pattern 82 and the second flattening pattern 83 are formed in the area of the wiring layer where the wiring pattern 81 is not formed, the interlayer insulating film is formed. The upper surface of the film 84 is substantially flat. Further, since the second flattening pattern 83 formed of a planar figure is formed in a region separated from the wiring pattern 81 by a second predetermined distance or more, the first flattening pattern 83 formed of a set of simple figures is formed. Compared with 82, the number of figures and the amount of data can be reduced.

Hereinafter, a first manufacturing method of the semiconductor integrated circuit device according to the seventh embodiment will be described with reference to FIGS.
This will be described with reference to FIG. In addition, FIG.
(C) corresponds to the cross section taken along line XX in FIG. 20 (a).

First, as shown in FIG. 21A, a wiring pattern 81 is formed on a semiconductor substrate 80,
A first flattening pattern 82 and a second flattening pattern 83 are formed by using the flattening pattern generation method according to the third embodiment.

Next, as shown in FIG. 21B, an interlayer insulating film 84 is formed over the entire surface of the wiring pattern 81, the first flattening pattern 82, and the second flattening pattern 83. As described above, the upper surface of the interlayer insulating film 84 is substantially flat, but when viewed from a microscopic view, the upper surface of the interlayer insulating film 84 has the wiring pattern 81 and the first planarization pattern below the interlayer insulating film 84. There is a slight unevenness between a portion where the second flattening pattern 83 exists or a portion where the second flattening pattern 83 does not exist.

Next, the upper portion 84a of the interlayer insulating film 84 is
Polishing is performed by a P (Chemical Mechanical Polish) device to completely flatten the upper surface of the interlayer insulating film 84 as shown in FIG. Thereafter, although not shown, an upper wiring pattern is formed on the planarized interlayer insulating film 84.

Hereinafter, in order to evaluate the first method of manufacturing a semiconductor integrated circuit device according to the seventh embodiment, a method of manufacturing a conventional semiconductor integrated circuit device will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 43A, a wiring pattern 91 is formed on a semiconductor substrate 90, and then, as shown in FIG.
As shown in (b), an interlayer insulating film 92 is formed on the wiring pattern 91. By doing so, the interlayer insulating film 92
Are formed on the upper surface according to the presence or absence of the wiring pattern 91. Thereafter, as shown in FIG. 43C, when the surface portion 92a of the interlayer insulating film 92 is polished by a CMP device, the polishing rate for the interlayer insulating film 92 varies depending on the presence or absence of the wiring pattern 91. Despite this, irregularities remain on the upper surface of the polishing interlayer insulating film 92.

On the other hand, according to the first manufacturing method of the semiconductor integrated circuit device according to the seventh embodiment, the first flattening pattern 82 and the second flattening pattern are formed on the wiring layer of the semiconductor substrate 80. Since the upper surface of the interlayer insulating film 84 is formed almost flat, the interlayer insulating film 8 after the CMP is performed.
The top surface of 4 is completely flat.

Hereinafter, a second method of manufacturing the semiconductor integrated circuit device according to the seventh embodiment will be described with reference to FIGS.
This will be described with reference to FIG. In addition, FIG.
(D) corresponds to the cross section taken along line XX in FIG.

First, as shown in FIG. 22A, a wiring pattern 81 is formed on a semiconductor substrate 80,
A first flattening pattern 82 and a second flattening pattern 83 are formed by using the flattening pattern generation method according to the third embodiment.

Next, as shown in FIG. 22B, an interlayer insulating film 84 is formed on the entire surface of the wiring pattern 81, the first flattening pattern 82, and the second flattening pattern 83. As described above, the upper surface of the interlayer insulating film 84 is substantially flat, but when viewed from a microscopic view, the upper surface of the interlayer insulating film 84 has the wiring pattern 81 and the first planarization pattern below the interlayer insulating film 84. There is a slight unevenness between a portion where the second flattening pattern 83 exists or a portion where the second flattening pattern 83 does not exist.

Next, a viscous resin 85 is applied on the interlayer insulating film 84 so that the surface becomes flat.

Next, the upper portions of the resin 85 and the interlayer insulating film 84 are removed by an etch-back method, and the upper surface of the interlayer insulating film 84 is completely flattened as shown in FIG. Thereafter, although not shown, the planarized interlayer insulating film 84 is formed.
An upper wiring pattern is formed thereon.

Hereinafter, a third method of manufacturing the semiconductor integrated circuit device according to the seventh embodiment will be described with reference to FIGS.
This will be described with reference to FIG. In addition, FIG.
(D) corresponds to the cross section taken along line XX in FIG.

First, as shown in FIG. 23A, a wiring pattern 81 is formed on a semiconductor substrate 80, and then, as shown in FIG.
As shown in (b), an interlayer insulating film 84 is formed over the entire surface of the wiring pattern 81. In this manner, a protrusion 84b is formed in a region where the wiring pattern 81 exists below the interlayer insulating film 84.

Next, as shown in FIG. 23 (c), on the interlayer insulating film 84, using a method for generating a flattening pattern according to the third embodiment, a second material made of a material different from that of the wiring pattern 81 is used. A first flattening pattern 82 and a second flattening pattern 83 are formed. Since the first flattening pattern 82 and the second flattening pattern 83 are separated from the wiring pattern 81 by the first and second predetermined distances, respectively, the region where the convex portion 84b is not formed in the interlayer insulating film 84 is formed. Formed.

Next, the first flattening pattern 82, the second flattening pattern 83, and the projections 84b of the interlayer insulating film 84 are polished by a CMP apparatus, and as shown in FIG. The upper surface of the film 84 is completely flattened. Thereafter, although not shown, an upper wiring pattern is formed on the planarized interlayer insulating film 84.

Hereinafter, a fourth method of manufacturing the semiconductor integrated circuit device according to the seventh embodiment will be described with reference to FIGS.
This will be described with reference to FIG. In addition, FIG.
(D) corresponds to the cross section taken along line XX in FIG.

First, as shown in FIG. 24A, a wiring pattern 81 is formed on a semiconductor substrate 80, and then, as shown in FIG.
As shown in (b), a lower interlayer insulating film 84A is formed over the entire surface of the wiring pattern 81. In this manner, a protrusion 84b is formed in a region where the wiring pattern 81 exists below the lower interlayer insulating film 84A.

Next, as shown in FIG. 24C, the first flattening pattern 82 is formed on the lower interlayer insulating film 84A by using the flattening pattern generation method according to the third embodiment.
And a second flattening pattern 83 is formed. The first flattening pattern 82 and the second flattening pattern 83 are separated from the wiring pattern 81 by the first and second predetermined distances, respectively, so that the convex portions 84b in the lower interlayer insulating film 84A are formed. Not formed in the area.

Next, an upper interlayer insulating film 84B is deposited over the entire surface of the first flattening pattern 82, the second flattening pattern 83, and the lower interlayer insulating film 84A. In this case, since the first planarization pattern 82 and the second planarization pattern 83 are formed in the region where the protrusion 84b is not formed in the lower interlayer insulating film 84A, the upper interlayer insulating film 84A is formed. The top surface of 84B is substantially flat.

Thereafter, although not shown, an upper wiring pattern is formed on the substantially flat upper interlayer insulating film 84B.

(Eighth Embodiment) Hereinafter, a semiconductor integrated circuit device according to an eighth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. 26 and 27.

FIG. 25 shows a plan structure of a semiconductor integrated circuit device according to the eighth embodiment. The semiconductor integrated circuit device has a first wiring formed on a first wiring layer on a semiconductor substrate 80. It includes a pattern 81 and a second wiring pattern 86 formed on a second wiring layer located above or below the first wiring layer. FIG. 26 shows that the second wiring layer is the first wiring layer.
YY in FIG. 25 in the case where the
FIG. 27 shows a cross-sectional structure taken along line YY in FIG. 25 when the second wiring layer is located above the first wiring layer.

In the first wiring layer, the first wiring pattern is separated from the first wiring pattern 81 by a first predetermined distance or more and is within a second predetermined distance larger than the first predetermined distance, and the second wiring pattern 86 The first flattening pattern 82 composed of a set of simple figures
Are formed. Further, the second wiring pattern is separated from the first wiring pattern 81 in the first wiring layer by a second predetermined distance or more, and
A second flattening pattern 83 composed of a plurality of figures larger than a simple figure is formed in a region separated from the wiring pattern 86 by a third predetermined distance or more.

The first wiring pattern 81, the first flattening pattern 82, the second flattening pattern 83 formed on the first wiring layer, and the second wiring pattern 81 formed on the second wiring layer, respectively. Between the wiring pattern 86 and the interlayer insulating film 8
4 are formed.

In the method of manufacturing the semiconductor integrated circuit device according to the eighth embodiment, the first flattening pattern 8 is formed by using the flattening pattern generating method according to the fifth embodiment.
The steps other than forming the second and second flattening patterns 83 are well-known, and thus description thereof is omitted.

In the semiconductor integrated circuit device according to the seventh embodiment, the method for generating a flattened pattern according to the third embodiment is used. In the method for manufacturing a semiconductor integrated circuit device according to the eighth embodiment, Although the method for generating a flattening pattern according to the fifth embodiment is used, the first
Needless to say, a flattening pattern may be formed by appropriately using the method for generating a flattening pattern according to the fifth to fifth embodiments.

[0158]

According to the first method for generating a flattening pattern, the flattening pattern is composed of only simple figures having a predetermined size or more. A flattening pattern that does not satisfy the rule of the above wiring pattern can be prevented from being generated, and the number of simple figures constituting the flattening pattern and the data amount can be reduced.

In the first method for generating a flattening pattern, when a dummy pattern is generated by deleting an overlapping portion with an enlarged wiring pattern obtained by enlarging a wiring pattern by a first predetermined amount from a dummy original pattern, A dummy pattern composed of a set of simple figures can be reliably generated in a region at least a predetermined distance from a wiring pattern formation region where a wiring pattern is formed. In addition, the dummy pattern is
After a reduced dummy pattern is generated by reducing the reduced dummy pattern by a predetermined amount, the flattened pattern is generated by expanding the reduced dummy pattern by a second predetermined amount. It can be surely reduced.

In the first method for generating a flattening pattern, a reduced inverted wiring pattern obtained by reducing an inverted wiring pattern formed by graphically inverting a wiring pattern among dummy original patterns by a first predetermined amount is used. When the dummy pattern is generated by leaving only the overlapping portion of the dummy pattern, a dummy pattern composed of a set of simple figures can be reliably generated in a region at least a predetermined distance from the wiring pattern formation region where the wiring pattern is formed. Further, after the reduced dummy pattern is generated by reducing the dummy pattern by the second predetermined amount and then the reduced dummy pattern is expanded by the second predetermined amount to generate the flattening pattern, the simple pattern forming the flattening pattern is obtained. The number of figures and the amount of data can be reliably reduced.

According to the second flattening pattern generation method, similarly to the first flattening pattern generation method, the number of simple figures constituting the flattening pattern and the data amount can be reduced. Since the flattening pattern is formed by using the second dummy original pattern in addition to the first dummy original pattern, a region that is not filled with the flattening pattern between the wiring patterns can be reduced, which is required in the process. A flattening pattern that satisfies the flatness of the wiring layer can be formed.

In the second flattening pattern generation method, the wiring pattern is enlarged by a first predetermined amount from the second dummy original pattern obtained by translating the simple figure constituting the first dummy original pattern in parallel. When a fourth dummy pattern is generated by deleting an overlapping portion between the enlarged wiring pattern formed and the first dummy pattern formed of the first dummy original pattern and the enlarged dummy pattern formed by being enlarged by the second predetermined amount, A region between the wiring patterns that cannot be filled with the flattening pattern made of the first dummy original pattern can be filled with the second dummy original pattern.

According to the third method for generating a flattening pattern, an area at least a second predetermined distance from the wiring pattern forming area is replaced with at least one larger than the simple figure instead of the flattening pattern consisting of the simple figure. Since a flattening pattern composed of figures is generated, the number of figures and the amount of data of the flattening pattern can be reduced as compared with a case where a flattening pattern is formed only by a set of simple figures.

In the third flattening pattern generation method, the first enlarged wiring pattern and the wiring pattern obtained by expanding the wiring pattern from the dummy original pattern by the first predetermined amount are expanded by the second predetermined amount. When the first dummy pattern is generated by removing the overlapping portion with the inverted pattern obtained by inverting the second enlarged wiring pattern formed, the first dummy pattern is separated from the wiring pattern by a first predetermined distance or more. It is possible to reliably generate the first pattern composed of a set of simple figures in an area within a second predetermined distance larger than the first pattern. Further, when the second dummy pattern is generated by using the inverted pattern, it is possible to surely generate a flattening pattern including at least one figure larger than the simple figure in an area at least a second predetermined distance from the wiring pattern formation area. Can be.

In the third method of generating a flattening pattern, a first enlarged wiring pattern obtained by enlarging a wiring pattern by a first predetermined amount and an inverted pattern obtained by inverting the wiring pattern are extracted from the dummy original pattern. When a first dummy pattern is generated by removing an overlapping portion with a reduced inversion pattern obtained by reducing by a second predetermined amount, the first dummy pattern is separated from the wiring pattern formation region by a first predetermined distance or more and a first predetermined distance or more. It is possible to reliably generate the first pattern composed of a set of simple figures in an area within the second predetermined distance, which is also large. Further, when the second dummy pattern is generated by the reduced inversion pattern, a flattening pattern composed of at least one figure larger than the simple figure is reliably generated in a region at least a second predetermined distance from the wiring pattern formation region. be able to.

In the third flattening pattern generation method, the first enlarged wiring pattern and the wiring pattern obtained by expanding the wiring pattern by the first predetermined amount from the dummy original pattern are expanded by the second predetermined amount. When a first dummy pattern is generated by removing an overlapping portion with the second inverted pattern obtained by inverting the second enlarged wiring pattern formed,
A first pattern composed of a set of simple figures can be reliably generated in a region separated from the wiring pattern formation region by a first predetermined distance or more and within a second predetermined distance larger than the first predetermined distance. Further, when the second dummy pattern is generated by the second inversion pattern, a flattening pattern composed of at least one figure larger than the simple figure is surely formed in a region at least a second predetermined distance from the wiring pattern formation region. Can be generated.

According to the fourth flattening pattern generation method, the first simple figure is replaced by the first simple figure instead of the flattening pattern consisting of the first simple figure in an area at least a second predetermined distance from the wiring pattern formation area. Since a flattening pattern composed of a set of second simple figures larger than that is generated, the number of figures and the data amount of the flattening pattern can be reduced. Further, in a region that is at least a second predetermined distance from the wiring pattern formation region, a flattening pattern composed of the second set of simple figures is generated, so that the upper or lower wiring layer on which the wiring pattern is formed is formed. It is possible to suppress a situation where the parasitic capacitance in the wiring layer due to the flattening pattern increases. For this reason, it is possible to achieve both a reduction in the number of figures and the amount of data of the flattening pattern and a suppression of an increase in the parasitic capacitance in the second wiring layer.

In the fourth flattening pattern generation method, the wiring pattern is enlarged by a second predetermined amount among the second dummy original patterns formed of a set of second simple figures larger than the first simple figure. When the second dummy pattern is generated while leaving only the overlapping portion with the inverted pattern obtained by inverting the second enlarged wiring pattern formed, the region separated from the wiring pattern forming region by the second predetermined distance or more is generated. , A flattening pattern composed of a set of second simple figures is reliably generated.

According to the fifth method for generating a flattening pattern, an area separated from the first wiring pattern forming area by a second predetermined distance or more and a second wiring pattern formed area by a third predetermined distance or more can be obtained. , At least one larger than a simple figure instead of a flattening pattern consisting of a set of simple figures
Since a flattening pattern including one figure is generated, the number of figures and the data amount of the flattening pattern can be reduced while suppressing an increase in parasitic capacitance.

In the fifth flattening pattern generation method, a first enlarged wiring pattern formed by enlarging a first wiring pattern by a first predetermined amount and a second wiring pattern expanded by a second predetermined amount are obtained. When the second dummy pattern is generated by inverting the composite pattern obtained by superimposing the second enlarged wiring pattern formed on the second wiring pattern, the second dummy pattern is separated from the first wiring pattern formation region by a second predetermined distance or more and the second dummy pattern is formed. A flattening pattern composed of at least one graphic larger than a simple graphic can be reliably generated in a region at least a third predetermined distance from the wiring pattern formation region.

According to the sixth method for generating a flattening pattern, a region separated from the first wiring pattern forming region by a second predetermined distance or more and a second wiring pattern formed region from the third predetermined distance by a When a flattening pattern composed of a set of second simple figures larger than the first simple figure is generated, the number of figures and the data amount of the flattening pattern can be reduced while further suppressing an increase in parasitic capacitance.

In the sixth flattening pattern generation method, in the second dummy original pattern composed of the second simple figure larger than the first simple figure, the first wiring pattern is the first predetermined amount. Overlap of an inverted pattern obtained by inverting a composite pattern formed by superimposing an enlarged first enlarged wiring pattern and a second enlarged wiring pattern obtained by enlarging a second wiring pattern by a second predetermined amount. When the second dummy pattern is generated by leaving only the portion, the second dummy pattern is separated from the first wiring pattern formation region by a second predetermined distance or more and the second wiring pattern formation region is separated by a third predetermined distance or more. A flattening pattern consisting of a set of second simple figures larger than the first simple figure can be reliably generated.

According to the first flattening pattern generating device, the first flattening pattern generating method can be reliably realized. According to the second flattening pattern generating device, the second flattening pattern generating device can be used. According to the third flattening pattern generating apparatus, the third flattening pattern generating method can be surely realized, and the fourth flattening pattern generating method can be realized. According to the generation device, the fourth flattening pattern generation method can be reliably realized, and according to the fifth flattening pattern generation device, the fifth flattening pattern generation method can be reliably realized. According to the sixth flattening pattern generating apparatus, the sixth flattening pattern generating method can be reliably realized.

According to the first semiconductor integrated circuit device, the first flattening pattern composed of a set of simple figures is provided in a region of the wiring layer which is separated from the wiring pattern by the first predetermined distance or more and within the second predetermined distance. On the other hand, since the second flattening pattern composed of at least one figure larger than the simple figure is formed in a region of the wiring layer that is at least the second predetermined distance from the wiring pattern in the wiring layer, the simple figure The number of figures and data amount of the flattening pattern can be reduced as compared with the case of forming a flattening pattern consisting of only a set of.

According to the second semiconductor integrated circuit device, the first
In the wiring layer, a region separated from the first wiring pattern by a first predetermined distance or more and within a second predetermined distance and within a third predetermined distance from the second wiring pattern region includes:
A first flattening pattern composed of a set of simple figures is formed, and a third predetermined distance from the first wiring pattern in the second wiring layer and a third predetermined distance from the second wiring pattern. Since the second flattening pattern composed of at least one graphic larger than the simple graphic is formed instead of the flattened pattern composed of the set of simple graphics in the region separated by more than the distance, the increase in the parasitic capacitance is suppressed. In addition, the number of figures and the data amount of the flattening pattern can be reduced.

[Brief description of the drawings]

FIGS. 1A to 1D are plan views showing steps of a method for generating a flattening pattern according to a first embodiment of the present invention.

FIGS. 2A to 2C are plan views showing steps of a method for generating a flattening pattern according to the first embodiment of the present invention.

FIGS. 3A to 3D are plan views showing steps of a method for generating a flattening pattern according to a second embodiment of the present invention.

FIGS. 4A to 4D are plan views showing steps of a method for generating a flattening pattern according to a second embodiment of the present invention.

FIGS. 5A to 5D are plan views showing steps of a method for generating a flattening pattern according to a second embodiment of the present invention.

FIGS. 6A to 6D are plan views showing steps of a method for generating a flattening pattern according to a second embodiment of the present invention.

FIGS. 7A to 7D are plan views showing steps of a method for generating a flattening pattern according to a second embodiment of the present invention.

FIGS. 8A to 8D are plan views showing steps of a method for generating a flattening pattern according to a second embodiment of the present invention.

FIGS. 9A to 9D are plan views showing steps of a method for generating a flattening pattern according to a second embodiment of the present invention.

FIGS. 10A and 10B are plan views showing steps of a method for generating a flattening pattern according to a third embodiment of the present invention.

FIGS. 11A and 11B are plan views showing steps of a method for generating a flattened pattern according to a third embodiment of the present invention.

FIGS. 12A and 12B are plan views showing steps of a method for generating a flattening pattern according to a third embodiment of the present invention.

FIGS. 13A and 13B are plan views showing steps of a method for generating a flattening pattern according to a fourth embodiment of the present invention.

FIGS. 14A and 14B are plan views showing steps of a method for generating a flattening pattern according to a fourth embodiment of the present invention.

FIGS. 15A and 15B are plan views showing steps of a method for generating a flattened pattern according to a fifth embodiment of the present invention.

FIGS. 16A and 16B are plan views showing steps of a method for generating a flattening pattern according to a fifth embodiment of the present invention.

FIGS. 17A and 17B are plan views showing steps of a method for generating a flattening pattern according to a fifth embodiment of the present invention.

FIGS. 18A and 18B are plan views showing steps of a method for generating a flattening pattern according to a sixth embodiment of the present invention.

FIG. 19 is a plan view showing steps of a method for generating a flattening pattern according to a sixth embodiment of the present invention.

20A is a plan view of a semiconductor integrated circuit device according to a seventh embodiment of the present invention, and FIG. 20B is a cross-sectional view taken along line XX in FIG.

FIGS. 21A to 21C are cross-sectional views illustrating each step of a first manufacturing method of the semiconductor integrated circuit device according to the seventh embodiment.

FIGS. 22A to 22D are cross-sectional views showing each step of a second method for manufacturing a semiconductor integrated circuit device according to the seventh embodiment.

FIGS. 23A to 23D are cross-sectional views illustrating steps of a third method of manufacturing the semiconductor integrated circuit device according to the seventh embodiment.

FIGS. 24A to 24D are cross-sectional views illustrating steps of a fourth method of manufacturing the semiconductor integrated circuit device according to the seventh embodiment.

FIG. 25 is a plan view of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

FIG. 26 is a cross-sectional view taken along the line YY in FIG. 25 when the second wiring layer is located below the first wiring layer in the semiconductor integrated circuit device according to the eighth embodiment.

FIG. 27 is a cross-sectional view taken along line YY in FIG. 25 when the second wiring layer is located above the first wiring layer in the semiconductor integrated circuit device according to the eighth embodiment.

FIG. 28 is a flowchart of a method for generating a flattening pattern according to the first embodiment.

FIG. 29 is a flowchart of a first half of a method of generating a flattened pattern according to the second embodiment.

FIG. 30 is a flowchart of the latter half of the method for generating a flattening pattern according to the second embodiment.

FIG. 31 is a flowchart of a method for generating a flattening pattern according to the third embodiment.

FIG. 32 is a flowchart of a method for generating a flattening pattern according to the fourth embodiment.

FIG. 33 is a flowchart of a method for generating a flattening pattern according to the fifth embodiment.

FIG. 34 is a flowchart of a method for generating a flattening pattern according to the sixth embodiment.

FIG. 35 is a block diagram of a first flattening pattern generation device used in the flattening pattern generation method according to the first embodiment.

FIG. 36 is a block diagram of a second flattening pattern generation device used in the flattening pattern generation method according to the second embodiment.

FIG. 37 is a block diagram of a third flattening pattern generation device used in the flattening pattern generation method according to the third embodiment.

FIG. 38 is a block diagram of a fourth flattening pattern generation device used in the flattening pattern generation method according to the fourth embodiment.

FIG. 39 is a block diagram of a fifth flattening pattern generation device used in the flattening pattern generation method according to the fifth embodiment.

FIG. 40 is a block diagram of a sixth flattening pattern generation device used in the flattening pattern generation method according to the sixth embodiment.

41 (a) to (d) are plan views showing steps of a conventional flattening pattern generation method.

FIGS. 42A and 42B are plan views showing steps of a conventional method for generating a flattening pattern.

FIGS. 43A to 43C are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor integrated circuit device.

[Explanation of symbols]

 Reference Signs List 10 first dummy original pattern 11 wiring pattern 12 enlarged wiring pattern 13 dummy pattern 14 reduced dummy pattern 15 flattening pattern 21 second dummy original pattern 22 third dummy original pattern 23 fourth dummy original pattern 24 fifth Dummy original pattern 25 wiring pattern 26 enlarged wiring pattern 27 first dummy pattern 28 first reduced dummy pattern 29 second dummy pattern 30 first enlarged dummy pattern 31 first enlarged combined pattern 32 third dummy pattern 33 third dummy pattern 34 4 dummy pattern 35 second enlarged dummy pattern 36 second enlarged combined pattern 37 fifth dummy pattern 38 third reduced dummy pattern 39 sixth dummy pattern 40 third enlarged dummy pattern 41 third enlarged combined pattern 42 seventh dummy Pattern 43 fourth reduced dummy pattern 44 eighth dummy pattern 50 wiring pattern 51 first enlarged wiring pattern 52 second enlarged wiring pattern 53 inverted pattern 55 sixth dummy pattern 56 seventh dummy pattern 60 other layer wiring pattern 61 third enlarged Wiring pattern 62 Inverted pattern 70 Eighth dummy pattern 80 Semiconductor substrate 81 Wiring pattern (first wiring pattern) 82 First planarization pattern 83 Second planarization pattern 84 Interlayer insulation film 84a Upper part of interlayer insulation film 84b Interlayer insulation Projection 84A Lower interlayer insulating film 84B Upper interlayer insulating film 85 Resin 86 Second wiring pattern 100 Graphic enlargement processing means 101 Graphic logical difference operation means 102 Graphic reduction processing means 103 Graphic enlargement processing means 104 Graphic OR operation Processing means 200 Usage data Data switching means 201 graphic enlargement processing means 202 used data switching means 203 graphic logical difference operation processing means 204 graphic reduction processing means 205 graphic enlargement processing means 206 used data switching means 207 graphic enlargement processing means 208 graphic OR operation processing means 209 graphic logic Sum operation processing means 300 Use data switching means 301 Graphic enlargement processing means 302 Graphic enlargement processing means 303 Graphic inversion processing means 304 Graphic OR operation processing means 305 Use data switching means 306 Graphic reduction processing means 307 Graphic enlargement processing means 308 Use data switching Means 309 Graphic OR operation processing means 310 Use data switching means 311 Graphic OR operation processing means 312 Graphic enlargement processing means 400 Use data switching means 401 Graphic enlargement processing means 402 Graphic enlargement processing means 403 Figure inversion processing means 404 figure logical difference calculation processing means 405 logical sum calculation processing means 406 used data switching means 407 figure logical difference calculation processing means 408 figure reduction processing means 409 figure enlargement processing means 410 used data switching means 411 figure logical sum calculation processing Means 412 Graphic OR operation processing means 413 Graphic enlargement processing means 500 Use data switching means 501 Graphic enlargement processing means 502 Graphic enlargement processing means 503 Graphic OR operation processing means 504 Graphic inversion processing means 505 Graphic enlargement processing means 506 Graphic OR operation Processing means 507 Use data switching means 508 Graphic logical difference operation processing means 509 Graphic reduction processing means 510 Graphic enlargement processing means 511 Use data switching means 512 Graphic OR operation processing means 513 Graphic enlargement processing means 514 Graphic OR operation Processing means 600 Use data switching means 601 Graphic enlargement processing means 602 Graphic enlargement processing means 603 Graphic enlargement processing means 604 Graphic OR operation processing means 605 Graphic logical difference operation processing means 606 Graphic OR operation means 607 Use data switching means 608 Graphic logic Difference calculation processing means 609 Graphic reduction processing means 610 Graphic expansion processing means 611 Use data switching means 612 Graphic logical OR calculation processing means 613 Graphic logical OR calculation processing means 614 Graphic expansion processing means

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 21/3205

Claims (20)

(57) [Claims] 1. A first dummy pattern generating step of generating a first dummy pattern composed of a set of simple figures in a region of a wiring layer at least a first predetermined distance from a wiring pattern forming region where a wiring pattern is formed. And the arrangement of the wiring pattern from the first dummy pattern.
Diagram of a size that does not satisfy the rule for specifying the minimum line width
A second dummy pattern generating step of generating a second dummy pattern by removing a shape; and a step of separating from the wiring pattern forming region in the wiring layer by the first predetermined distance or more and removing the second dummy pattern from the first dummy pattern. A third dummy pattern generating step of generating a third dummy pattern composed of a set of the simple figures translated in an area at least two predetermined distances apart from each other; and disposing the wiring pattern from the third dummy pattern.
Diagram of a size that does not satisfy the rule for specifying the minimum line width
A fourth dummy pattern generating step of generating a fourth dummy pattern by removing a shape; and a flattening pattern generating a flattening pattern by combining the second dummy pattern and the fourth dummy pattern. And generating a flattening pattern. 2. The first dummy pattern generation step includes: a step of generating an enlarged wiring pattern by enlarging the wiring pattern by a first predetermined amount; and a step of repeatedly arranging the simple figure on the wiring layer. Generating a first dummy original pattern; and generating the first dummy pattern by a graphic logical difference operation process of deleting an overlapping portion of the first dummy original pattern and the enlarged wiring pattern , wherein the third dummy pattern generating step comprises generating a second dummy original pattern by translating the simple shapes that constituting the first dummy original pattern, where the second dummy pattern of the second overlapping portions of only the step of generating an enlarged dummy pattern enlarged and, with the enlarged wiring pattern and the larger the dummy pattern from said second dummy original pattern quantitative Generating the third dummy pattern by a graphic logical difference operation processing for eliminating the pattern logic , wherein the flattening pattern generating step includes: a graphic logic for superimposing the second dummy pattern and the fourth dummy pattern. claims, characterized in that it comprises a step of generating the flat pattern by the sum operation processing
2. The method for generating a flattening pattern according to item 1 . 3. A set of simple figures located in a region within a second predetermined distance greater than or equal to a first predetermined distance and greater than the first predetermined distance from a wiring pattern forming region in the wiring layer where a wiring pattern is formed. A first dummy pattern generating step of generating a first dummy pattern, wherein at least one figure larger than the simple figure is provided in a region of the wiring layer at least a second predetermined distance from the wiring pattern formation region. A second dummy pattern generating step of generating a second dummy pattern, and a flattening pattern generating step of combining the first dummy pattern and the second dummy pattern to generate a flattening pattern. A method for generating a flattening pattern, comprising: 4. The first dummy pattern generating step includes: generating a first enlarged wiring pattern by enlarging the wiring pattern by a first predetermined amount; and generating the first enlarged wiring pattern by the first predetermined amount. Second greater than
Generating a second enlarged wiring pattern by enlarging by a predetermined amount of: a step of inverting the second enlarged wiring pattern to generate an inverted pattern; Generating the first dummy pattern by a graphic logical difference operation process of deleting an overlapping portion of the first enlarged wiring pattern and the inverted pattern from the dummy original pattern. The second dummy pattern generation step includes a step of generating the second dummy pattern composed of the inverted pattern, and the flattening pattern generation step includes overlapping the first dummy pattern with the second dummy pattern. claims, characterized in that it comprises a step of generating the flat pattern by figure logical sum operation to match
3. The method for generating a flattening pattern according to item 3 . 5. The first dummy pattern generation step includes: a step of generating an enlarged wiring pattern by enlarging the wiring pattern by a first predetermined amount; and a step of generating an inverted pattern by inverting the wiring pattern. A second pattern larger than the first predetermined amount;
Generating a reduced inversion pattern by reducing by a predetermined amount, generating a dummy original pattern by repeatedly arranging the simple figures, and overlapping the enlarged wiring pattern and the reduced inversion pattern from the dummy original pattern. Generating the first dummy pattern by a graphic logical difference operation process of deleting a portion, wherein the second dummy pattern generating step includes the step of generating the second dummy pattern composed of the reduced inverted pattern wherein the said flat pattern generation step, claims characterized in that it comprises a step of generating the flat pattern by the first graphic logical sum operation of superimposing the dummy pattern and said second dummy pattern Term
3. The method for generating a flattening pattern according to item 3 . 6. The first dummy pattern generating step includes a step of generating a first enlarged wiring pattern by enlarging the wiring pattern by a first predetermined amount, and a step of generating the first enlarged wiring pattern by the first predetermined amount. Second greater than
Generating a second enlarged wiring pattern by enlarging the first inverted pattern by a predetermined amount; generating a first inverted pattern by inverting the second enlarged wiring pattern; Generating a reduced inversion pattern by reducing the reduced inversion pattern by a predetermined amount, and generating a second inversion pattern by expanding the reduced inversion pattern by the third predetermined amount. Generating a dummy original pattern; and generating the first dummy pattern by a graphic logical difference operation process of removing an overlapping portion between the first enlarged wiring pattern and the second inverted pattern from the dummy original pattern. The step of generating the second dummy pattern includes the step of generating the second dummy pattern composed of the second inverted pattern. Over emissions generation step, claims, characterized in that it comprises a step of generating the flat pattern by the first graphic logical sum operation of superimposing the dummy pattern and said second dummy pattern
3. The method for generating a flattening pattern according to item 3 . 7. A first simple figure in an area within a second predetermined distance that is greater than or equal to a first predetermined distance and larger than the first predetermined distance from a wiring pattern forming area in the wiring layer where a wiring pattern is formed. A first dummy pattern generating step of generating a first dummy pattern consisting of a set of: a first dummy pattern in a region of the wiring layer that is at least a second predetermined distance from the wiring pattern formation region in the wiring layer; A second dummy pattern generation step of generating a second dummy pattern composed of a set of large second simple figures; and generating a flattened pattern by combining the first dummy pattern and the second dummy pattern. And generating a flattening pattern. 8. The first dummy pattern generating step includes a step of generating a first enlarged wiring pattern by enlarging the wiring pattern by a first predetermined amount, and a step of generating the first enlarged wiring pattern by the first predetermined amount. Second greater than
Generating a second enlarged wiring pattern by enlarging by a predetermined amount, inverting the second enlarged wiring pattern to generate an inverted pattern, and repeatedly arranging the first simple figure. Generating a first dummy pattern; and performing a graphic logical difference calculation process of removing an overlapping portion of the first enlarged wiring pattern and the inverted pattern from the first dummy original pattern. Generating a second dummy pattern, wherein the second dummy pattern generating step comprises: repeatedly arranging the second simple figure to generate a second dummy original pattern; Generating the second dummy pattern by a graphic AND operation process that leaves only an overlapping portion with the inverted pattern, and the flattening pattern generating step The method according to claim 1 , further comprising a step of generating the flattened pattern by a graphic OR operation for overlapping the first dummy pattern and the second dummy pattern.
8. The method for generating a flattening pattern according to item 7 . 9. A second predetermined distance that is at least a first predetermined distance from the first wiring pattern formation region in the first wiring layer where the first wiring pattern is formed and that is larger than the first predetermined distance. The first wiring layer is located within a third predetermined distance from a second wiring pattern forming region where a second wiring pattern is formed in a second wiring layer that is an upper layer or a lower layer of the first wiring layer. A first dummy pattern generation step of generating a first dummy pattern composed of a set of simple figures in a region of the wiring layer, and a step of generating the second predetermined pattern from the first wiring pattern formation region in the first wiring layer. A second dummy pattern formed of at least one graphic larger than the simple graphic in the first wiring layer region separated by at least a distance and separated from the second wiring pattern formation region by the third predetermined distance or more; And a flattening pattern generating step of synthesizing the first dummy pattern and the second dummy pattern to generate a flattening pattern. A method for generating a flattening pattern. 10. The first dummy pattern generating step includes: a step of enlarging the first wiring pattern by a first predetermined amount to generate a first enlarged wiring pattern; Generating a second enlarged wiring pattern by enlarging the second enlarged wiring pattern by a second predetermined amount; and generating a composite pattern by performing a graphic OR operation for superimposing the first enlarged wiring pattern and the second enlarged wiring pattern. Inverting the composite pattern to generate an inverted pattern; repeatedly arranging the simple figures to generate a dummy original pattern; and performing the first enlarged wiring pattern and the inversion from the dummy original pattern. Generating the first dummy pattern by graphic logical difference operation processing for removing an overlapping portion with the pattern, The forming step includes a step of generating the second dummy pattern composed of the inversion pattern, and the flattening pattern generating step includes: a graphic OR operation in which the first dummy pattern and the second dummy pattern are overlapped. claims, characterized in that it comprises a step of generating the flat pattern by the arithmetic processor
10. The method for generating a flattening pattern according to item 9 . 11. A method according to claim 1, wherein the first wiring pattern is formed on the first wiring layer in the first wiring pattern forming region.
From the second wiring pattern forming area where the second wiring pattern is formed in the second wiring layer which is at least the predetermined distance and within the second predetermined distance and which is the upper layer or the lower layer of the first wiring layer. A first dummy pattern generating step of generating a first dummy pattern composed of a set of first simple figures in a region of the first wiring layer within a third predetermined distance; A second area larger than the first simple figure in an area separated from the first wiring pattern formation area by the second predetermined distance or more and separated from the second wiring pattern formation area by the third predetermined distance or more; A second dummy pattern generating step of generating a second dummy pattern composed of a set of simple figures; and generating a flattened pattern by combining the first dummy pattern and the second dummy pattern. Method of generating a planarizing pattern characterized by comprising a tanker pattern generation step. 12. The first dummy pattern generating step includes: a step of enlarging the first wiring pattern by a first predetermined amount to generate a first enlarged wiring pattern; Generating a second enlarged wiring pattern by enlarging the second enlarged wiring pattern by a second predetermined amount; and generating a composite pattern by performing a graphic OR operation for superimposing the first enlarged wiring pattern and the second enlarged wiring pattern. A step of inverting the composite pattern to generate an inverted pattern; a step of repeatedly arranging the first simple figure to generate a first dummy original pattern; Generating the first dummy pattern by a graphic logical difference operation process of deleting an overlapping portion between the first enlarged wiring pattern and the inverted pattern. Generating a second dummy original pattern by repeatedly arranging the second simple figure; and leaving only an overlapped portion of the second dummy original pattern with the inverted pattern. Generating the second dummy pattern by graphic logical product operation processing, wherein the flattening pattern generating step comprises: a graphic logical sum operation processing for superimposing the first dummy pattern and the second dummy pattern. Generating the flattening pattern according to the following :
12. The method for generating a flattening pattern according to item 11 . 13. A first graphic enlargement processing means for enlarging a wiring pattern in a wiring layer by a first predetermined amount to generate an enlarged wiring pattern, and a dummy element for generating a dummy original pattern by repeatedly arranging simple figures. Pattern generation processing means; graphic logical difference calculation processing means for generating a dummy pattern by removing an overlapping portion with the enlarged wiring pattern from the dummy original pattern; and reducing and reducing the dummy pattern by a second predetermined amount. Flatness comprising: a graphic reduction processing means for generating a dummy pattern; and a second graphic enlargement processing means for generating a flattened pattern by expanding the reduced dummy pattern by the second predetermined amount. Device for generating a pattern. 14. A first graphic enlargement processing means for generating an enlarged wiring pattern by enlarging a wiring pattern in a wiring layer by a first predetermined amount, and a first dummy original pattern formed by repeatedly arranging the simple figures. A first dummy original pattern generating means for generating, a graphic logical difference operation processing means for generating a first dummy pattern by deleting an overlapping portion with the enlarged wiring pattern from the first dummy original pattern; First graphic reduction processing means for reducing a first dummy pattern by a second predetermined amount to generate a first reduced dummy pattern; and expanding the first reduced dummy pattern by the second predetermined amount. Second figure enlargement processing means for generating a second dummy pattern; and a second figure for generating a second dummy original pattern by translating a simple figure constituting the first dummy original pattern in parallel. Dummy original pattern generating means; third graphic enlarging processing means for enlarging the second dummy pattern by a third predetermined amount to generate an enlarged dummy pattern; and expanding the enlarged wiring pattern from the second dummy original pattern And a graphic logical difference calculation processing means for generating a third dummy pattern by deleting an overlapping portion with the enlarged dummy pattern; and a second reduced dummy by reducing the third dummy pattern by a fourth predetermined amount. A second graphic reduction processing means for generating a pattern; a fourth graphic expansion processing means for generating the fourth dummy pattern by expanding the second reduced dummy pattern by the fourth predetermined amount; A flattening unit comprising: a graphic OR operation processing unit that generates a flattened pattern by superimposing a second dummy pattern and the fourth dummy pattern. Device for generating a pattern. 15. A first graphic enlargement processing means for enlarging a wiring pattern in a wiring layer by a first predetermined amount to generate a first enlarged wiring pattern; and setting the wiring pattern to be larger than the first predetermined amount. Big second
Second pattern enlargement processing means for enlarging a predetermined amount of the second enlarged wiring pattern to generate a second enlarged wiring pattern; graphic inversion processing means for inverting the second enlarged wiring pattern to generate an inverted pattern; Generating a dummy original pattern by repeatedly arranging a simple figure, and generating a dummy pattern by removing an overlapping portion of the first enlarged wiring pattern and the inverted pattern from the dummy original pattern. An apparatus for generating a flattened pattern, comprising: a graphic logical difference operation process; and a graphic OR operation process for generating a flattened pattern by superimposing the dummy pattern and the inverted pattern. 16. A first graphic enlarging processing means for enlarging a wiring pattern in a wiring layer by a first predetermined amount to generate a first enlarged wiring pattern, wherein said wiring pattern is made larger than said first predetermined amount. Big second
A second graphic enlargement processing means for enlarging by a predetermined amount to generate a second enlarged wiring pattern; a graphic inversion processing means for inverting the second enlarged wiring pattern to generate an inverted pattern; First dummy original pattern generation means for repeatedly arranging simple figures to generate a first dummy original pattern; and determining an overlapping portion of the first enlarged wiring pattern and the inverted pattern from the first dummy original pattern. A graphic logical difference operation processing means for generating a first dummy pattern by deleting, and a second dummy pattern for generating a second dummy original pattern by repeatedly arranging a second simple graphic larger than the first simple graphic Dummy original pattern generation means, and a graphic AND operation processing for generating a second dummy pattern by leaving only an overlapping portion of the second dummy original pattern with the inverted pattern Means and apparatus for producing a flat pattern, characterized in that it comprises a graphic logical sum operation means for generating a flattened pattern by superimposing said first dummy pattern and said second dummy pattern. 17. A first graphic enlarging means for enlarging a first wiring pattern in a first wiring layer by a first predetermined amount to generate a first enlarged wiring pattern; Second enlargement processing means for enlarging a second wiring pattern in a second wiring layer, which is an upper layer or a lower layer, by a second predetermined amount to generate a second enlarged wiring pattern; A graphic OR operation processing means for generating a composite pattern by superposing a wiring pattern and the second enlarged wiring pattern; a graphic inversion processing means for generating an inverted pattern by inverting the composite pattern; A dummy original pattern generating means for generating a dummy original pattern by arranging the first enlarged wiring pattern and the inverted pattern from the dummy original pattern; A graphic logical difference operation processing means for generating a me pattern; and a graphic logical operation processing means for generating a flattened pattern by superimposing the first dummy pattern and the inverted pattern. An apparatus for generating a flattening pattern. 18. A first graphic enlarging means for enlarging a first wiring pattern in a first wiring layer by a first predetermined amount to generate a first enlarged wiring pattern; and wherein the first wiring layer Second enlargement processing means for enlarging a second wiring pattern in a second wiring layer, which is an upper layer or a lower layer, by a second predetermined amount to generate a second enlarged wiring pattern; A graphic OR operation processing means for generating a composite pattern by superimposing a wiring pattern and the second enlarged wiring pattern; a graphic inversion processing means for generating an inverted pattern by inverting the composite pattern; A first dummy original pattern generating means for repeatedly arranging figures to generate a first dummy original pattern, and an overlap of the first enlarged wiring pattern and the inverted pattern from the first dummy original pattern. A logical difference operation processing means for generating a first dummy pattern by removing a portion of the original pattern, and a second dummy original pattern is generated by repeatedly arranging a second simple graphic larger than the first simple graphic. A second dummy original pattern generating unit; a graphic AND operation processing unit for generating a second dummy pattern by leaving only an overlapping portion of the second dummy original pattern with the inverted pattern; A flattened pattern generating apparatus, comprising: a graphic logical sum operation processing means for generating a flattened pattern by superimposing the dummy pattern and the second dummy pattern. 19. A wiring pattern formed on a wiring layer on a semiconductor substrate, and separated from the wiring pattern on the wiring layer by a first predetermined distance or more and within a second predetermined distance larger than the first predetermined distance. And a first flattening pattern formed of a set of simple figures, and a first flattening pattern formed in an area of the wiring layer at a distance of the second predetermined distance or more from the wiring pattern, and A second flattening pattern formed of at least one figure having a larger size, and an interlayer insulating film formed on the wiring pattern, the first flattening pattern, and the second flattening pattern. Semiconductor integrated circuit device. 20. A first wiring pattern formed on a first wiring layer on a semiconductor substrate, and formed on a second wiring layer located above or below the first wiring layer on the semiconductor substrate. The second wiring pattern, and the second wiring pattern in the first wiring layer, which is separated from the first wiring pattern by at least a first predetermined distance and within a second predetermined distance larger than the first predetermined distance, A first flattening pattern formed in a region within a third predetermined distance from the second wiring pattern and comprising a set of simple figures; and a first wiring pattern in the first wiring layer. A second flattening pattern formed in an area separated by at least the second predetermined distance and separated by at least the third predetermined distance from the second wiring pattern and formed of at least one figure larger than the simple figure; The first wiring pattern, the first planarization pattern and the second planarization pattern formed on the first wiring layer, and the second wiring pattern formed on the second wiring layer. A semiconductor integrated circuit device comprising: an interlayer insulating film formed between the second wiring pattern and the second wiring pattern.