JP3127948B2 - Semiconductor package and mounting method thereof - Google Patents

Abstract

PURPOSE: To obtain a semiconductor package excellent in heat dissipation performance and handling performance in which the size can be reduced as small as a semiconductor chip, and a mounting method thereof. CONSTITUTION: The semiconductor package comprises a semiconductor chip 1 having an electrode on the surface thereof, a package board 3A having a first electrode part 31 corresponding to the electrode of the semiconductor chip 1 on the rear and a second electrode part conducting through a connecting part 33 with the first electrode part 31 on the surface, and a bump 2 for bonding the electrode of the semiconductor chip 1 and the first electrode part 31 of the package board 3A. The semiconductor chip 1 is die bonded, on the rear thereof, to a circuit board 6 through a die bond material 5 and the second electrode part 32 of the package board 3A is connected with the circuit board 6, at a predetermined connecting point thereon, through a bonding wire.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package including a semiconductor chip and a method for mounting the semiconductor package on a circuit board.

[0002]

2. Description of the Related Art As is well known, a semiconductor package is designed to mechanically reinforce a semiconductor chip, protect the semiconductor chip from an external environment such as moisture, and to facilitate mounting on a circuit board or the like. After being electrically connected to the external leads, they are usually entirely resin-sealed. In such a semiconductor package, a search for miniaturization is rapidly progressing.

For example, as a package shape, a thin S
OP (Small Outline Package) and thin QFP (Quad F
lat Package). Further, as a packaging structure, there is a so-called LOC (Lead On Chip) or the like in which the tip of a lead is fixed on a semiconductor chip, and an electrode and a lead portion are connected on the chip by a bonding wire. For these reasons, miniaturization in the mold package is considered to be near the limit. However, even in the thin SOP having the LOC structure, the volume of the semiconductor chip occupying the mold portion is only about 24% at maximum (the area occupation ratio is 80% and the thickness occupation ratio is 30%).

Further, in the conventional mold package, the heat dissipation from the semiconductor chip is poor. For example, a QFP (42 alloy lead, 100
(Pin, general mold structure, when mounted on a substrate, no wind)), thermal resistance θja = 90 ° C./W. For this reason, at present, many studies have been made on the material of the lead, the material of the sealing resin, the structure of providing the heat radiating plate, and the like.

[0005]

Recently, as a mounting technique having advantages such as high-speed operability and miniaturization, an MCM (Multicnd) in which a plurality of bare chips are mounted on a high-density wiring board has been developed.
hip Module). In this MCM, the use of bare chips is advantageous in terms of miniaturization and heat dissipation as compared with the above-described mold package.

However, in this MCM, all of the bare chips mounted are non-defective products (so-called Known Go) including reliability.
od Die) is essential. However,
Since the evaluation of characteristics and reliability of bare chips involves handling of the semiconductor chip itself, there is a problem that there are many difficult points such as breakage of the semiconductor chip and breakage of surface circuits during handling.

[0007] As described above, the conventional semiconductor package is near the limit of miniaturization, and has a problem in the magnitude of thermal resistance. Further, a bare chip which is relatively advantageous in these respects is used. For example, in the case of an MCM or the like, the technology development of a known good die is required.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor package which can be reduced in size to approximately the same size as a semiconductor chip, has good heat dissipation, and has excellent handling properties, and a method of mounting the same. .

[0009]

In order to achieve the above object, a semiconductor package according to the present invention has a semiconductor chip having an electrode on a front surface and a first electrode portion corresponding to the electrode of the semiconductor chip on a rear surface. A package substrate having on its surface a second electrode portion conducting to the first electrode portion, and a bump joining the electrode of the semiconductor chip and the first electrode portion of the package substrate. The outer peripheral portion of the substrate protrudes outward from the side surface of the semiconductor chip, and the rear surface of the outer peripheral portion is formed thicker than the portion facing the semiconductor chip.

Further, the semiconductor package according to the present invention comprises:
A semiconductor chip having an electrode on the front surface, a package substrate having a first electrode portion corresponding to the electrode of the semiconductor chip on the back surface, and a second electrode portion on the front surface conducting to the first electrode portion; A semiconductor package comprising: a bump that joins an electrode of the semiconductor chip and a first electrode portion of the package substrate; and a resin that seals at least an outer periphery between the semiconductor chip and the package substrate. An outer peripheral portion of the package substrate is projected outward from a side surface of the semiconductor chip, and a rear surface of the outer peripheral portion is formed to be thicker than a portion facing the semiconductor chip.

[0011]

[0012]

Further, according to the present invention, there is provided a method of mounting a semiconductor package, comprising: a semiconductor chip having an electrode on a front surface; a first electrode portion corresponding to the electrode of the semiconductor chip on a back surface; A method for mounting, on a circuit board, a semiconductor package including a package substrate having a conductive second electrode portion on a surface thereof, and a bump joining an electrode of the semiconductor chip and a first electrode portion of the package substrate. A back surface of the semiconductor chip is fixed to a circuit board, and a second electrode portion on a front surface of the package substrate is connected to a predetermined portion of the circuit board by a bonding wire.

Further, according to the present invention, there is provided a method of mounting a semiconductor package, comprising: a semiconductor chip having an electrode on a front surface; a first electrode portion corresponding to the electrode of the semiconductor chip on a back surface; A package substrate having a conductive second electrode portion on its surface; a bump joining the electrode of the semiconductor chip to the first electrode portion of the package substrate; and a bump at least between the semiconductor chip and the package substrate. A method of mounting a semiconductor package made of a resin for sealing the periphery on a circuit board, wherein a back surface of the semiconductor chip is fixed to a circuit board, and a second electrode portion on a surface of the package board and a circuit board of the circuit board. A predetermined portion is connected by a bonding wire.

[0015]

According to the above arrangement, the package substrate is fixed on the semiconductor chip by bonding the first electrode portion of the package substrate to the electrodes of the semiconductor chip via the bumps. The second electrode portion electrically connected to the electrode portion serves as an external connection portion at the time of wire bonding or bump bonding to the circuit board. The package substrate on the semiconductor chip mechanically reinforces the semiconductor chip and protects the chip surface. As a result, it is possible to package a package having a size approximately the same as that of a semiconductor chip in a projected area.

In the mounting by the mold package, since the circuit board and the bottom of the package of the chip float, the heat from the chip is radiated to the circuit board via the lead of the package. Since one surface of the chip is entirely in contact with the circuit board, the heat radiation can be greatly improved. If at least the outer periphery between the semiconductor chip and the package substrate is sealed with a resin, the strength of the entire package is further increased, and protection from an external environment such as moisture is also effective.

Further, by holding the package substrate by suction, for example, the semiconductor package can be easily handled without touching the semiconductor chip itself. As a result, characteristic evaluation and reliability evaluation can be performed without causing breakage of the semiconductor chip and destruction of the surface circuit, and thus, for example, it becomes easy to sort bare chips for MCM or the like.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor package according to the present invention and a method of mounting the same will be described below with reference to the drawings.

FIG. 1 shows a first embodiment. 1 is a semiconductor chip, 2 is a bump, 3A is a package substrate, 4 is a bonding wire, 5 is a die bond material, and 6 is a circuit board. This semiconductor package is characterized in that it has a package substrate 3A on the semiconductor chip 1, and this package is hereinafter referred to as a CCP (Caped Chip Package).

A plurality of electrodes (not shown) are arranged on the semiconductor chip 1 along the vicinity of the outer periphery of the surface. Note that the electrode may be in the inner peripheral area of the surface.

The package substrate 3A is formed in a flat plate shape from an insulating material such as an epoxy resin, for example, and has a rectangular planar shape substantially the same size as the semiconductor chip 1. A first electrode portion 31 is provided on the back surface of the package substrate 3A so as to correspond to the electrode of the semiconductor chip 1, and a second electrode portion 32 is provided on the front surface. First
The electrode portion 31 and the second electrode portion 32 are electrically connected via a connection portion 33 provided around the outer periphery from the front and back surfaces of the package substrate 3A. These electrode portions 31 and 32 and connection portion 3
3 can be integrally formed as a conductive pattern by, for example, etching or plating. In particular, in the case of plating, a plastic material that can be plated is preferably used as the package substrate 3A.

In order to assemble the CCP, first, the bumps 2 are bonded to the electrodes of the semiconductor chip 1, and then the electrodes of the semiconductor chip 1 are connected to the package substrate 3 via the bumps 2.
The first electrode unit 31 of FIG. As a result, the semiconductor chip 1 and the package substrate 3A are mechanically fixed, and each electrode is electrically connected to the first electrode unit 31. Further, the bumps 2 may be bonded to the first electrode portion 31 of the package substrate 3A first. In addition, bump 2
May be wafer bumps formed on the electrodes of the semiconductor chip 1 at the wafer stage, or ball bumps for post-bonding, and may be made of Au, Cu, P
b-Sn or the like is used.

To mount the CCP on the circuit board 6, first, the back surface of the semiconductor chip 1 is die-bonded to the circuit board 6 by a die bonding material 5 such as Ag paste or eutectic bonding. Next, the second electrode portion 32 on the surface of the package substrate 3A and a predetermined connection point on the circuit board 6 are wired by a bonding wire 4 such as Au or Al.

According to this CCP, the second electrode portion 32 of the package substrate 3A fixed on the semiconductor chip 1
It serves as an external connection portion for wire bonding to the circuit board 6, and the package substrate 3A on the semiconductor chip 1 mechanically reinforces the semiconductor chip 1 and protects the chip surface. Thus, ultra-small packaging having a size substantially equal to that of the semiconductor chip 1 on a projected area can be achieved. The thickness of the package substrate 3A is substantially equal to or at most twice the thickness of the semiconductor chip 1 (generally 0.4 mm).
Since the height of the CCP is several tens of μm, the overall thickness of the CCP can be substantially the same as or less than that of the conventional mold package.

In this embodiment, the back surface of the semiconductor chip 1 is in contact with the entire circuit board 6 via the die bonding material 5, so that the heat generated by the semiconductor chip 1 is directly transferred to the circuit board 6 via the die bonding material 5. Since heat is dissipated, heat radiation can be greatly improved. In particular, in mounting by die bonding and wiring as in this embodiment,
Extremely excellent heat dissipation (for example, thermal resistance θja = 10 ° C./W) almost equivalent to that of a bare chip can also be expected. After the semiconductor chip 1 is mounted on the circuit board 6 as described above, it is preferable that the entirety be sealed with, for example, a potting resin 9 in order to mechanically protect the bonding wires 4.

Further, according to this CCP, as shown by the phantom line in FIG.
The CCP can be easily handled like a general mold package without touching itself.
As a result, characteristic evaluation and reliability evaluation can be performed without causing damage to the semiconductor chip 1 or damage to the surface circuit. Becomes easier.

Next, FIG. 2 shows a second embodiment. The method of assembling the CCP is the same as that of the first embodiment, except that the side surfaces of the semiconductor chip 1 including the gap between the semiconductor chip 1 and the package substrate 3B and the outer periphery thereof are sealed with the resin 7. . The package substrate 3B is formed somewhat larger (for example, 1 to 2 mm) so that the outer peripheral portion 34 protrudes outward from the side surface of the semiconductor chip 1.

Here, the sealing with the potting resin 7 is shown, but in order to enhance the heat dissipation, the surface of the package substrate 3B is cured downward so that the resin 7 does not turn to the back surface of the semiconductor chip 1. I do. At this time, the outer peripheral portion 34 of the package substrate 3B can prevent the resin 7 from flowing down.

As described above, at least the outer periphery between the semiconductor chip 1 and the package substrate 3B, preferably the gap between the semiconductor chip 1 and the package substrate 3B is sealed with a resin, so that the mechanical properties of the entire CCP can be further improved. The strength can be improved, and the surface circuits and the joints of the semiconductor chip 1 can be effectively protected from an external environment such as moisture. When the outer peripheral portion 34 of the package substrate 3B is made larger than the semiconductor chip 1 as in this example, the package substrate 3
The outer peripheral edge of B can also be gripped.

Next, FIG. 3 shows a third embodiment. The method of assembling the CCP is the same as that of the first embodiment, except that the package substrate 3C has a concave back surface. That is, the thickness (h ₁ ) of the outer peripheral portion 34 protruding outward from the side surface of the semiconductor chip 1 is formed to be larger on the back surface side than the thickness (h ₂ ) of the portion 35 facing the semiconductor chip 1. I have.

As a result, when the thickness h ₂ of the facing portion 35 is made smaller than that of the package substrate 3A as compared with the flat package substrate 3A shown in FIG. ₃ can be lowered. Further, when the thickness h ₂ of the facing portion 35 equivalent to the package substrate 3A can obtain higher strength by CCP same height.

Next, FIG. 4 shows a fourth embodiment. The method of assembling the CCP is the same as that of the first embodiment described above, except that through holes 36 are formed in the package substrate 3D at positions corresponding to the electrodes of the semiconductor chip 1. In this example, the first electrode portion 31 and the second electrode portion 32 are formed by the lower end and the upper end of the through hole 36, and the bonding wire 4 and the bump 2 are directly provided on the upper and lower ends of the through hole 36, respectively. Are joined.

As described above, when conduction between the first electrode portion 31 and the second electrode portion 32 is performed by the through hole 36,
The continuity between these electrode portions 31 and 32 is established by connecting portions 3 on the outer peripheral edge.
3 makes the package substrate 3D easier to manufacture than the package substrate 3A.

FIG. 5 shows a modification of the package substrate having through holes. In the package substrate 3E, as shown in FIG. 3B, first and second electrode portions 31 and 32 are formed from the lower end and the upper end of the through hole 36 by a conductive pattern such as plating. In this way, as shown in FIG. 3A, the positions of the adjacent through holes 36 are deviated from each other, so that even if the first electrode portions 31 on the rear surface are narrow in pitch, the second electrode portions 3 on the front surface are formed.
2 can be easily connected to the package substrate 3 with respect to the semiconductor chip 1 having a large number of narrow electrodes.
E can be provided effectively.

In the case of the package substrates 3B and 3C having a large or thick outer peripheral portion 34 as shown in FIGS. 2 and 3, it is better to use the through holes 36 as shown in FIG. 4 or FIG. This is preferable because the connection portion 33 on the outer peripheral edge becomes unnecessary. Further, the package substrates 3D and 3E having no connection portion 33 on the outer peripheral edge are also preferable when gripping the outer peripheral edge.

FIG. 6 shows still another modification. In the package substrate 3F, a through hole 37 is formed at the outer peripheral edge. That is, as shown in FIG. 3A, a plurality of package substrates 3F are obtained from a large plate-like member, and through holes 37 are provided in advance along cutting lines of each package substrate 3F. Accordingly, by dividing each package substrate 3F, as shown in FIG. 3B, a recessed through hole 37 is formed in the outer peripheral edge of each package substrate 3F, and the first electrode portion is formed. 31 and the second electrode unit 32 are connected.

FIG. 7 shows a fifth embodiment showing another mounting method of the CCP. The method of assembling the CCP is the same as that of the first embodiment described above, but is characterized in that the mounting method on the circuit board 6 uses the bumps 8 without using the bonding wires 4. That is, the bump 8 is bonded to the second electrode portion 32 on the surface of the package substrate 3A, the surface of the package substrate 3A faces the circuit board 6, and the second electrode portion 32 is connected to the circuit board 6 via the bump 8. Join at a predetermined connection point.

According to this mounting method, the CC after the mounting is completed
There is an advantage that the area occupied by P can be accommodated in almost the same area as the semiconductor chip 1. Particularly in the MCM or the like, the overall size can be further reduced by high-density mounting of the CCP.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various effective modifications and applications are possible based on the technical idea of the present invention. For example, the shape of the package substrate, the conductive structure between the first and second electrode portions of the package substrate, the sealing portion with resin, the method of mounting the semiconductor package, and the like
Various combinations are possible between the configurations of the embodiments or other effective configurations.

[0040]

As described above, according to the present invention,
A semiconductor package is formed by fixing a package substrate on a semiconductor chip, and at the time of mounting, the second electrode portion of the package substrate is connected to a circuit board via a bonding wire or a bump, so that the semiconductor chip is substantially formed. It is possible to obtain a very small semiconductor package of the same size and very good heat dissipation, and the handling for bare chip selection becomes much easier. Becomes possible. Furthermore, since the electrode of the semiconductor chip and the first electrode portion of the package substrate are bump-bonded, mechanical fixing and electrical connection between the semiconductor chip and the package substrate are extremely simple in one assembly process. It can be performed reliably.

[Brief description of the drawings]

FIG. 1 is a sectional view of a mounted state of a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor package according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor package according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a mounted state of a semiconductor package according to a fourth embodiment of the present invention.

5A and 5B show a semiconductor package according to a modification of the fourth embodiment, wherein FIG. 5A is a plan view and FIG. 5B is a sectional view.

FIGS. 6A and 6B show a semiconductor package in still another modification of the fourth embodiment, wherein FIG. 6A is a plan view and FIG. 6B is a sectional view.

FIG. 7 is a cross-sectional view illustrating a mounted state of a semiconductor package according to a fifth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Bump 3A-3F Package board 31 1st electrode part 32 2nd electrode part 33 Connection part 34 Outer part 35 Opposing part 36, 37 Through hole 4 Bonding wire 5 Die bond material 6 Circuit board 7 Sealing resin 8 Bump 9 sealing resin

Claims (4)

(57) [Claims] 1. A semiconductor chip having electrodes on a front surface, and a first electrode portion corresponding to the electrodes of the semiconductor chip on a back surface and a second electrode portion conducting to the first electrode portion on a front surface. A semiconductor substrate comprising: a package substrate having the semiconductor substrate; and a bump for joining an electrode of the semiconductor chip to a first electrode portion of the package substrate, wherein an outer peripheral portion of the package substrate is located outside a side surface of the semiconductor chip. A semiconductor package, wherein a rear surface of an outer peripheral portion thereof is formed thicker than a portion facing the semiconductor chip. 2. A semiconductor chip having an electrode on the front surface, and a second electrode portion having a first electrode portion corresponding to the electrode of the semiconductor chip on the back surface and conducting to the first electrode portion on the front surface. Comprising a package substrate, a bump for joining an electrode of the semiconductor chip to a first electrode portion of the package substrate, and a resin for sealing at least an outer periphery between the semiconductor chip and the package substrate. A semiconductor, wherein an outer peripheral portion of the package substrate protrudes outward from a side surface of the semiconductor chip, and a rear surface of the outer peripheral portion is formed to be thicker than a portion facing the semiconductor chip. package. 3. A semiconductor chip having an electrode on a front surface, and a second electrode portion having a first electrode portion corresponding to the electrode of the semiconductor chip on a back surface and conducting to the first electrode portion on a front surface. A method for mounting a semiconductor package, comprising a package substrate having a semiconductor chip and a bump for bonding an electrode of the semiconductor chip and a first electrode portion of the package substrate, to a circuit board, wherein a back surface of the semiconductor chip is mounted on the circuit board. A method of mounting a semiconductor package, wherein the semiconductor device is fixed and connected between a second electrode portion on a surface of the package substrate and a predetermined portion of the circuit substrate by a bonding wire. 4. A semiconductor chip having an electrode on a front surface, and a second electrode portion having a first electrode portion corresponding to the electrode of the semiconductor chip on a back surface and conducting to the first electrode portion on a front surface. Comprising a package substrate, a bump for joining an electrode of the semiconductor chip to a first electrode portion of the package substrate, and a resin for sealing at least an outer periphery between the semiconductor chip and the package substrate. A method of mounting a package on a circuit board, wherein a back surface of the semiconductor chip is fixed to a circuit board, and a second electrode portion on a surface of the package board and a predetermined portion of the circuit board are connected by a bonding wire. A method for mounting a semiconductor package.