JP3121944B2 - Electronic circuit fabrication method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix such as a semiconductor integrated circuit and a liquid crystal display, or other electronic circuits, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Since the 1980s, gate materials of MOS type semiconductor integrated circuits have been mainly made of silicon. This is in addition to the physical characteristic that the energy difference between the gate electrode and the semiconductor channel is small,
This is because the source / drain can be formed in a self-aligned manner (self-alignment) because of heat resistance. Conversely, aluminum gates, which have been the mainstream until then, are not suitable for self-alignment processes because of their lack of heat resistance, and have been gradually used, despite their low wiring resistance.

However, recently, by using a laser annealing technique or the like, it has been clarified that a self-alignment process can be adopted even with an aluminum gate, and furthermore, a gate electrode or a wiring connected to the gate electrode (these are mutually connected). Since these are not clearly distinguishable, hereinafter, they are collectively referred to as gate electrode wirings), and by forming an aluminum oxide film having excellent corrosion resistance and pressure resistance on the surface by an anodizing method, electrical connection between wiring layers can be achieved. It has been shown that the separation can be reliably performed and that an offset region can be formed in the gate and the source / drain by using aluminum oxide (Japanese Patent Application No. 3-34033).
6, 4-30220, 4-34194).

[0004]

However, there are some problems. For example, even if anodizing is performed, the adhesion of the oxide film varies depending on the location,
In some cases, it was peeled off. In addition, since aluminum oxide has extremely high corrosion resistance, it cannot be easily removed by ordinary wet etching or dry etching. Aluminum oxide has a remarkably high etching selectivity with respect to silicon oxide, and a material such as silicon oxide in the periphery may be significantly etched during the etching of aluminum oxide. In particular, when configuring a complicated circuit, the gate electrode wirings of a number of transistors are connected to one wiring to perform anodic oxidation, but the wiring for that purpose must be removed later. It was difficult to remove the wiring covered with aluminum oxide. Further, when a contact is to be formed in a limited portion of these gate electrode wirings, the erosion of even the surrounding materials has been a great constraint on the fabrication of the circuit.

On the other hand, for example, Japanese Patent Application No. 3-3481
As described in No. 30, a high-energy electromagnetic wave such as a laser beam is intensively irradiated on the etching portion,
A method for removing the aluminum oxide and the underlying gate electrode wiring in that portion was proposed. However, in such a method, even the underlying gate electrode wiring is removed or suffers considerable damage, making it almost impossible to form a contact.

The present invention has been made in view of such problems, and an object thereof is to propose a method of stably manufacturing an anodized aluminum gate transistor and a circuit arrangement suitable for the method.

[0007]

[Means for Solving the Problems] As pointed out above, in the fabrication of an anodized aluminum gate transistor, the variation in adhesion due to the peeling of the anodized film, the removal of unnecessary wiring after the anodization and the contact hole Formation. Among them, as a result of research conducted by the present inventors, it has become clear that it is only necessary to optimize the wiring up to the gate electrode wiring.
That is, conventionally, no special consideration was given to the width of the wiring, so that the potential was different between the gate electrode wirings. This is because the current path leading to the gate electrode wiring was not considered. And in such a situation,
Even if anodic oxidation progresses in the same way, the thickness of the anodic oxide film occupying the wiring width increases earlier in places where the line width is narrower than in places where the line width is wider, and as a result, the difference is due to variations in adhesion. And led to peeling. Therefore, in the present invention, as shown in FIG. 1A, the wiring up to the gate electrode wiring is hierarchized by its width.

That is, the wiring extending from the current source is the main wiring 13 having the widest width, the branch wiring 5 narrower than the main wiring is provided, and the gate electrode wiring 6 at the end is provided. With such a circuit arrangement,
The difference in the progress of anodic oxidation between the terminal gate electrode wirings was remarkably suppressed, and the adhesion of the anodic oxide film of each gate electrode wiring could be made almost constant.

In order to solve the problem of the present invention, in the present invention, a portion to be etched or a contact is formed later is coated with an organic coating material so as not to be anodized. It is desirable that the organic coating material has a heat resistance of at least 270 ° C.
For that purpose, a polyimide organic material is suitable. In particular, photo nice (photosensitive polyimide) is preferable because patterning is easy. Such organic coating materials are easily removed by a suitable solvent (eg, hydrazine) or plasma in an atmosphere of oxygen or another oxidizing gas (eg, nitrogen dioxide, ozone, etc.). On the other hand, it has oxidation resistance enough to withstand anodic oxidation.

FIG. 5 shows a photo nice (UR38 manufactured by Toray Industries, Inc.).
FIG. 4 shows the relationship between the etching rate and the atmospheric pressure in oxygen plasma of FIG. Oxygen partial pressure is 100
%. The thickness of the photonice was 2.3 μm, and etching (ashing) was performed by applying RF power to the parallel plate electrodes at room temperature to generate plasma. The atmosphere is oxygen and the oxygen flow rate is 2.3 SCCM. As is clear from the figure, the etching rate is proportional to the plasma pressure. Although not shown in the figure,
As the temperature at the time of ashing was higher, the etching rate was increased. In the range from room temperature to 300 ° C., linear etching rate dependence was observed. In the etching using the oxidizing gas plasma, the higher the partial pressure of the oxidizing gas, the better the etching characteristics.

After removing the organic coating material, the metal wiring is exposed, so that the etching is easy, and there is no problem in forming a contact.
In particular, in forming a contact, after forming an interlayer insulator, a contact hole may be formed as usual, and a contact may be provided. Examples are shown below,
Further, the present invention will be described.

[0012]

【Example】

Embodiment 1 FIGS. 1 and 2 show this embodiment. FIG.
FIG. 2 shows a conceptual cross section of each step in order to make the steps of the present invention easy to understand. Accordingly, FIG. 2 is not a cross-section of any particular portion of FIG.

First, Corning 7059 glass was used as the substrate 1. Then, the underlying silicon oxide film 2 is formed to a thickness of 1
Only a thickness of 00 nm was formed by a sputtering method. further,
An amorphous silicon film was formed to a thickness of 150 nm by a plasma CVD method. This at 600 ° C for 60 hours
Annealed in a nitrogen atmosphere and recrystallized. further,
This was patterned to form a plurality of island-shaped semiconductor regions 3.

Further, a gate oxide film 4 is deposited to a thickness of 115 nm by a sputtering method in an oxygen atmosphere using silicon oxide as a target, and then an aluminum film (500 nm in thickness) is formed by electron beam evaporation. This was patterned to form a first wiring 5, a second wiring 13, and a gate electrode wiring 6. Here, the first wiring is a branch wiring according to the present invention, and the second wiring is a main wiring. The width of these wirings was 4 μm for the first wiring and 10 μm for the second wiring. Thus, the outer shape of the thin film transistor (TFT) was adjusted. TFT at this time
The channel had a length of 2 μm and a width of 12 μm.

Further, 5 wt.
% Nitric acid and phosphoric acid were used. For example, when the etching temperature is 40 ° C., wiring (aluminum)
Was 225 nm / min. The state so far is shown in FIGS. 1A and 2A.

Further, Photo Nice (Toray UR380)
0) was applied by a spin coater. 25 rpm
It was 00 rpm. After drying for 1 hour in a nitrogen atmosphere at 80 ° C., the photonice was patterned. In this case, the first wiring 5 and the second wiring 13 are left over the entire surface. Then, by baking at 300 ° C. for 0.5 to 2 hours, the photonice is made into a polyimide, and electricity is passed through the wirings 13, 5, and 6, and the gate electrode on which the photonice is not applied is anodized by the anodic oxidation method. An aluminum oxide coating 8 was formed around the wiring (top and side). Anodization was performed using a solution in which a 3% solution of tartaric acid in ethylene glycol was neutralized with 5% ammonia to adjust the pH to 7.0 ± 0.2. First, platinum was immersed in the solution as a cathode, and the TFT was immersed together with the substrate, and the second wiring 13 was connected to the anode of the power supply. The temperature was kept at 25 ± 2 ° C.

In this state, 0.1 to 0.5 mA /
flowing a current of cm ^2, When voltage reaches 250V, energized while keeping the voltage constant, current 0.005 mA / c
When the current reached m ² , the current was stopped and anodization was terminated. After the anodization was completed, photonice was removed by ashing in oxygen plasma of 0.2 to 2.0 Torr and RF power of 0.1 to 0.3 W / cm ² .
At this time, if the substrate temperature was heated to 90 to 300 ° C., the etching rate could be further improved. The thickness of the anodic oxide film thus obtained was 320 nm. FIGS. 1B and 2B show the state of the circuit obtained so far.

Next, an N-type impurity region (source / drain) 9a or a P-type impurity region 9b was formed in the semiconductor region 3 by ion implantation. Phosphorus ions are used as the N-type dopant, and the ion energy is 70.
-100 keV, and the concentration of phosphorus was 1-5 × 10 ¹³ cm ⁻² . BF ₃ ⁺ was used as the P-type dopant. The dose and the acceleration energy were set to the same conditions as those for doping with phosphorus. By this ion implantation, the source,
In the drain region 9, a portion (offset region) which does not overlap with the gate electrode has a thickness of aluminum oxide (about 300 n
m) is presumed to have been formed.

Next, the photonice was removed and laser annealing was performed. As a laser, a KrF excimer laser was used, and a laser pulse having a power density of, for example, 350 mJ / cm ² was irradiated for 50 shots. By this laser annealing, the portion which was made amorphous by ion implantation was recrystallized. In this step, the same effect was obtained even when irradiation was performed using a halogen lamp or the like instead of the laser. FIGS. 1C and 2C show the states of the circuit obtained so far.

Next, as shown in FIG. 1D, a part of the first wiring and the entirety of the second wiring are selectively removed, and C
A large number of MOS gate arrays were formed. Part of the first wiring was left as shown by 5a. Then, FIG. 2 (D)
As shown in FIG. 1, an interlayer insulator 10 is formed by sputtering a silicon oxide film, and contact holes 11a, 1a, 1a, and 1b are formed on the semiconductor region 3 by a known photolithography technique.
1b, and at the same time, a contact hole 12 was also formed on the first wiring 5a. Of course, the contact holes need not always be formed at the same time, and if necessary, these contact holes may be formed independently. Thereafter, if a metal film is selectively formed, a semiconductor circuit is completed.

Embodiment 2 FIG. 3 shows this embodiment. Note that the wiring pattern viewed from above is substantially the same as FIG.

First, Corning 7059 is used as the substrate 21.
Glass was used. Then, the underlying silicon oxide film 22 was formed to a thickness of 100 nm by a sputtering method. Further, an amorphous silicon film was formed to a thickness of 50 nm by the LPCVD method. This was irradiated with a pulse laser to be crystallized. Further, this was patterned to form a plurality of island-shaped semiconductor regions 23.

Further, a gate oxide film 24 is deposited to a thickness of 115 nm by sputtering in an oxygen atmosphere targeting silicon oxide, and then an aluminum film (500 nm in thickness) is formed by electron beam evaporation. ,
This was patterned to form a first wiring 25 and a gate electrode wiring 26. Thus, the outer shape of the thin film transistor (TFT) was adjusted. The size of the TFT channel at this time was 2 μm in length and 12 μm in width.

Also, 5 wt.
% Nitric acid and phosphoric acid were used. For example, when the etching temperature is 40 ° C., wiring (aluminum)
Was 225 nm / min. The state so far is shown in FIG.

Further, Photo Nice (Toray UR380)
0) was applied. Then, this photonice was patterned and left only on the wiring 25 as shown in FIG. Then, electricity is passed through the wirings 25 and 26,
An aluminum oxide film 28 was formed around the gate electrode wiring not coated with photonice (upper surface and side surfaces) by an anodizing method. Anodization was performed using a solution in which a 3% solution of tartaric acid in ethylene glycol was neutralized with 5% ammonia to adjust the pH to 7.0 ± 0.2. First, platinum is immersed in a solution as a cathode, and T
The FT was immersed together with the substrate, and the wiring was connected to the anode of the power supply.
The temperature was kept at 25 ± 2 ° C.

In this state, first, 0.1 to 0.5 mA /
flowing a current of cm ^2, When voltage reaches 250V, energized while keeping the voltage constant, current 0.005 mA / c
When the current reached m ² , the current was stopped and anodization was terminated. The thickness of the anodic oxide film thus obtained is 320
nm. The state of the circuit obtained so far is shown in FIG.
It is shown in (B).

Next, an N-type impurity region (source / drain) 29a or a P-type impurity region 29b was formed in the semiconductor region 23 by ion implantation. Phosphorus ions are used as the N-type dopant, the ion energy is 70 to 100 keV, and the phosphorus concentration is 1 to 5 × 10 ¹³ c.
m ^-2 . Further, as the P-type dopant, BF ₃
Used ⁺ . The dose and the acceleration energy were set to the same conditions as those for doping with phosphorus. As a result of this ion implantation, a portion (offset region) of the source / drain region 29 which does not overlap with the gate electrode has a thickness of aluminum oxide (about 3
00 nm). This step may be performed by plasma doping (also referred to as ion doping) that cannot separate ions by mass, or may be performed by another appropriate doping method.

Next, the photonice was removed and laser annealing was performed. At this time, unlike in Example 1, laser was irradiated from the back surface of the substrate (see FIG. 3C). The laser is a XeCl excimer laser (wavelength 3
08 nm) or XeF excimer laser (wavelength 3
50 nm). Here, in selecting a laser, the light transmittance of the substrate (here, Corning 7059) must be considered. For quartz, a KrF laser (wavelength 248 nm) may be used. In this example, as shown in FIG. 3C, laser irradiation was performed from the back surface, and for example, 10 shots of a laser pulse having a power density of 350 mJ / cm ² were irradiated. By this laser annealing, the portion which was made amorphous by ion implantation was recrystallized. In this step, the same effect was obtained even when irradiation was performed using a halogen lamp or the like instead of the laser.

This method is the same as that of the first embodiment in that the activation of the impurity region is performed by laser annealing (or lamp annealing), but the second laser annealing (or lamp annealing) is performed from the back surface of the substrate. By doing so, an object is to form a continuous connection between the impurity region and the channel formation region. Defects due to discontinuous boundaries will be described later. However, when laser irradiation (or lamp annealing) is performed only from the back surface, only the substrate side of the silicon layer may be well crystallized and may not reach the entire impurity region. For more reliable crystallization, laser irradiation (or lamp annealing) may be performed from both sides.

When the laser (or lamp annealing) is applied from the upper surface as in the first embodiment, the wiring is separated due to the difference in the coefficient of thermal expansion at the interface between the non-anodized region and the anodized region. Was observed,
Since there is no such difference on the back surface, peeling of the wiring was suppressed by irradiation from the back surface.

Thereafter, a part of the wiring 25 is removed, and
As shown in FIG. 3D, an interlayer insulator 30 is formed by sputter deposition of silicon oxide, contact holes 31a and 31b are formed on the semiconductor region 23 by a known photolithography technique, and wiring is simultaneously performed. A contact hole 32 was also formed on 25a. Of course, the contact holes need not always be formed at the same time, and if necessary, these contact holes may be formed independently. Thereafter, if a metal film is selectively formed, a semiconductor circuit is completed.

FIG. 4 shows an example of the characteristics of the obtained device (NMOS). FIG. 4A shows the device characteristics when laser irradiation for activating the impurity region is performed from the upper surface. The initial characteristics (indicated by a in FIG. 4A) are good, but the gate has 25 to 25%. When a pulse of 30 V is continuously applied, b
It has deteriorated as shown by. This is considered to be because the interface between the impurity region and the channel formation region is discontinuous, the junction is weak, and hydrogen or the like terminating the dangling bond has been released by application of a voltage for a long time.

On the other hand, when the laser irradiation was performed from the back surface, neither the initial characteristics (indicated by c in the figure) nor the characteristics after 100 hours (indicated by d in the figure) changed. Thus, the effect of laser irradiation from the back surface was confirmed.

[0034]

As described above, according to the present invention, the wiring patterning of the anodized aluminum gate transistor can be performed as easily as in the case of the conventional transistor. In particular, it is believed that the present invention is advantageous for microfabrication. This is because aluminum oxide cannot be removed by a normal dry etching process other than a special method such as laser etching, and is mainly performed by wet etching. However,
Since micro-processing was difficult with wet etching,
The manufactured device was also of low integration. According to the present invention, a dry etching process can be used, fine processing can be performed, and the yield can be improved.

In the embodiments of the present invention, the transistor on the insulating substrate has been described. This is used, for example, in an active matrix of a liquid crystal display device, but this asserts that the present invention cannot be used for manufacturing a transistor on a semiconductor substrate, that is, a normal semiconductor integrated circuit. It does not do. Rather, if a semiconductor integrated circuit is fabricated on a semiconductor substrate at a low temperature by using a laser annealing process according to the present invention, the characteristics of the device will be better than those of a conventional silicon gate. The present invention is also effective when forming a TFT on an insulating layer on a semiconductor substrate. As described above, the present invention is widely used as a basic technology required for manufacturing a semiconductor circuit, and its industrial value is great.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of a semiconductor circuit of the present invention. (Top view)

FIG. 2 shows a process for manufacturing a semiconductor circuit of the present invention. (Cross section)

FIG. 3 shows a manufacturing process of the semiconductor circuit of the present invention. (Cross section)

FIG. 4 shows an example of characteristics of an element obtained in an example.

FIG. 5 shows an example of the etching characteristics of Photo Nice.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Base oxide film 3 Semiconductor region 4 Gate insulating film 5 First wiring 6 Gate electrode wiring 7 Organic coating material 8 Anodized film 9 Impurity region (source / drain) 10 Interlayer insulator 11 Contact hole (for impurity region) 12 contact hole (for first wiring) 13 second wiring

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shunpei Yamazaki 398 Hase, Atsugi-shi, Kanagawa Examiner, Semiconductor Energy Laboratory Co., Ltd. Examiner Masashi Migita (56) References JP-A 1-237525 (JP, A) JP JP-A-58-23479 (JP, A) JP-A-1-248136 (JP, A) JP-A-2-272430 (JP, A) JP-A-61-99186 (JP, A) (58) Fields investigated (Int) .Cl. ⁷ , DB name) G02F 1/1362 H01L 29/78

Claims (6)

(57) [Claims] A gate electrode, a first wiring electrically connected to the gate electrode, above a substrate having an insulating surface;
Forming a second wiring electrically connected to the first wiring, covering a part of the first wiring and the second wiring with an organic material, and oxidizing a surface of the gate electrode. A method for manufacturing an electronic circuit, comprising: removing at least the organic material of the second wiring; and removing the second wiring. 2. The method according to claim 1 , wherein the gate electrode and the wiring are on the same film. 3. The method according to claim 1 , wherein the organic material is a polyimide-based organic material. 4. The method according to claim 1 , wherein the gate electrode and the wiring are made of aluminum. 5. The method for manufacturing an electronic circuit according to claim 1 , wherein the organic material has a heat resistance of 270 ° C. or higher. 6. The method according to claim 1 , wherein the organic material is removed by etching in an oxygen or oxidizing atmosphere.