JP3119740B2 - Internal power supply switching circuit for semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal power supply switching circuit for a semiconductor memory such as a flash memory (batch erase EEPROM) which uses different internal power supply voltages for data reading and writing. Generally, in a flash memory, the electrode voltage of a memory cell transistor is different between a read mode and a write (or erase) mode.
Switching of the internal power supply voltage is performed for each mode.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram of a conventional internal power supply switching circuit. Reference numeral 100 denotes a power supply line (hereinafter referred to as an external power supply line) to which an external power supply (V _CC ) having a potential of +5 V is applied. For example, a power supply line to which an external power supply (V _PP ) having a potential of +12 V is applied (hereinafter, an external power supply line), 1
02 is an internal power supply (V) connected to the control electrode of the memory cell transistor via a row decoder (not shown).
_PI ) (hereinafter referred to as an internal power line). The connection destination of the internal power supply line 102 is a representative example.

A MOS transistor Q _{1 that} is turned on when the signal G ₁ is at H level is connected between the external power supply line 100 and the internal power supply line 102. the, the MOS transistor Q ₂ to which the signal G ₂ is turned on when the L level, MOS transistor Q of the complementary relationship the Q ₁ is turned on in the off
₃ and is connected to the series via a node N _1.
Here, Q ₁ is an n-channel depletion type, and Q ₂
And Q ₃ is an enhancement type p-channel, Q ₂ wells (n-well) to the external power source line 101,
Q ₃ wells (n-well) are connected to the internal power supply line 102.

According to such a configuration, when the signal G ₁ and the signal G ₂ are set to the H level, Q ₁ is turned on, and Q ₂ and Q ₃ are turned on.
Is turned off, the internal power line 102 is connected to the external power line 100
(V _CC ; +5 V). Conversely, when the signal G ₁ and the signal G ₂ are set to L level, Q ₁
Are turned off and Q ₂ and Q ₃ are turned on.
2 can represent the potential of the external power supply line (V _PP ; +12 V). Thus, by controlling the read and the level of the signal G ₁ and the signal G ₂ for each mode of write, to generate an internal power supply voltage (V _PI) having a potential adapted to each mode (V _CC or V _PP) Can be.

FIG. 12 shows an actual timing chart of a conventional example.
It is. In the read mode, the signal G₁Is at H level (V
_CC+ 5V), signal G_TwoIs at H level (V_PP; + 12V)
Which gives V_PI= V_CC(+ 5V)
You. When shifting to the write mode, first, the signal G₁To
L level and Q₁Off, Q_ThreeAfter turning on the signal
G_TwoIs gradually reduced to the L level. This
When node N₁Of the ON state Q_ThreeBy V
_PI(+ 5V). Time passes and signal G_TwoLevel
Is Q_TwoWhen it goes down to the point where it turns on, this Q_TwoThrough
External power line 101 and node N₁Are connected. This
Node N₁Is the Q that is already on_ThreeThrough
Connected to the internal power line 102,
A current flows from the power supply line 101 to the internal power supply line 102,
_PIIs V _PP(+ 12V).

[0006] Here, the gradually reducing the level of the signal G ₂ upon transition to the write mode for the following reason. That is, when the level of the signal G ₂ (gate level of Q ₂ ) is immediately changed to L level (0 V), this Q ₂ corresponds to a large potential difference between V _PP (+12 V) and the gate level (0 V). A large amount of channel current i _ch2 flows,
At this time, the channel current i _ch3 of Q ₃ can only flow a small amount of current corresponding to a relatively small potential difference between the potential of the node N ₁ (in this case, +5 V) and the gate level (0 V). residual current (i _ch2 -i _ch3) flows into the n-well from the p-channel diffusion layers of the source region of the Q ₃ (node n ₁ side), a large substrate current is generated.

As a result, a parasitic pnpn thyristor (parasiti
c pnpn thyristor) is turned on to easily cause a fatal phenomenon such as fixing the MOS device to a low impedance state, so-called latch up phenomenon. In the prior art, by gradually reducing the level of the signal G _2, avoiding a sudden increase in i _ch2, thereby preventing the occurrence of the latch-up phenomenon to suppress the substrate current.

[0008]

However, in such a conventional internal power supply switching circuit of a semiconductor memory,
It is necessary to secure a wait time between the read mode and the write mode for avoiding the latch-up phenomenon. The wait time includes a time constant of the level decrease of the signal G ₁ and Q
_Since a margin for absorbing a manufacturing error and the like of ₂ is included, the mode switching cannot be performed at a high speed, which has been an obstacle in realizing a high-speed external storage device that is readable and writable, for example. [Purpose] Accordingly, an object of the present invention is to provide an internal power supply switching technique that can minimize the waiting time from the read mode to the write mode and contributes to the realization of, for example, a high-speed external storage device that is readable and writable.

[0009]

The present invention achieves the above object.
As shown in FIG.
One of the pole or the source electrode is connected to the first power supply line 1, and the other is
Is connected to the second power supply line 2 and is a first MOS transistor having a first polarity.
Jista Q₁And one of a drain electrode or a source electrode and
The well is connected to the potential V of the first power supply line 1._CCHigher potential V
_PPAnd the other is connected to the node N₁Connect to
The second MOS transistor Q of the second polarity _TwoAnd the drain
One of the electrode and the source electrode is connected to the node N₁Connect to
A second polarity in which the other and the well are connected to the second power supply line 2
Of the third MOS transistor Q_ThreeAnd a semiconductor device comprising
In the internal power supply switching circuit of the memory, the drain electrode or
One of the source electrodes is connected to the third power supply line 3, and the other is
A fourth MOS transistor of a first polarity connected to the second power supply line 2
Transistor Q_FourIt is characterized by having.

The first polarity is an n-channel type and the second polarity is
Polarity means p-channel type.

[0011]

According to the present invention, in the course transition from the read mode to the write mode, Q ₄ is turned on, the Q ₄ through the second power supply line 2 of the electric potential V _PI is the first power supply line 1 potential V _CC or lifted (lifting potential is dependent on the gate potential of the Q _4), the lifted V _PI is transmitted through Q ₃ in the oN state to the node N _1.

Therefore, the node N _{1 during the} mode transition
Is increased to at least V _CC or more, the drain-source voltage of Q ₂ (corresponding to the difference between the potential of N ₁ and V _PP ) can be reduced to suppress the channel current of Q ₂ . The gate of Q ₃ - source voltage (G ₁ and N
By increasing the equivalent) to the difference between the _first potential can be increased channel current capability of the Q _3. As a result, it is possible to take account balance of the channel current of Q _3, the occurrence of the latch-up phenomenon can be reliably prevented by suppressing the substrate current.

As described above, according to the present invention, the latch-up phenomenon does not occur even if the gate level of Q ₂ is immediately changed to the L level.
Can be less extent to lift the _first level time, for example, it can provide a useful internal power source switching technology contributes to realization of a readable and writable high-speed external memory device.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 10 show an embodiment of the present invention, and are examples of application to a flash memory. First, the configuration will be described. In FIG. 2, reference numeral 11 denotes a flash memory (hereinafter referred to as an EEPROM). 17, memory cell array 18, column gate 19, sense amplifier 2
0, a write amplifier 21, a data out buffer 22, a data in buffer 23, an erase amplifier 24, a control circuit 25, a control buffer 26, an internal power supply switching circuit 27, and a high voltage detection circuit 28. 29 is a plurality of bit address signal terminals, 30 is a plurality of column address signal terminals, 31
Is a data in / out terminal, 32 is various control signal terminals, 33 is a high voltage power supply (V _PP ) for writing.
Terminal.

Here, the internal power supply switching circuit 27 supplies two external power supply voltages (V
_CC, select one of the V _PP), and outputs as the internal power supply voltage (V _PI), the internal power supply voltage (V _PI), in this example, row decoder 16, column decoder 17, a write amplifier 21 and It is supplied to the erase amplifier 24. FIG. 3 is a diagram showing the configuration of the row decoder 16.
6, a plurality of n-channel MOS (hereinafter nMOS) transistor Q ₁₀ to Q _12, which receives signals from the row predecoder 14 to the gate, nMOS transistor Q ₁₃ and the internal power supply voltage as a load element and (V _PI) Ground (0V)
When all of the signals Q _{10 to} Q ₁₂ are in the ON state, that is, when the signals from the row predecoder 14 are all at the H level, the p-channel MOS (hereinafter referred to as pMOS) transistor Q ₁₄ and the nMOS transistor Q ₁₅ The internal power supply voltage (V _PI ) appears at the output of the CMOS inverter gate 16a. Here, CMOS inverter gate 1
The output ( _VPI or 0 V) of the memory cell array 18a
, And is supplied to the control gate of a memory transistor in a row unit in the memory cell array 18 via this word line.

FIG. 4 is a block diagram of the column decoder 17. The column decoder 17 includes a plurality of nMOS transistors Q ₁₆ and Q ₁₇ receiving a signal from the column predecoder 15 at a gate, and an nMOS transistor Q as a load element. ₁₈ is connected between the internal power supply voltage (V _PI ) and the ground (0 V), and when all of Q ₁₆ and Q ₁₇ are in the ON state, that is, when all the signals from the column predecoder 15 are at the H level, the pMOS the output of the CMOS inverter gate 17a comprising transistors Q ₁₉ and the nMOS transistor Q ₂₀ is intended to represent the internal power supply voltage (V _PI). here,
The output of the CMOS inverter gate 17a ( _VPI or 0
V) is applied to the gate of the bit line select transistor in the column gate 19.

FIG. 5 is a configuration diagram of the write amplifier 21.
The write amplifier 21 includes two nMOS transistors Q ₂₁ and Q ₂₂ that are turned on when both the signal indicating the write mode from the control circuit 25 and the write data from the data-in buffer 23 are at the H level. the internal power supply voltage and the nMOS transistor Q ₂₃ of (V
_PI ) and ground (0V) and pMOS
When provided with a CMOS inverter gate 21a comprising transistors Q ₂₄ and the nMOS transistor Q _25, and one nMOS transistor Q ₂₆ of the output stage, the two nMOS transistors Q _21, Q ₂₂ was both turned on,
Through the transistor Q ₂₆ of the output stage and supplies the internal power supply voltage (V _PI) to the bit line of the column gate 19.

[0018] FIG. 6 is a block diagram of Irezuanpu 24, Irezuanpu 24, the nMOS transistor Q ₂₇ becomes ON state in response to the H-level signal indicating the erase mode from the control circuit 25, as a load element CMO that of an nMOS transistor Q ₂₈ an internal power supply voltage (V _PI) as well as connected between ground (0V), a pMOS transistor Q ₂₉ and the nMOS transistor Q ₃₀
S inverter gate 24a, pMOS transistor Q ₃₁
The nMOS transistor Q ₃₂ a CMOS inverter gate 24b, and the pMOS transistor Q ₃₃ and nM
It constitutes connected OS transistor Q ₃₄ a CMOS inverter gate 24c consisting of between the internal power supply voltage (V _PI) and ground, respectively (0V), when the nMOS transistor Q ₂₇ is turned on, the memory cell array 18
The internal power supply voltage (V _PI ) is collectively applied to each source electrode of the memory cell transistor.

FIGS. 7 and 8 show the internal power supply switching circuit 27.
3 is a configuration diagram of a high-voltage detection circuit 28. FIG. Figure 7
And B₁, B_TwoIs B in FIG._ThreeB_FourWith the internal power off
The four blocks constituting the switching circuit 27 are represented for convenience.
ing. Block B₁Is the same as the configuration of FIG.
Here, the same circuit symbols as those in FIG. 1 are used. You
That is, 1 is the external power supply V_CCPower line (first power line),
2 is the internal power supply V_PIPower line (second power line), 3 is external
Power supply V_PP(However, V_PP>> V_CC) For power line, Q₁Is
Connect either the rain electrode or the source electrode to the first power line 1
And the other is connected to the second power supply line 2 with the first polarity (n channel).
1st MOS transistor, Q _TwoIs the drain electrode
Alternatively, connect one of the source electrodes and the well to the third power supply line 3
And the other node N₁Connected to the second polarity (p-channel
Type) second MOS transistor, Q_ThreeIs the drain electrode or
Represents one of the source electrodes at the node N₁To the other end
And a second well (p-channel) having a well and a well connected to the second power line 2.
(A channel type) third MOS transistor. here,
Q_FourRepresents one of the drain electrode and the source electrode as a third power supply line
3 connected to the second power line 2
(N-channel type) fourth MOS transistor
This is a circuit element that is a point of the embodiment.

Block B_Two~ B_FourAre the above MOS transistors
Transistor Q₁~ Q_FourTo control the on / off of
No.G₁, G_TwoAnd G_ThreeIs the part that causes
B_ThreeResponds to the output of the high voltage detection circuit 28,
The width is almost 0V to V_CCSignal G up to₁And the logic amplitude is almost 0
V-V_PPSignal G up to_Four, The block B _Four
Is the signal G_FourDelay signal G_TwoIs the part that causes

[0021] The high voltage detecting circuit 28, the potential of V _PP is at least pMOS transistor threshold voltage V of the threshold voltage V _th and the pMOS transistor Q ₄₁ of Q _{40 th}
Is higher than the potential of V _CC by the sum of (V _PP >>
To V _CC), the output of the CMOS inverter gate 28a made of a pMOS transistor Q ₄₁ and the nMOS transistor Q _42, represents a substantially V _PP -2 V _th equivalent H level, that level two-stage inverter gates 28b, a 28c via Output in phase.

The block B ₃ includes a high voltage detection circuit 2
8 is at the H level, that is, when V _PP >> V _CC , the two output nodes a of the state holding circuit 44 including the NOR gate 40, the NAND gate 41, the inverter gates 42 and 43, and the capacitors C ₁ and C ₂ b represents an L level, the level of one of the node a is taken out in the same phase via a two-stage inverter gates 44 and 45, inverters together with the four-stage level of the other node b and outputs it as signal G ₁ It is taken out in the same phase via a gate 46 to 49, and outputs a signal G _4. In addition, Q ₅₀ ~Q ₅₃ is n
MOS transistor, Q ₅₄ ~Q ₅₇ is a pMOS transistor.

[0023] Here, the power supply voltage of the inverter gate 45 is V _CC and ground (0V), the logic amplitude of the signal G ₁ is approximately 0V to V _CC. In addition, the inverter gate 4
Supply voltage 7,48,49 are V _PP and ground, the logic amplitude of the signal G ₄ are is substantially 0V to V _PP. Further, although illustration is omitted, the logical amplitude of the signal G ₂ taken out from the block B ₄ is almost 0V to V _PP. When V _PP >> V _CC , all of the signals G ₁ , G ₂ and G ₄ become 0 V. In other cases, the signal G ₁ substantially corresponds to V _CC and the signal G ₂
And G _{4 are} substantially equivalent to V _PP .

The block B ₂ is intended to constitute a well-known bootstrap circuit, a larger logic swing 0V to V _PP signal G ₄ (here, 0V to V _PP + V _th) signal G ₃ (although reversed phase) Is to occur. In FIG. 7, Q ₆₀ ~
Q ₇₀ is an nMOS transistor, Q _{71 to} Q ₇₄ are pMOS transistors, C ₁₀ and C ₁₁ are capacitors, 50 is Q ₇₁ and Q
Inverter gate composed of _65, 51 denotes an inverter gate composed of Q ₇₄ and Q _70, 52 is an inverter gate composed of Q ₇₃ and Q _68, 53 is an inverter gate composed of Q ₇₂ and Q ₆₇ is there.

FIG. 9 is a waveform diagram showing the process of generating the signals G ₃ in the block B _2. In this figure, the signal G ₄
Falls, the potential of the output node (a) of the inverter gate 50 rises to V _PP , and at the same time, the potential of the output node (b) of the inverter gate 51 falls to 0V. Node potential V _PP -V _th node (f) in accordance with the potential change (i) (V _th is the threshold voltage of Q ₆₄₎ rises up, C ₁₁ is charged by the potential. On the other hand, node (b)
Charge to C ₁₀ with a change in potential (V _PP → 0V) is discharged, the potential of the node (c) begins to descend along the constant curve when given by the channel resistance of the capacitor to C ₁₀ and Q _69, When the potential of the node (c) falls below the threshold value of the inverter gate 52, the potential of the node (d) falls to 0 V and the Q ₆₆ is turned off.

Q₆₆Is turned off, the potential of the node (e) becomes
V_PP-2V_th(2V_thIs Q₆₄And Q₆₀Threshold voltage)
, Which causes the potential of the node (f) to rise
The potential of (e) is C₁₁Rise to the potential obtained by adding the voltage across
You. That is, the potential of the node (f) rises.
The potential of the node (e) is equal to the potential −V of the node (f).
_th(V_thIs Q_TenThreshold voltage).
Finally, the potential of the node (e) becomes V_PPUntil also the node
The potential of (f) is equal to the potential of node (e) by C₁₁The voltage across
The potential increases to the applied potential, and as a result, the signal G
_FourLogic amplitude of 0V to V _PP(Here, 0V to V_PP
+ V_th) Signal G_ThreeIs generated.

FIG. 10 is an operation waveform diagram of the block B _1, a diagram illustrating a shifting operation of the internal power supply voltage V _PI during the transition from the read mode to the write mode. In this figure, during the read mode, the signals G ₁ → V _CC , the signals G ₂ → V _PP , and the signals G ₃ → 0V, and only Q ₁ is on. Therefore, during the read mode, V _PI = V _CC
It is.

To shift to the write mode, first,
Off Q ₁ and the signal G ₁ to 0V, and turn on the Q _3, V
_While keeping _PI = V _CC , the potential of the node N ₁ is raised to V _PI (= V _CC ) through Q ₃ . Then, start-up signal G ₃ by a signal G ₄ to 0V to V _PP + V _th, Q
Turn on ₄ . As a result, current flows from the third power supply line 3 to the second power supply line 2, and _VPI in the period rises to _VPP .

Here, since the potential of the node N ₁ during the period is V _PI , that is, V _PP , the potential difference between the source and the drain of Q ₂ is 0V. Therefore, even if the signal G ₂ to 0V, and a large current does not flow immediately to the Q _2.
Further, since also potential difference between the p-channel diffusion layer and the n-well of the source of Q ₃ (Node N ₁₎ becomes 0V Similarly, no flow substrate current becomes a factor causing a latch-up phenomenon. Incidentally, in a state in which the signal G ₂ to 0V, and when starting the actual write operation of the memory cell, the cell current is the third power supply line 3 → Q ₂ → node N ₁ → Q ₃ → second power supply line 2 →→→ Supplied to the memory cell array 18 without any problem.

[0030] As described above, in this embodiment, since there is no risk of causing latch-up phenomenon even when reduced to promptly 0V gate level Q _2, latency in the transition from the read mode to the write mode (Corresponding to + in FIG. 10) can be set to the minimum necessary, that is, the short time necessary for stable operation of the device, and the mode switching can be speeded up, contributing to the realization of, for example, a high-speed external storage device that can be read and written. An internal power supply switching technique can be provided.

In this embodiment, V _PI during the period is
In order to increase to the maximum potential (V _PP), but the high potential level of the signal G ₃ is set to V _PP + V _th, but not limited thereto. At least _VPI in the period, _Vcc
Long as it can increase the above, the high potential level V _CC + V _th of the signal G _3, or V _CC + V _th ~V _PP + until V _th, or may be a V _PP + V _th or higher.

[0032]

According to the present invention, with the above-described configuration, the waiting time from the read mode to the write mode can be minimized, and for example, a useful internal memory that contributes to the realization of a high-speed external storage device that is readable and writable. Power supply switching technology can be provided.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block diagram of a flash memory according to one embodiment.

FIG. 3 is a configuration diagram of a row decoder of one embodiment.

FIG. 4 is a configuration diagram of a column decoder of one embodiment.

FIG. 5 is a configuration diagram of a write amplifier according to one embodiment.

FIG. 6 is a configuration diagram of an erase amplifier according to one embodiment.

FIG. 7 is a block B ₁ of an internal power supply switching circuit according to one embodiment;
And is a configuration diagram of a block B _2.

8 is a block diagram of the block B ₃ and the block B ₄ of the high voltage detection circuit and an internal power source switching circuit of an embodiment.

FIG. 9 is a block B ₂ of an internal power supply switching circuit according to one embodiment;
It is a waveform diagram showing the process of generating the signals G ₃ in.

FIG. 10 is a block B of an internal power supply switching circuit according to one embodiment;
_{3 is} an operation waveform diagram of FIG.

FIG. 11 is a configuration diagram of a conventional example.

FIG. 12 is an operation waveform diagram of a conventional example.

[Explanation of symbols]

1: the first power supply line 2: second power supply line 3: third power line N _1: Node Q _1: first 1MOS transistor Q _2: The 2MOS transistor Q _3: The 3MOS transistor Q _4: first 4MOS transistor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (3)

(57) [Claims] 1. One of a drain electrode and a source electrode is a first electrode.
A first MOS transistor (Q ₁ ) of a first polarity connected to the power supply line (1) and the other connected to the second power supply line (2), and _one of the drain electrode or the source electrode and the well connected to the first power supply line ( The potential (V _PP ) higher than the potential (V _CC ) of 1)
, A second MOS transistor (Q ₂ ) having a second polarity connected to the third power supply line (3) and the other to a node (N ₁ ).
A third MOS transistor (Q ₃ ) having a second polarity, one of a drain electrode or a source electrode connected to the node (N ₁ ), and the other and a well connected to the second power supply line (2). A fourth MOS transistor having a first polarity, wherein one of a drain electrode and a source electrode is connected to the third power supply line (3) and the other is connected to the second power supply line (2). An internal power supply switching circuit for a semiconductor memory, comprising (Q ₄ ). 2. The first MOS transistor (Q)₁) And the first
3 MOS transistors (Q_Three) Complementary on / off operation
And the third MOS transistor (Q_Three)
Is the third MOS transistor (Q_Three) On and at the same time
Is later than the fourth MOS transistor (Q _Four)
After turning on, the second MOS transistor (Q_Two)
Controls each transistor to turn on
Internal power supply switching circuit of a semiconductor memory. Wherein said first 4MOS transistor gate voltage of (Q ₄₎ the transistor during the ON operation of the (Q _4), at least a 4MOS transistor (Q to the potential (V _CC) of said first power supply line (1) 3. The circuit according to claim 2, wherein the potential is equal to or higher than the potential obtained by adding the threshold value of ₄ ).