JP3116308B2 - PN code generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a device for generating a pulse of a pseudo-random code (hereinafter referred to as a PN code) used for spread spectrum communication.

[Prior art]

There are direct spread modulation, frequency hopping modulation and the like in spread spectrum communication, all of which require a random code sequence signal for secondary modulation. In order to obtain the random code sequence signal, a PN that obtains a pseudo random code sequence signal by using a shift register or the like conventionally.
There was a code generator.

[Problems to be solved by the invention]

However, in the conventional PN code generator as described above,
Even if the transmission / reception code was known, demodulation could not be performed unless a synchronized PN code was generated. Therefore, the present invention can manually adjust the phase of the synchronization of the PN code when the transmission / reception code is known.
It aims to provide a PN code generator.

[Means for Solving the Problems]

In order to solve the above-mentioned problems, a PN code generator according to the present invention includes a frequency dividing means for dividing a clock pulse signal and outputting it as a PN clock signal; an up-count signal output means for outputting an up-count signal; A down-count signal output means for outputting a signal; and a synchronous one-shot multi-output for outputting a one-shot pulse corresponding to one cycle of the PN clock signal when either the up-count signal or the down-count signal is input. When the up-count signal is input, while the one-shot pulse is input,
A pulse adding unit that adds a predetermined number of pulses to the PN clock signal by adding the clock pulse signal to the PN clock signal; and the one-shot pulse is input when the down-count signal is input. A pulse removing unit that removes a predetermined number of pulses from the PN clock signal by intercepting the PN clock signal, thereby adjusting and outputting the number of pulses of the PN clock signal. A clock adjusting circuit, and a PN output from the clock adjusting circuit.
A PN code output circuit for generating and outputting a PN code synchronized with the clock signal is provided. Further, the up-count signal output means and the down-count signal output means may be constituted by a single rotary encoder.

[Action]

In the present invention, the PN clock signal obtained by dividing the pulse signal by the dividing means is synchronized with the clock pulse signal, but the pulse interval is longer than the clock pulse signal. Therefore, by adding the clock pulse signal between the pulses of the PN clock signal by the pulse adding means,
The PN clock signal advances. Also, by removing a predetermined number of clock pulse signals from the PN clock signal by pulse removing means,
The clock signal is delayed. Therefore, by outputting the up-count signal from the up-count signal output means, the PN clock signal is advanced by the pulse adding means, and the down-count signal is output from the down-count signal output means. By delaying the synchronization, the synchronization of the PN code can be adjusted to a desired timing. Hereinafter, the operation of the present invention will be described in more detail based on a basic block diagram. FIG. 1 is a basic block diagram of a PN code generator according to the present invention. In FIG. 1, when an up-count signal U from an up-count signal output means 10a or a down-count signal D from a down-count signal output means 10b is input, the OR gate 1 outputs a pulse signal P1. The frequency divider 2 divides the frequency of the clock pulse signal P by a predetermined frequency division ratio N and outputs a clock frequency divided signal P2. When the pulse signal P1 is input, the synchronous one-shot multi 3 outputs a pulse signal P3 synchronized with the clock divided signal P2. This pulse signal P3 is a signal that defines the operation of adding and removing pulses. The AND gate 4 outputs an AND-processed pulse signal P4 of the clock pulse signal P and the clock divided signal P2, and the AND gate 5 outputs an AND-processed pulse signal P5 of the clock pulse signal P and the pulse signal P3. This pulse signal P5
Is a signal to which a pulse synchronized with the clock pulse signal P is added. The OR gate 6 performs an OR operation on the pulse signal P4 and the pulse signal P5 to output a pulse signal P6. This pulse signal P6 is
Clock divided signal based on the timing of pulse signal P3
This is a signal in which one pulse is added to P2. The NAND gate 7 has a down-count signal D and a pulse signal.
The pulse signal P7 is output by performing NAND processing on P3. This pulse signal P7 is a signal that defines pulse elimination. The AND gate 8 performs an AND operation on the pulse signal P6 and the pulse signal P7 to output a PN clock signal P8. That is, if there is no pulse signal P7, the pulse signal P6 to which one pulse is added is output as a PN clock signal. Output as a signal. Based on the PN clock signal P8, the PN code output circuit 9
Outputs PN code P9. In this way, if the transmission and reception codes are known,
By operating the up-count signal output means 10a or the down-count signal output means 10b, the PN code signal can be advanced or delayed to synchronize the PN code. Note that the frequency divider 2, the synchronous one-shot multi 3, a pulse adding circuit including AND gates 4, 5 and OR gate 6, a pulse removing circuit including NAND gate 7 and AND gate 8, up-count signal output means 10a, and The down-count signal output means 10b constitutes the clock adjustment circuit described in the claims.

【Example】

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram of the PN code generator of the embodiment, and FIG.
The figure is a signal waveform diagram of each part of the PN code generator. Reference numeral 10 denotes an audio encoder which outputs an up-count signal U and a down-count signal D. 11 and 12 are up-count signal U and down-count signal D, respectively.
This is a Schmidt gate that prevents chattering. 13 is SR
-D flip-flop, which outputs a pulse signal N. 1 is an inverted NOR gate, 14 is a Schmitt gate, and outputs a pulse signal P1 obtained by OR-processing the up-count signal U and the down-count signal D. Reference numeral 2 denotes a frequency divider which reduces the clock pulse signal P by half.
And outputs a clock divided signal P2. Reference numeral 3 denotes a flip-flop that outputs a pulse signal E using the pulse signal P1 as a clock, and 16 denotes a pulse signal synchronized with the clock frequency-divided signal P2 by the input of the pulse signal E.
This flip-flop outputs P3, and these flip-flop 3 and flip-flop 16 constitute a synchronous one-shot multi. 15 is a delay time adjusting circuit for the clock pulse signal P,
4 is an AND gate for performing an AND operation on the output of the delay time adjusting circuit 15 and the clock frequency-divided signal P2 to output a pulse signal P4, and 5 is an AND gate for processing the output of the delay time adjusting circuit 15 and the pulse signal P3. And an AND gate 6 for outputting a pulse signal P5.
OR gate that OR-processes and outputs pulse signal P6, 7
Is a NAND gate that performs NAND processing on the pulse signal P3 and the pulse signal N and outputs a pulse signal P7, and 8 is an AND gate that performs AND processing on the pulse signal P6 and the pulse signal P7 and outputs a PN clock signal P8 It is. The PN code P9 is output from the PN code output circuit 9 based on the PN clock signal P8. This PN code P9 is buffered and output by the output buffer circuit 18. Reference numeral 17 denotes a reset signal output circuit of the PN code output circuit 9. FIG. 3 shows signal waveforms at various parts of the PN code generator having the above configuration. In the PN code generator having the above configuration, the PN clock signal
To advance P8, the rotary encoder 10 is operated to generate an up-count signal U, and the flip-flop 3 and the flip-flop 16 use the clock frequency dividing signal P2.
And outputs a pulse signal P3 based on. The AND gate 5 outputs two pulse signals P5 arranged at a shorter interval than the pulse signal P4 by AND processing of the clock pulse signal P and the pulse signal P3. The OR gate 6 outputs a pulse signal P6 in which an additional pulse C1 is added to the pulse signal P4 by OR processing of the pulse signal P4 having the adjusted pulse width and the pulse signal P5. At this time, since the down-count signal D is not input, the pulse signal N becomes low level and the pulse signal P3
The pulse signal P7 becomes high level by the NAND processing of the pulse signal N and the pulse signal N.
P6 is output as it is as a PN clock signal P8. In this way, the synchronization of the generation of the PN code is advanced by the PN clock signal P8 to which the additional pulse C1 is added. On the other hand, when the PN clock signal P8 is delayed, the rotary encoder 10 is operated to generate the down-count signal D, and the pulse signal N is output from the SR-D flip-flop 13.
Is output as a high level. Then, the pulse signal P7 from the NAND gate 7 becomes low level due to the NAND of the pulse signal P3 and the pulse signal N. Therefore, when the pulse signal P7 is at the low level, no pulse is output from the AND gate 8, and the PN clock signal P8 is output with one pulse, that is, the removal pulse C2 removed. Thus, the synchronization of the generation of the PN code is delayed by the PN clock signal P8 from which the removal pulse C2 has been removed. The up-count signal output means and the down-count signal output means include a rotary encoder 10
It is needless to say that the present invention is not limited to this, and independent switches or the like may be used. In this way, according to this PN code generator, the phase of the synchronization of the PN code output circuit can be manually adjusted. This makes it possible to demodulate the spread modulated signal.

【effect】

In this way, according to the present invention, the synchronization phase adjustment can be performed manually by adding or removing a pulse from the PN clock signal input to the PN code output circuit when the transmission / reception code is known. , And it is possible to demodulate a signal subjected to spread spectrum modulation. Further, by outputting the up-count signal and the down-count signal by a single rotary encoder, an effect that operability is improved can be obtained.

[Brief description of the drawings]

FIG. 1 is a basic block diagram of a PN code generator according to the present invention, FIG. 2 is a circuit diagram of an embodiment, and FIG. 3 is a signal waveform diagram of each part of the PN code generator. 2 ... frequency divider, 5, 6 ... pulse addition circuit, 7, 8 ... pulse removal circuit, 9 ... PN code output circuit, 10 ... rotary encoder, 10a ... up-count signal output means, 10b
... Down count signal output means, U... Up count signal, D... Down count signal, P... Clock pulse signal, P2... Clock divided signal, P8... PN clock signal, P9.

Claims (2)

(57) [Claims] 1. A frequency dividing means for dividing a clock pulse signal and outputting it as a PN clock signal; an up-count signal outputting means for outputting an up-count signal; a down-count signal outputting means for outputting a down-count signal; A synchronous one-shot multi that outputs a one-shot pulse corresponding to one cycle of the PN clock signal when either the up-count signal or the down-count signal is input; and when the up-count signal is input. A pulse adding means for adding a predetermined number of pulses to the PN clock signal by adding the clock pulse signal to the PN clock signal while the one-shot pulse is being input; When the one-shot pulse is input, the PN A clock adjusting circuit configured to adjust and output the number of pulses of the PN clock signal by providing a pulse removing unit that removes a predetermined number of pulses from the PN clock signal by blocking the lock signal; and And a PN code output circuit for generating and outputting a PN code synchronized with the PN clock signal output from the clock adjustment circuit. 2. The PN code generator according to claim 1, wherein said up-count signal output means and said down-count signal output means are constituted by a single rotary encoder.