JP3114409B2 - Multi-carrier modulation receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for receiving a modulated wave composed of a plurality of sub-channels multiplexed on a frequency axis and modulated by a modulation method called multi-carrier modulation or group modulation. Things.

[0002]

2. Description of the Related Art FIG. 9 shows, for example, IEEE JOURNAL ON SELECT.
ED AREAS IN COMMUNICATIONS, VOL.SAC-5 page 652 Fi
9 is an example of a conventional receiver for a multicarrier modulation scheme shown in g.6, and shows a case of multicarrier modulation of four subchannels. Hereinafter, a case of multicarrier modulation of four sub-channels will be described. In the figure, 1 is RF
Section / IF section, 2 is a sub-channel separation circuit, 3a is a symbol timing estimation circuit, 4a is a sampling circuit, 5a
Denotes a sub-channel demodulation processing circuit.

Next, the operation of FIG. 9 will be described. The received signal is subjected to filtering, amplification and the like by the RF unit / IF unit 1 and the subchannel separation circuit 2 as a baseband signal 6 in which each subchannel is multiplexed on the frequency axis.
Is input to FIG. 5 shows the frequency spectrum of the signal 6 of four sub-channels. The sub-channel separation circuit 2 separates the components of each sub-channel of the baseband signal 6 and outputs four baseband signals 7 for each sub-channel.
Output as Subsequent processing is performed for each sub-channel. First, symbol timing estimation is performed by the circuit 3a using the baseband signal 7, and the signal 7 is sampled according to the detected timing signal 8a.
Sample at a. The sampled signal 9 is input to the sub-channel demodulation processing circuit 5a, where it is subjected to data demodulation processing and output as demodulated data 10. In this case, the estimation of the symbol timing is performed individually for each sub-channel. However, in general, in the multi-carrier modulation scheme, each sub-channel is modulated by the same modulator, so that the symbol timing of each sub-channel is synchronized. . Therefore, it is considered that performing common timing estimation using all the data of the four sub-channels is advantageous in terms of the circuit scale and the reduction of the symbol timing jitter because the circuits can be integrated into one. However, in practice, synchronization is established for each sub-channel as described above.

FIG. 10 shows an example of a conventional 4-subchannel multicarrier modulation type receiver shown in FIG. 4 of US9103784. In the figure, 1 is an RF unit / IF
2, 2 is a sub-channel separation circuit, 3b is a symbol timing estimation circuit, 4b is a sampling circuit, and 5a is a sub-channel demodulation processing circuit.

[0005] In the case of this figure, the symbol timing estimation is not performed individually for the four sub-channels, but is performed by the symbol timing estimation circuit 3b using the baseband signal 6 before the signal of each sub-channel is separated. Timing estimation is performed. In the data sampling, the sampling circuit 4b performs sampling at the same timing for the four sub-channels in accordance with the timing signal 8b output from the symbol timing estimation circuit 3b. Although this is advantageous from the viewpoint of the circuit scale, the symbol timing is generated before the sub-channel separation, so that the characteristics are degraded when the symbol timing position varies for each sub-channel. This variation often occurs in the modulator of the sub-channel signal or in the RF section / IF section of the receiver, and particularly the characteristics of the IF filter for channel separation are large. FIG. 6 is a diagram illustrating an example of the amplitude and delay characteristics of the IF filter. As shown in the figure, since the group delay characteristic differs depending on the sub-channel, the actual symbol timing position varies from τ1 to τ4 in the figure, and the amplitude and delay change for each channel. Normally, a filter having an inverse characteristic is used after the RF unit / IF unit 1 in order to cancel out the characteristic of the filter as shown in FIG. 6, but the circuit scale becomes large. In addition, since actual filter characteristics have variations, the variations cannot be compensated for by the inverse characteristics. Furthermore, since the combined signal of the four sub-channels is used, when the communication mode does not use the specific sub-channel or when the specific sub-channel fails, the waveform of the combined signal of the four sub-channels changes, and it is determined that there is no failure. The premise method breaks down, making it difficult to use.

[0006]

The conventional receiver is configured as described above. In the case of a method of independently synchronizing each sub-channel after separation, the operation of symbol timing estimation and sampling is performed by one sub-channel. Since processing is performed for each channel, there are problems such as an increase in circuit scale or processing amount, and an increase in symbol timing jitter. In the method of generating symbol timing before sub-channel separation, since the processing is not performed for each sub-channel, the circuit scale or the processing amount does not increase, but when the symbol timing position for each sub-channel varies. There have been problems such as deterioration of characteristics, difficulty in using a communication mode not using a specific sub-channel, or difficulty in using a specific sub-channel when it fails.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and aims to reduce the circuit size or processing amount of the symbol timing estimation function, reduce the timing jitter, and reduce the symbol timing position for each sub-channel. It is an object of the present invention to obtain a receiver which can correct the variation of the sub-channel and can cope with a case where a specific sub-channel is not used or a specific sub-channel fails.

[0008]

SUMMARY OF THE INVENTION A receiver for a multicarrier modulation system according to the present invention is a receiver for a multicarrier modulation system.
In the transceiver, each sub-channel that constitutes a multi-carrier
The symbol timing on the sub-channel is
Delay circuits for obtaining delay timings to be delayed, and the respective delay circuits
Each sub-channel signal after delay by
Symbol timing to estimate the symbol timing of the channel
And a symbol tie estimated for each channel.
From each sub-channel based on the
Delay control circuit that sets and controls the amount of delay for the delay circuit
Channel and a single synth after delay setting and control for each subchannel.
Synchronize each sub-channel with vol timing and sample
A sampling circuit for ringing.

Furthermore, level conversion is performed for each sub-channel.
To make the signal level of each subchannel the same.
Was. In addition, for a certain period of time,
Sub-channel signal that cannot be demodulated or cannot be demodulated.
Symbol timing estimating circuit for known sub-channel signal
Operation sub-channel control circuit to remove from the input
Was.

[0010]

In the receiver for the multi-carrier modulation system according to the present invention , the symbol timing position is estimated for each sub-channel.
And the amount of delay for each subchannel is controlled accordingly.
A single symbol timing is generated after each delay setting.
Then, all the sub-channels are sampled at the same timing .

Further, the level of each channel is corrected.
As a result, synchronization is detected at the same level, and the operation is stabilized. Also
In addition, signals on subchannels that are considered
Then, the timing detection operation is stabilized.

[0012]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a receiver for a multicarrier modulation system according to an embodiment of the present invention. In FIG. 1, reference numeral 3c denotes a symbol timing estimating circuit for obtaining the same timing of four sub-channels, 11 denotes a delay circuit for each sub-channel, and 12 denotes a level conversion circuit for each sub-channel. The same parts as those in FIG. 9 or 10 are denoted by the same reference numerals, and description thereof is omitted.

Next, the operation will be described. Delay circuit 11
Delays the baseband signal 7 output from the sub-channel separation circuit 2 by a fixed amount specific to each sub-channel, outputs the same as a signal 13, and matches the symbol timing of each sub-channel. The level conversion circuit 12 converts the level of the signal 13 to a constant value for each sub-channel so that the average level of each sub-channel of the output signal 14 is constant. For example, when the signal 7 complies with the amplitude characteristic and the group delay characteristic of FIG. 6, with respect to the subchannel 1, the subchannels 2 to 4 respectively have τ1-τ2, τ1-τ3,
Since τ1-τ4 is advanced, the delay amounts of the sub-channels 1 to 4 of the delay circuit 11 are set to 0, τ1-τ2, τ1-
Symbol timing can be matched by setting τ3 and τ1−τ4. Also, subchannels 1 and 4 are 2
Since the level is lower than the above, the level should be raised by the amount of the drop. The symbol timing estimating circuit 3c performs timing estimation using all the baseband signals 14 of the respective sub-channels whose symbol timings and average levels match, and outputs a timing signal 8b. The sampling circuit 4b follows the timing signal 8b.
Thus , sampling is performed at the same timing for the four sub-channels.

FIG. 4 shows a configuration example of the symbol timing estimation circuit 3c. In the figure, 15 is a squaring circuit, 16 is an addition circuit, and 17 is a BPF for extracting a symbol frequency component.
(Band pass filter), 18 is a symbol timing detection circuit, and 19 is an averaging circuit. Since the input baseband signal 14 of each sub-channel does not usually have a symbol frequency component, it is squared by the squaring circuit 15 to generate a symbol frequency component. The squared signals 20 from the respective sub-channels are added by the adding circuit 16. Here, signal 1 from each subchannel
By squaring 4 and adding all, it is possible to obtain a symbol frequency component that is sufficiently larger than when only one sub-channel is used, and to further reduce the timing jitter since variations are averaged. . The added signal 21 is a BP for extracting a symbol frequency component.
The signal other than the symbol frequency component is removed by F17, and is input as the symbol frequency component signal 22 to the symbol timing detection circuit 18 to determine the symbol timing. As a symbol timing detection method, a method using a zero cross level, a method using a maximum value of amplitude, and the like have been proposed. The detected symbol timing 23 is output as a timing signal 8b after the jitter is removed by the averaging circuit 19.

In the above embodiment, the level conversion circuit 12
Is shown after the delay circuit 11, but the same effect can be obtained when it is before the delay circuit 11. If the difference in amplitude characteristics between the sub-channels is small enough to cause no problem, the level conversion circuit 12 can be omitted.

Embodiment 2 FIG. FIG. 2 is a block diagram of a receiver for a multicarrier modulation system according to an embodiment of the present invention. In the figure, 24 is a delay control circuit, 25 is a level control circuit, 26 is an input control circuit, and 5b is a sub-channel demodulation processing circuit having means for detecting a frame synchronization position. In the present embodiment, the function of measuring the delay characteristics and the reception level of each sub-channel and setting the delay amount of the delay circuit 11 and the conversion amount of the level conversion circuit 12 is performed by the delay control circuit 24, the level control circuit 25, and the input control circuit 26. I have it. The setting operation is ideal when the product is shipped, when the receiver is used for the first time, or when the characteristics of the filter, etc. are changed. After setting the value, the setting operation is normally turned off.

Next, an example of the operation of the delay control circuit 24, that is, an example of the operation of setting the amount of delay of the delay circuit 11 and the operation of setting the amount of conversion of the level conversion circuit 12 is shown in the flowchart of FIG. First, the delay amount of the delay circuit 11 of each sub-channel is set to 0, and the conversion amount of the level conversion circuit 12 is set to 1. next,
The input control circuit 26 selects a signal of only one sub-channel and inputs it to the symbol timing estimating circuit 3c as a signal 27, finds the symbol timing position of each sub-channel, and sends it to the delay control circuit 24 as a timing signal 8b. input. The delay control circuit 24 detects the latest symbol timing among the sub-channel symbol timings, and sets the delay amount of the delay circuit 11 to 0 to set the delay amount setting signal 2
Set at 8. The delay amounts of the other sub-channels are set to be delayed by the difference from the slowest channel. By this operation, the symbol timing of each sub-channel matches. However, the symbol timing estimation circuit 3c
Since the symbol timing obtained in (1) is 0 or more and less than T when the symbol time length is T, if the difference in delay characteristics between the sub-channels is T or more, the corresponding correction cannot be made.
That is, a shift occurs in the frame synchronization position in the sub-channel demodulation processing circuit 5b. As a next step for compensating for this deviation, the sub-channel demodulation processing circuit 5b detects a frame synchronization position and inputs the frame synchronization position signal 29 to the delay control circuit 24. The delay control circuit 24
Among the delay amounts obtained by matching the symbol timing and the frame synchronization position obtained in step 2, the latest delay amount is detected, and the delay amount is set as in step 3. With this operation, the shift of the frame synchronization position is also corrected.

This will be described with reference to the timing chart of FIG. For example, in step 2, the symbol timings of subchannels 1 to 4 are τ1, τ2, τ3, τ4, respectively.
(0 ≦ τ1−τ4 <T). As shown in FIG. 8, for the frame synchronization position, the relationship between the frame timing generated by the receiver, the symbol timing, and each subchannel data is represented by 0, T, -T, 2T with respect to the frame timing generated by the receiver. In the case of, the sub-channel 4 has the largest delay amount. At this time,
The delay amounts of the sub-channels 1 to 4 are set as follows. Sub-channel 1: (2T + τ4) -τ1 Sub-channel 2: (2T + τ4)-(T + τ2) Sub-channel 3: (2T + τ4)-(-T + τ3) Sub-channel 4: 0

In setting the conversion amount of the level conversion circuit 12, first, the level control circuit 25 averages the signal 14 for a certain period of time to obtain the reception level of each sub-channel. Then, based on the result, the conversion amount (or gain) of the level conversion circuit 12 is adjusted so that the reception level of each sub-channel becomes the same.
Is set by the conversion amount setting signal 30. For example, the reception levels of 1 to 4 subchannels are 0.5, 1.0,
In the case of 2.0 and 0.4, the conversion amount is 2.0 times and 1.0
The times may be doubled, 0.5 times, and 2.5 times.

In the above embodiment, the level control circuit 2
Although 14 was used as the signal input to 5, the signal 7,
9 or 13, and the same effects as in the above embodiment can be obtained. In addition, the delay amount is controlled so that both the symbol timing and the frame synchronization timing between the sub-channels match. However, if only the symbol timings need to match, or the transmission data does not have a frame configuration. In this case, the delay control circuit 24 uses only the timing signal 8b and does not require the operations of steps 4 to 6 in the flowchart.
No 9 is needed. When the difference in the amplitude characteristics between the sub-channels does not matter, the level conversion circuit 12 and the level control circuit 25 can be omitted. Further, a part 31 indicated by a dotted line is manufactured as a jig, and signals 8b, 27, 2
An output terminal such as 8, 29, or 30 may be provided.

Embodiment 3 FIG. FIG. 3 is a block diagram of a receiver for a multicarrier modulation system according to an embodiment of the present invention. In the figure, reference numeral 32 denotes an operation sub-channel control circuit. When the operation sub-channel control circuit 32 detects a signal that is lower than the predetermined level for a certain period or more among the reception levels 33 of the respective sub-channels measured by the level control circuit 25, the sub-channel is not used or abnormal. Is assumed to be. Then, the control signal 34 is input to the input control circuit 26, and the signal 14 of the corresponding sub-channel is cut so that only the signal of the effective channel is input to the symbol timing estimation circuit 3c so that no adverse effect is caused. Further, the corresponding sub-channel demodulation processing circuit 5b is also turned off by the control signal 35. When a signal higher than a predetermined level is detected for a certain period or more, various functions of the corresponding sub-channel are turned on again.

In the above embodiment, the condition that the reception level 33 is lower than the predetermined level for a certain period or more is used as a determination condition of the operation sub-channel control circuit 32. However, demodulation in each sub-channel demodulation processing circuit is performed for a certain period. The above-mentioned impossibility may be used as the determination condition. The same effect can be obtained by using the above two determination conditions in combination.

[0023]

According to the present invention, as described above,
Each sub-channel signal after channel separation is
A predetermined delay so that the
Sampled at the same symbol timing
Circuit size or processing amount can be reduced,
This has the effect of reducing the number of light sources.

Further, level conversion is performed for each sub-channel.
The level of each sub-channel is corrected
There is an effect that the synchronization detection becomes stable.

Further, an operation sub-channel control circuit is provided.
Digit, the reception level of a subchannel is very low.
Stable operation even when the
There is an effect that you can trust.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multicarrier modulation system receiver according to an embodiment of the present invention.

FIG. 2 is a block diagram of a receiver for a multicarrier modulation system according to another embodiment of the present invention.

FIG. 3 is a block diagram of a receiver for a multicarrier modulation system according to still another embodiment of the present invention.

FIG. 4 is a configuration diagram of an embodiment of a symbol timing estimation circuit according to the present invention.

FIG. 5 is a diagram illustrating a frequency spectrum of a multi-carrier modulated wave of four sub-channels.

FIG. 6 is a diagram illustrating an example of amplitude and delay characteristics of an intermediate frequency filter.

FIG. 7 is a flowchart illustrating an example of a delay amount by a delay control circuit and a conversion amount setting operation by a level control circuit;

FIG. 8 is a diagram illustrating an example of a frame synchronization position of each subchannel.

FIG. 9 is a block diagram of a conventional receiver for a multicarrier modulation scheme.

FIG. 10 is a block diagram of another conventional receiver for a multicarrier modulation scheme.

[Explanation of symbols]

 Reference Signs List 1 RF unit / IF unit 2 Sub-channel separation circuit 3c Symbol timing estimation circuit 4b Sampling circuit 5a, 5b Sub-channel demodulation processing circuit 11 Delay circuit 12 Level conversion circuit 24 Delay control circuit 25 Level control circuit 26 Input control circuit 32 Operation sub-channel Control circuit

Claims (3)

(57) [Claims] 1. A multi-carrier modulation receiver
Thus, for each sub-channel constituting the multi-carrier,
Delay to match symbol timing on subchannels
A delay circuit for obtaining timing and each sub-channel signal delayed by each of the delay circuits are input.
And estimate the symbol timing of each channel
Symbol timing estimating circuit and symbol timing position estimated for each of the above channels
From each frame and the frame synchronization position
A delay control circuit for setting and controlling the amount of delay for the circuit, a delay setting for each sub-channel, and a single symbol after control
Synchronize each of the above sub-channels at the
And a sampling circuit for pulling.
And a receiver for a multi-carrier modulation system. 2. A level converter is provided for each sub-channel.
The signal level of each sub-channel
The receiver for a multicarrier modulation system according to claim 1, wherein: 3. The method according to claim 1, wherein the predetermined period is equal to or less than a predetermined level.
Sub-channel signal that cannot be demodulated or cannot be demodulated.
Symbol timing estimating circuit for known sub-channel signal
Operation sub-channel control circuit to remove from input for
The receiver according to claim 1, characterized in that: