JP3107676B2 - Quantization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantization circuit used in a device for compressing image data.

[0002]

2. Description of the Related Art Methods for compressing color and monochrome still images and moving images have been studied by international organizations such as ISO and CCITT, and JPEG [Joint Photogr] has been studied.
aphic Experts Group] and MPEG
[Moving Picture Experts G
group] and H. Rup. 261 are standardized.

[0003] JPEG uses a color still image of 1/8 to 1
This is a method of compressing to about / 100. It became an international standard in November 1991. FIG. 7 is a block diagram showing an encoding method. The input image 71 is input to the encoder 72. In the encoder 72, the input image 71 input is input to the DCT unit 721, and the DCT (discrete cosine transform) is performed.
Is performed. Next, in the quantization unit 722, the table 7
The output of the DCT unit is quantized with reference to 23, and the output of the quantization unit 722 is further entropy-coded with reference to the table 725 in the entropy coding unit 724. As a result, the compressed data 73 having the table and the header information is transferred to the transmission path 74.

[0004] MPEG is a system for compressing color moving images. Digital recording media such as CD-ROM (DS
M: Digital Storage Media). In November 1991, a draft recommendation (CD: Co
(mittee Draft). FIG. 8 is a block diagram showing an encoding method. An encoding circuit based on this method includes a predictor 88 for generating predicted image data having a small difference value from input image data, and a subtractor 8 for subtracting predicted image data output from the predictor 88 from the input image data.
9 for performing a DCT operation on the difference output of the subtractor 89
A CT unit 81, a quantization unit 82 for performing quantization on the DCT coefficient output (C) of the DCT unit 81, and a VL for performing variable length coding on the quantization coefficient output (QC) of the quantization unit 82
A C unit 83, a buffer unit 84, an inverse quantization unit 85 that performs inverse quantization on the quantized coefficient output of the quantization unit 82, and an inverse DCT unit 86 that performs inverse DCT on the output of the inverse quantization unit 85
And an adder 87 that adds the output of the inverse DCT unit 86 and the predicted image data output from the predictor 88 to generate new predicted image data.

[0005] H. H.261 is a video conference / telephone coding system, which is described in CCITT Recommendation H.264. 261.
In 1991 it became the International Standard (IS). ISDN is assumed as a network, and a moving image is transmitted at 64 k to 1.5 Mbit / sec. FIG. 9 is a block diagram showing an encoding method.

The encoding circuit according to this method includes a DCT transformer 92, a quantizer 93 for quantizing the output of the DCT transformer and outputting a quantization index (q) of a transform coefficient, and an output of the quantizer 93. Inverse quantizer 94 that inversely quantizes the output signal and an inverse DCT unit 95 that performs an inverse DCT transform on the output of the inverse quantizer 94
An adder 96 for adding the outputs of the switch 99 and the inverse DCT unit 95; an image memory 97 having a variable delay function for motion compensation for receiving the output of the adder 96 and outputting a motion vector; Upon receiving the output, the motion compensation inter-frame prediction accuracy is raised, and an on / off signal of the in-loop filter is outputted, a negative input 100 of the output of the in-loop filter 98 is fed back to the video input, a switch 101 and the quantum The coding control unit 91 controls the quantizer 93 and outputs an inter-frame / intra-frame identification flag (p), a transmission / non-transmission identification flag (t), and a quantizer type (qz).

The above three image compression methods commonly employ a method as shown in FIG. That is, DCT [Discrete Co
sine Transform] 611 to convert to a DCT coefficient 622, and then perform quantization 612 on the DCT coefficient 622 to obtain a quantization coefficient 623.

[0008] The quantization process is individually defined for each image compression method, but each of the processes includes the following three steps.

(1) The DCT coefficient is divided by a quantization threshold. (Division processing) (2) Round the division result to an integer excluding the decimal part. (Rounding process) (3) The rounded result is limited to a value not exceeding a predetermined range. (Range Restriction Processing) However, the rounding processing in (2) may be “truncated” or “rounded off” for each image compression method.

For example, JPEG and H.-K. The quantization at 261 is as follows. Here, R is a DCT coefficient, L is a quantization coefficient, and Q is a quantization threshold.

1) JPEG (8-bit mode) (-1)
024 ≦ L ≦ 1023) L = R / Q The rounding method is rounded off as shown in FIG. FIG. 2 shows that, for example, a number greater than or equal to 0.5 and less than 1.5 is rounded to one.

2) H. 261 (−127 ≦ L ≦ 127) L = R / 2Q (Q: odd number) = (R + 1) / 2Q (Q: even number, R ≧ 0) = (R−1) / 2Q (Q: even number, R <0) The rounding method is truncation as shown in FIG. FIG. 3 shows that, for example, a number greater than or equal to one and less than two is rounded as one.

[0013] Methods for realizing quantization are roughly classified into two methods: a method using software and a method using hardware.

As shown in FIG. 4, the method implemented by software divides the DCT coefficient by a quantization threshold in step S41, and outputs the DCT coefficient in steps S42, S43, and S44 in accordance with each of the positive and negative signs. After rounding the result to an integer value according to the method specified in the image compression standard, a range limiting process is performed in step S45.

[0015] The method performed by hardware is the division processing (1) of the quantization processing, (a) a method using a divider, and
(B) A method is known in which the reciprocal of the quantization threshold is calculated in advance, and the DCT coefficient is multiplied by the reciprocal using a multiplier.

As for the rounding method (2) of the quantization processing, a dedicated circuit for "cutting off" and "rounding off" and a range limiting circuit are added in correspondence with the image compression method. FIG. 5 is a hardware block diagram of the quantization processing.
Shown in The quantization circuit calculates the coefficient to be quantized R and the quantization threshold Q
, A sign determination circuit 502 receiving an output of the division circuit 501 as an input, and a sign determination circuit 50
Decimal part truncation circuit 50 for positive number inputting the output of 2
3, a fractional part truncation circuit 504 for negative numbers, a fractional part truncation circuit 503 for positive numbers, and a range limiting circuit 505 to which an output of the fractional part truncation circuit 504 for negative numbers is input.

The division circuit 501 divides the quantized coefficient R by the quantization threshold Q. The sign determination circuit 502 determines the sign of the division result. If the sign is positive, the decimal part truncation circuit 503 for positive numbers performs a truncation process. If the sign is negative, the negative decimal part truncation circuit 504 performs a truncation process. The range limiting circuit 505 limits the range of the quantization coefficient to a predetermined value.

[0018]

The conventional software-based realization method needs to determine whether the DCT coefficient is positive or negative, and requires a multi-step instruction, which causes a problem that the speed is reduced.

In the conventional hardware implementation method, the circuit scale becomes large and the execution speed is slow because of the rounding process of (2) among the three steps for quantization. There was a problem.

An object of the present invention is to provide a quantization circuit having a high execution speed and a reduced circuit scale.

[0021]

According to the present invention, there is provided a quantization circuit comprising:
Holding means for holding the rounding constant for positive number input, holding means for holding the rounding constant for negative number input, and rounding constant selection for selecting one of the rounding constant for positive number input and the rounding constant for negative number input according to the positive / negative judgment of the input Means for inputting and multiplying a reciprocal of a DCT coefficient and a quantization threshold; input means for receiving the output of the rounding constant selecting means and the output of the multiplying means as inputs and adding them; A shift means for inputting an output and performing a shift process on the input value, and a range limiting means for limiting the value range by receiving the output of the shift means as an input.

[0022]

The rounding constant when the DCT coefficient is a positive number is stored in the rounding constant holding means for positive number input, and the rounding constant when the DCT coefficient is a negative number is stored in the rounding constant holding means for negative number input. The rounding constant selecting means selects a rounding constant for a positive number or a negative number according to the sign bit of the DCT coefficient, and inputs it to one of the input terminals of the adding means. On the other hand, the product of the DCT coefficient and the reciprocal of the quantization threshold is obtained by the multiplication means,
The obtained result is input to the other of the input terminals of the adding means. The output of the adding means is shifted by the shifter means and limited within the range of the quantized coefficients by the range limiting means.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

Assuming that the DCT coefficient is R, the quantization threshold is Q, and the rounding function is F (x), the quantization coefficient L before performing the range limitation is expressed as follows.

L = F (R / Q) (Equation 1) Here, A / S is selected such that (1 / Q) = (A / 2 ^S ) (Equation 2) L = F (AR / 2 ^S ) (Equation 3) = F (AR >> S) (Equation 4) (where >> S indicates that S bits are to be shifted right by S bits in two's complement representation. Here, if X is used as a rounding constant in order to round the value of L after multiplication to an integer, by changing the value of the rounding constant X, the DCT is calculated as follows.
The rounding method of the decimal part resulting from dividing the coefficient R by the quantization threshold Q can be freely selected.

L = (AR + X) >> S (Equation 5) When R ≧ 0, X = 0: Truncation = A / 2: Rounding R <0 X = 2 ^S −1: Truncation = A / 2-1: rounded off.

FIG. 1 is a block diagram showing one configuration example of the quantization circuit of the present invention.

The quantizing circuit shown in FIG. 1 includes a rounding constant register 101 for positive number input and a rounding constant register 10 for negative number input.
2. A selection circuit 103 connected to the rounding constant registers 101 and 102, a multiplier 104 which receives a DCT coefficient R and a reciprocal A of a quantization threshold as inputs, a selection circuit 103 and a multiplier 104
, A shifter 106 connected to the adder 105, and a range limiting circuit 107 connected to the shifter 106.

When the DCT coefficient R in (Equation 5) is a positive number, the rounding constant X is set to the rounding constant register 10 for inputting a positive number.
1, the rounding constant X when the DCT coefficient R is a negative number is stored in the rounding constant register 102 for negative number input.

The selection circuit 103 selects a positive or negative rounding constant based on the sign bit of the DCT coefficient R, and inputs it to the adder 105.

On the other hand, the DCT coefficient R
And the reciprocal A of the quantization threshold are obtained. Adder 105
Then, (AR + X) is obtained, shifted by S bits to the right by the shifter 106, and the value range of the quantization coefficient is limited to a predetermined value by the value range limiting circuit 107.

Thus, the calculation of (Equation 5) is realized and D
The CT coefficient R is quantized by the quantization threshold Q, and a result L rounded to an integer is obtained.

The quantization circuit of this embodiment has two conventional rounding constant registers, which is a conventional problem.
Faster execution speed in software-based implementation method, one-hardware implementation for various rounding schemes for fractional parts in hardware-based implementation method, and reduced circuit scale compared to conventional methods Becomes

[0034]

The quantizing circuit according to the present invention comprises a rounding constant holding means for positive number input, a rounding constant holding means for negative number input,
Since it has a rounding constant for positive number input and a rounding constant selecting means for selecting one of the rounding constants for negative number input according to the positive / negative determination of the input, a multiplying means, an adding means, a shifting means and a range limiting means, The execution speed is fast,
A quantization circuit with a reduced circuit size can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a quantization circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a rounding method by rounding off.

FIG. 3 is an explanatory diagram of a rounding method by truncation.

FIG. 4 shows a conventional technique using software.

FIG. 5 shows a conventional technique using hardware (when the rounding method is truncation).

FIG. 6 is a configuration diagram of an image compression method.

FIG. 7 is a block diagram of a JPEG encoding circuit.

FIG. 8 is a block diagram of an MPEG encoding circuit.

FIG. FIG. 3 is a block diagram of a H.261 coding circuit.

[Explanation of symbols]

 101 Rounding constant register for positive number input 102 Rounding constant register for negative number input 103 Selection circuit 104 Multiplier 105 Adder 106 Shifter 107 Range limiting circuit 611 DCT execution means 612 Quantization execution means 621 Image data 622 DCT coefficient 623 Quantization coefficient

Continuation of front page (56) References JP-A-5-48464 (JP, A) JP-A-2-227770 (JP, A) JP-A-64-10326 (JP, A) JP-A-61-278213 (JP) , A) JP-A-58-225436 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/30

Claims (1)

(57) [Claims] 1. A holding means for holding a rounding constant for positive number input, a holding means for holding a rounding constant for negative number input, and one of a rounding constant for positive number input and a rounding constant for negative number input in accordance with the positive / negative judgment of the input. Means for selecting a rounding constant to be selected;
Multiplication means for inputting and multiplying a DCT coefficient and a reciprocal of a quantization threshold; input means for receiving the output of the rounding constant selection means and the output of the multiplication means as inputs and adding the output of the addition means; A quantizing circuit comprising: a shift means for performing a shift process on the input value; and a range limiting means for limiting a value range by using an output of the shift means as an input.