JP3103014B2 - Receiving machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver provided with an automatic frequency control (AFC) used for digital data transmission such as automobile telephones, and more particularly to a correction using a frequency offset. Reception with an AFC function with improved performance such as fast convergence of values, compensation of a wide range of frequency offsets, realization of high-accuracy characteristics even at low C / N, and use of maximum ratio combining diversity reception It is about the machine.

[0002]

2. Description of the Related Art The technical background of the present invention will be described. First, the carrier phase synchronization circuit will be described.
The reception signal for the transmission signal In is rn, and the transmission path characteristic is c.
Assuming that n is additive white Gaussian noise (hereinafter, referred to as AWGN) as wn, the received signal rn can be expressed as in equation (1).

Rn = cn · In + wn (1) Here, the suffix n represents time. For the sake of simplicity, it is assumed that the information to be transmitted is two-phase PSK.

The carrier phase synchronization circuit shown in FIG. 20 doubles the received signal rn to obtain the next signal.

Rn ² = c n ² · In ² + 2cn · In · w n + w n ² (2) where In = exp (jΘn) (Θn = 0, π), cn =
Let Cn exp (jγn) (where Cn is a positive number),
Equation (3) holds.

Cn ² · I n ² = C n ² exp {2j (Θn + γ n)} = C n ² exp (2jγ n) (3) In the above expression, exp (2jΘn) = 1 is used. did.

Next, by taking the average of r n ² , r
The average of n ² are asymptotic to C n ² exp (2jγn). Now, assuming that the average carrier phase angle of c n ² · I n ² is β, the carrier phase γ n is either β / 2 or β / 2 + π. This phenomenon is called phase uncertainty. Usually, β / 2 or β / 2 + π to remove this phase uncertainty
Is often estimated using a known transmission sequence or the like in advance.

Next, the frequency offset will be described. The received IF (intermediate frequency) signal is converted into a carrier frequency component (the carrier angular frequency is ωc
) Is removed to become a received signal. At this time, the carrier frequency component remaining in the received signal is a frequency offset. The frequency converter removes a carrier frequency component from the received IF signal based on an oscillator in the receiver and outputs a received signal.

Here, the IF signal Rn is represented by rn exp (jωc
nT), and the conversion angular frequency of the frequency converter is ωo,
The output of the frequency converter is Rn exp (-jωo nT) = rn exp (j (ωc-ωo) nT) (4) If ωc ≠ ωo, exp (j (ωc−ωo) n
Due to the twiddle factor T), the reference phase of the received signal rotates with time, and the bit error rate characteristics deteriorate. This Δω = (ωc−ωo) T is a normalized angular frequency offset (hereinafter simply referred to as “frequency offset”).
).

Generally, the phase is defined as a scalar quantity θ. In an actual signal processing, this phase is defined as cos θ.
In some cases, it is more convenient to display a complex number as + j sin θ (= exp (jθ)), that is, to display θ as the phase axis of polar coordinates. Therefore, in the following description, the phase is represented by the scalar quantity θ.
In the case where the complex number is expressed simply as phase exp (jθ), it is referred to as “complex value of the phase expressed in polar coordinates”. The operation of obtaining the scalar amount θ from exp (jθ) will be referred to as “inverse tangent”.

Next, a brief description will be given of a phase jump when performing an arc tangent. In the detection of the phase near π, if the phase to be detected is π + τ (τ ≧ 0), the detection range of the phase is [−π, π), and the detection result is −π + τ, which is called “phase jump”. Call.

For example, if the values to be detected are distributed with a variance σ around π, the average value of the detection values should be π, but the average value of the detection result becomes 0 due to a phase jump. Thus, when averaging a phase near π or a phase with a large variance, averaging cannot be performed correctly due to a phase jump.

Next, the estimation of transmission path characteristics will be described. The estimation of the transmission path characteristics is an operation for estimating the actual transmission path characteristics cn. First, a method of estimating transmission path characteristics from a known sequence called a training sequence will be described.
Assuming that cn is a temporally constant value c, when there is a sufficiently random training sequence of length K, the estimated value g of the transmission path characteristic c can be calculated as equation (5).

[0014]

(Equation 1) Here, * indicates a complex number conjugate.

When the tap coefficient cn changes with time, an adaptive algorithm such as an LMS (Least Mean Square) algorithm or an RLS (Recursive Least Squares) algorithm is effective.

Hereinafter, the LMS algorithm will be described. An LMS algorithm is one of the algorithms for sequentially obtaining an approximate solution of the Wiener solution. This is to adjust the tap coefficient so that the square error value of the received signal and its replica is minimized. The LMS algorithm when the number of taps is 1 can be expressed as follows.

Gn + 1 = gn + δ · en · In ^* (6) en = rn−gn · In (7) where, in particular, δ is called a step size and In is called a reference input. .

Next, the soft decision will be briefly described. One type of encoding is convolutional coding, and a Viterbi algorithm is used for an optimal decoding method of the convolutional code. The input of this Viterbi algorithm includes not only binary quantized (“hard decision”) data such as “0” or “1” but also reliability such as “0.1” or “0. 9 "and the like (referred to as" soft decision ") show better error rate characteristics. Therefore, to decode the convolutional code,
The error rate characteristics can be improved when soft decision data is used.

Next, fading will be briefly described. The term "fading" refers to a phenomenon in which a radio wave is reflected, diffracted, scattered, or the like due to surrounding terrain, a building, or the like, and the envelope or phase of the received wave fluctuates randomly. In particular, in land mobile communication, fading called “Rayleigh fading” occurs. The phase of this fading is uniformly distributed, and the envelope is a Rayleigh distribution.
The envelope power is 20 [dB] or 30 [dB] from the average power.
May be smaller. This phenomenon is called “fade”, and the bit error rate characteristic may be significantly deteriorated during the fade.

Next, the diversity receiver will be described. The “diversity receiver” prepares a plurality of antennas (here, N antennas) and determines data by combining N-system received signals. For example, FIG.
The configuration example shown in FIG. 1 includes N antennas and obtains N systems of received signals.

In the diversity receiver, N antennas are set so that the noise component and the envelope component of the N systems of received signals are as uncorrelated as possible. In other words, in a situation where the above-described fading has occurred, if the fluctuations in the envelope power of the N antennas are set to be independent, the probability of the N antennas simultaneously fading can be significantly reduced. This is the effect of diversity under fading.

Here, a type of diversity called "combination diversity after detection" will be described. In the diversity receiver shown in FIG. 21, it is assumed that N = 2 and the received signals received from two systems of antennas 1 and 2 are r (1) n and r (2) n, respectively. Also, the rms values (square root of the envelope power) of the signal components of the two systems of received signals are a (1) n and a (2) n, and the carrier phases are γ (1) n and γ (2) n. For a certain case, the equal gain combining method and the maximum ratio combining method will be described.

In the equal gain combining method, a combined signal is created as equation (8) regardless of the envelope power, and in the maximum ratio combining method, the combined signal is weighted by the envelope power as equation (9) and output.

R (1) n exp (−jγ (1) n) + r (2) n exp (−jγ (2) n) (8) a (1) n · r (1) n exp (−jγ (1) n) + a (2) n · r (2) n exp (−jγ (2) n) (9) That is, in the maximum ratio combining method, when the reception level of one of the antennas is small, the weight for this is given. And the effect of noise can be suppressed.

Next, an example (conventional example 1) of a conventional receiver having an AFC function will be described. FIG. 22 is a configuration diagram of a receiver having an AFC function of Conventional Example 1. This conventional example is described in Yukihiro Shimakata and Hideo Osawa, "Configuration and Characteristics of PSK Baseband Differential Detection Demodulator", 1991 IEICE Spring Conference, Lecture No. B-360. A announced at
This realizes a receiver having an FC function.

In FIG. 22, reference numeral 220 denotes a reception signal input terminal, 221 denotes a reception tangent circuit for receiving a reception signal from the reception signal input terminal 220 and calculating an arc tangent value of the reception signal;
Reference numeral 22 denotes a delay circuit for delaying the arctangent value output from the arctangent circuit 221 by one symbol, and 223 denotes a delay circuit 22.
Arc tangent circuit 221 by the amount of delay data output from
224 for subtracting from the arctangent value output from
Is the subtraction value output from the subtraction circuit 223 and the averaging circuit 2
Addition circuit 225 for adding the average value output from 27
Is a determination circuit that outputs a determination value of transmission data based on the addition value output by the addition circuit 224, and 226 is a determination circuit 22
5 is a subtraction circuit that subtracts the judgment value output from the addition circuit 224 by the addition value output from the addition circuit 224, 227 is an averaging circuit that averages the subtraction value output from the subtraction circuit 226, and 228 is the judgment value output. Terminal.

Next, the operation of the conventional example will be described.
It is assumed that the transmission signal is 4-phase PSK. First, the delay circuit 222 receives the arc tangent value of the received signal output from the arc tangent circuit 221, delays it by one symbol, and outputs it. The subtraction circuit 223 subtracts the arc tangent value output from the arc tangent circuit 221 by the delay data output from the delay circuit 222, and outputs the subtraction result to the addition circuit 224.

Here, when the frequency offset is Δω and the received signal rn is represented by ignoring noise as in equation (10), the output of the subtraction circuit 223 is as in equation (11).

Rn = cn exp (j (Θn + Δωn)) (10) (Θn + Δωn)-(Θn-1 + Δω (n-1)) = (Θn-Θn-1) + Δω (11) cn is a constant value c, Θn is a phase component of the transmission signal, and Θn = πi / 2 + π / 4, (i = 0, 1, 2, 2,
3).

Next, the addition circuit 224 is provided with a subtraction circuit 223.
Is added to the frequency offset correction value φn output by the averaging circuit 227 to the subtraction value output by the equation (12) to obtain the equation (12).

(Θn−Θn−1) + Δω + φn (12) The judgment circuit 225 outputs the signal from the addition circuit 224 (1
2) When the expression is in the range of [0, π / 2), the difference Θn−Θn−1 between the transmission signal at time n and the transmission signal at time n−1 is calculated by π
/ 4, and when the expression (12) is in the range of [π / 2, π], the difference 送信 n−Θn−1 of the transmission signal is determined to be 3π / 4, and the expression (12) is [π, 3π / 4), the difference 送信 n−Θn−1 of the transmission signals is determined to be 5π / 4,
When the expression (12) is in the range of [3π / 2, 2π),
The difference Θn−Θn−1 between the transmission signals is determined to be 7π / 4, and this determination value is output from the determination value output terminal 228.

The subtraction circuit 226 subtracts the expression (12) output from the addition circuit 224 from the judgment value output from the judgment circuit 225 to obtain the expression (13). However, it is assumed that there is no determination error in the determination circuit 225.

Εn = −Δω−φn
(13) For example, when .epsilon.n> 0, the averaging circuit 227 gradually increases the value of .phi.n and operates so that .epsilon.n approaches zero.
Conversely, when εn <0, the value of φn is gradually reduced,
It operates so that εn approaches zero.

However, the absolute value of the frequency offset is π /
When the number exceeds 4, a determination error occurs in the above-described determination circuit 225. That is, the compensation range of the frequency offset in the conventional example is limited to π / 4 or less. If a determination error occurs, an estimation error of π / 2 or more occurs at the input of the averaging circuit 227. Therefore, in the conventional example, since the influence of the determination error is large, it is difficult to realize high-accuracy characteristics at a low C / N where the determination error is relatively likely to occur.

In order to sufficiently suppress the fluctuation of the compensation value of the frequency offset due to noise, it is necessary to increase the time constant of the averaging circuit 227. If this time constant is increased, the convergence of the correction value becomes slow. Further, since the configuration of the conventional example does not use diversity reception for improving the error rate of the receiver, the characteristics are deteriorated as compared with the receiver using diversity reception.

Next, another example (conventional example 2) of the receiver having the conventional AFC function will be described. FIG. 23 is a configuration diagram of a receiver having an AFC function of Conventional Example 2. This conventional example shows a receiver having an AFC function similar to the "frequency offset compensation method" disclosed by Hiroyasu Ishikawa (JP-A-5-344172).

In FIG. 23, reference numeral 231 denotes a reception signal input terminal, 232 denotes a delay circuit for delaying the reception signal from the reception signal input terminal 231 by one symbol (T _S ), and 233 denotes a delay with the reception signal from the reception signal input terminal 231. A multiplication circuit A 234 for calculating a multiplication value with the delay signal output from the circuit 232 is a low-pass filter, and 235 is a low-pass filter 23.
4 is an L multiplying circuit, 236 is an averaging circuit, 237 is an L frequency dividing circuit, and 238 is an L frequency dividing circuit 237.
A complex conjugate circuit 239 outputs a complex conjugate of the output of the multiplication circuit 239, a multiplication circuit B for calculating a multiplication value of the output from the low-pass filter 234 and the complex conjugate circuit 238, a determination circuit 2310,
Reference numeral 311 denotes a judgment value output terminal.

Next, the operation of the conventional example will be described.
It is assumed that the transmission signal is 4-phase PSK (L = 4). First, the multiplication circuit A 233 outputs a multiplication value of the reception signal from the reception signal input terminal 231 and a delay signal obtained by delaying the reception signal by one symbol by the delay circuit 232, and the low-pass filter 234 outputs the multiplication value. The harmonic component of the result is removed, and the delay detection result is output.

Here, when the frequency offset is Δω and the received signal rn is represented by ignoring noise as in equation (14), the output of the low-pass filter 234 is as in equation (15).

Rn = cn exp (j (Θn + Δωn)) (14) C ² exp (j (Θn−Θn-1 + Δω)) (15) where cn is a constant value C (hereinafter, C = 1), Θ
n is the phase component of the transmission signal, and Θn = πi / 2 + π /
4, (i = 0, 1, 2, 3).

The L multiplying circuit 236 includes a low-pass filter 234
Is multiplied by 4 to obtain the equation (16).

Exp (j4 (Θn-Θn-1 + Δω)) = exp (j (4 (Θn-Θn-1) + 4Δω)) = exp (j4Δω) (16) where 4 ( Θn-Θn-1) = 2πi,
(I is an integer).

The phase of the equation (16) has a frequency offset of 4
The value is multiplied. The averaging circuit 236 is an L multiplication circuit 23
5 are summed over N symbols and averaged, and L
The frequency dividing circuit 237 divides this average value by four and outputs it as an estimated value of the frequency offset expressed as a complex number exp (jΔω ′). The complex conjugate circuit 238 calculates the complex conjugate of the frequency offset represented by the complex number, and outputs it as a correction value of the frequency offset represented by the complex number.

Next, the multiplying circuit B 239 calculates the delay detection result output from the low-pass filter 234 and the complex conjugate circuit 2
The multiplication by the complex-valued frequency offset correction value exp (−jΔω ′) output by 38 is performed to remove the frequency offset component included in the delay detection result. As a result, the output of the multiplying circuit B239 becomes the equation (17), and when the frequency offset is accurately estimated (Δω ′ = Δω), (1)
Equation (7) becomes equation (18).

Exp (j (Θn−Θn−1 + Δω−Δω ′)) (17) exp (j (Θn−Θn-1)) (18) The judgment circuit 2310 is output from the multiplication circuit B239. The multiplication value is hard-decided, and the result is output to a decision value output terminal 2311
Output more. Furthermore, in this conventional example, since the frequency offset estimation range is not narrowed by multiplying by L,
A method has been proposed in which a transmission signal is differentially encoded twice and differential decoding is performed before a determination circuit in a receiver.

As described above, in the conventional example, the modulation component of the received signal is removed by the multiplication process.
Since the multiplication process deteriorates C / N equivalently, a low C / N
It is difficult to realize highly accurate characteristics with N. Also,
Since the delay detection is used as the demodulation method, the error rate is lower than that of the synchronous detection. Further, since the configuration of the conventional example does not use diversity reception for improving the error rate of the receiver, the characteristics are deteriorated as compared with the receiver using diversity reception.

Next, an example of a conventional diversity receiver (conventional example 3) will be described. FIG. 24 is a configuration diagram of a receiver having diversity of the third conventional example. This conventional example shows a diversity receiver similar to the "diversity wireless receiver" (JP-A-6-90225) disclosed by Hideaki Omori et al.

In FIG. 24, 241-1 and 241-
2 is a reception wave input terminal, 242-1 and 242-2 are oscillation circuits A1 and A2, 243-1 and 243-2 are reception waves from the reception wave input terminals 241-1 and 241-2 and an oscillation circuit A1 (242 -1) and multiplication circuits A1 and A2 for calculating multiplication values with outputs from A2 (242-2), respectively.
2, 244-1 and 244-2 are bandpass filters A1 and A2, 245 is an addition circuit, 246 is bandpass filter B, 2
47 is a delay circuit for delaying the output from the bandpass filter B 246 by M symbols (MT _S ), 248 is a multiplication circuit B,
249 is a bandpass filter C having a bandwidth equal to or greater than the Nyquist frequency, and 2410 is a synthesized signal output terminal.

Next, the operation of the conventional example will be described.
First, the multiplication circuits A1 (243-1) and A2 (243-
1) are reception wave input terminals 241-1 and 241, respectively.
-2 and a sine wave output from the oscillation circuits A1 (242-1) and A2 (242-2) are output, and the bandpass filters A1 (244-1) and A2 (2
44-2) removes unnecessary wave components such as harmonics from the multiplied value and outputs an IF (intermediate frequency) reception signal.

However, if the nominal IF frequency is fi,
It is necessary to set the oscillation frequency of the oscillation circuits A1 (242-1) and A2 (242-2) so that each IF signal becomes the expression (19) and the expression (20).

[0051] R1 cos ((ωi + 2πm / MT S) t + Θ (t) + θ1) ... (19) R2 cos ((ωi + 2πn / MT S) t + Θ (t) + θ2) ... (20) | m-n |> M / 2 (21) where m and n are integers satisfying the expression (21), and R1
, R2 is the amplitude of the IF reception signal in each branch, θ1
, Θ2 is the phase of the IF reception signal in each branch, Θ
(t) is a modulation component.

The addition circuit 245 includes a bandpass filter A1 (2
44-1) and the output of A2 (244-2) (1
The addition value of the expressions 9) and (20) is output, and the bandpass filter B
H.245 limits the band of the added value and outputs equation (22).

[0053] R1 cos ((ωi + 2πm / MT S) t + Θ (t) + θ1) + R2 cos ((ωi + 2πn / MT S) t + Θ (t) + θ2) ... (22) multiplication circuit B248 is, the output of the band-pass filter B245 ,
A multiplied value of the output and a signal delayed by M symbols by the delay circuit 247 is output, and a bandpass filter C249 is output.
Removes the harmonic component of the multiplied value and outputs equation (23), which is an M-symbol differential detection output.

[0054] ^{R 1 2 / 2cos (Θ (} t) -Θ (t-MT S) + ωi MT S + 2πm) + R 2 2 / 2cos (Θ (t) -Θ (t-MT S) + ωi MT S + 2πn) + R ^{1 2 R 2 2 / 2cos (} (m-n) / MT S) · t + ωi MT S + 2πn + Θ (t) -Θ (t-MT S) + θ1 -θ2) + R 1 2 R 2 2 / 2cos ((n- _{m) / MT S · t +} ωi MT S + 2πm-Θ (t) + Θ (t-MT S) -θ1 + θ2) ... (23) However, the third and fourth terms in equation (23), band-pass filter C249 Can be cut off by setting the band of the Nyquist bandwidth, in this case, the bandpass filter C24
The output of No. 9 is given by equation (24).

[0055] ^{R 1 2 / 2cos (Θ (} t) -Θ (t-MT S) + ωi MT S + 2πm) + R 2 2 / 2cos (Θ (t) -Θ (t-MT S) + ωi MT S + 2πn) = ^{R 1 2 / 2cos (Θ (} t) -Θ (t-MT S) + ωi MT S) + R 2 2 / 2cos (Θ (t) -Θ (t-MT S) + ωi MT S) = (R 1 2 + R 2 ² ) / ² cos (Θ (t) −Θ (t−MT _S ) + ωi MT _S ) (24) This equation (24) is output from the combined signal output terminal 2410 as an equal gain combining diversity reception signal after differential detection. Is done.

As described above, in this conventional example, since the received signals are synthesized in the IF band, it is difficult to digitize the circuit.
In addition, since the maximum ratio combining of the received signals is not used, the characteristics are deteriorated as compared with the diversity receiver using the maximum ratio combining. Further, since the delay detection is used as the demodulation method, the error rate is deteriorated as compared with the synchronous detection.

[0057]

As described above,
The conventional receiver has the following problems.

First, in the receiver having the AFC function of the conventional example 1, the convergence of the correction value due to the frequency offset is slow, and the range of the frequency offset that can be compensated is narrow. Equipped receiver (conventional example 1)
And the conventional example 2), and the diversity receiver (the conventional example 3), it is difficult to realize high-precision characteristics with low C / N. Third, the receiver having the AFC function (the conventional example) In Example 1 and Conventional Example 2), diversity reception is performed.
Since the diversity receiver (conventional example 3) does not use the maximum ratio combining diversity reception, there is a problem that the characteristics are deteriorated as compared with the receiver using the maximum ratio combining diversity reception.

The present invention has been made in order to solve the above-mentioned problems. The convergence of the correction value due to the frequency offset is fast, the frequency offset over a wide range can be compensated, and the C / N ratio is low.
AF with improved performance, such as realizing high-precision characteristics and using maximum ratio combining diversity reception
It is an object of the present invention to provide a receiver having a C function.

[0060]

In order to solve the above problems, a receiver according to a first aspect of the present invention corrects a phase and / or an amplitude of an input reception signal based on characteristics of an input transmission path. Receiving signal correcting means for outputting the corrected receiving signal, receiving means for receiving the corrected receiving signal, determining means for outputting a determination value which is an estimated value of transmitted data, and output from the determining means. The transmission path characteristics determined by the frequency offset, the carrier phase and the amplitude, based on the determined value or the previously known transmission data, the input frequency offset, and the input received signal. Transmission path estimation means for outputting to the signal correction means,
Input the determination value or known transmission data and the input received signal, and the current determination value or known transmission data,
Mi symbol (i is 1 to S; S is an integer of 2 or more,
Mi is one or more integers different from each other) S frequency offsets for estimating the i-th frequency offset based on the past determination value or known transmission data by the present reception signal and the reception signal by the Mi symbol in the past Estimating means, calculating a finely adjusted frequency offset based on the S i-th frequency offsets output by the S frequency offset estimating means, and transmitting the finely adjusted frequency offset to the transmission path estimating means. And fine adjustment means for outputting.

Further, the receiver according to claim 2 of the present invention comprises:
The phase and / or amplitude of the input received signal is corrected based on the input transmission path characteristics, a received signal correcting unit that outputs the corrected received signal, and the corrected received signal is input and transmitted. A determination unit that outputs a determination value that is an estimated value of data; a determination value output from the determination unit or a known transmission data; a frequency offset to be input; and the frequency based on the input reception signal. A transmission path estimating means for estimating a transmission path characteristic determined by the offset, the carrier phase, and the amplitude, and outputting it to the reception signal correcting means, and inputting the judgment value or known transmission data and the input reception signal. and, the current determination value or known transmitted data, M ₁ symbol (M ₁ is an integer of 1 or more) by a past decision value or known transmit data, and the current reception signal, M A symbol only on the basis of the previously received signal, the first stage of the frequency offset estimation means and a plurality of frequency offset estimation means are stepwise connected following the frequency offset estimating means of the first stage of estimating the frequency offset Then, the judgment value or known transmission data, the input received signal, and the frequency offset output from the frequency offset estimating means at the preceding stage are input, and the current judgment value and the Mi + 1 symbol (i = 1 to 1) are input. S-1; S is an integer of 2 or more; the M ₁ and Mi + 1, and previous decision value or known transmit data differ by an integer of 1 or more) to one another, and the current reception signal, Mi + 1 symbols only past And a second stage to a S-th stage frequency offset estimating means for estimating the finely adjusted frequency offset based on the received signal of the second stage. Wherein the frequency offset stage is estimated is output to the channel estimation unit.

Further, the receiver according to claim 3 of the present invention comprises:
The receiver according to claim 1, wherein the S frequency offset estimating units each receive the received signal,
The current received signal and Mi symbol (i = 1 to S; S is 2
The frequency offset is estimated based on a received signal in the past (the above integer) and known information on the transmitted signal.

Further, the receiver according to claim 4 of the present invention comprises:
2. The receiver according to claim 1, wherein said S frequency offset estimating means inputs said judgment value or known transmission data and said reception signal, and respectively receives a current judgment value or known transmission data and Mi. Symbol (i = 1 to S;
Phase deviation detecting means for detecting a phase deviation occurring between Mi symbols based on a past determination value or known transmission data by S (an integer of 2 or more), a current reception signal, and a reception signal only Mi symbols in the past. And phase deviation averaging means for averaging the phase deviation outputted by the phase deviation detection means and outputting a frequency offset.

A receiver according to claim 5 of the present invention corrects received N received signals (N is an integer of 1 or more) based on N input channel characteristics, respectively. Synthesizing means for outputting a synthesized signal obtained by synthesizing, a judgment means for inputting the synthesized signal and outputting a judgment value which is an estimated value of transmitted data, and a judgment value output from the judgment means or a known value in advance. Inputting transmission data, an input frequency offset, and the N-system input received signals, estimating N-system transmission path characteristics for each of the N-system input received signals, and outputting them to the combining means Transmission path estimating means, the judgment value or the known transmission data, and a judgment value in the past by Mi symbols (i is 1 to S; S is an integer of 2 or more, and each Mi is an integer of 1 or more different from each other). Or known S frequency offset estimators for estimating the i-th frequency offset of the N-system input received signals based on the received data, the current N-system input received signals, and the N-system past input-received signals by Mi symbols. Means, and the S frequency offsets output by the S frequency offset estimating means are input, and the frequency offset for transmission path estimation is finely adjusted, and the finely adjusted frequency offset is sent to the transmission path estimating means. And fine adjustment means for outputting.

Further, the receiver according to claim 6 of the present invention provides:
Synthesizing means for correcting the received N-system input received signals (N is an integer of 1 or more) based on N input channel characteristics, and outputting a synthesized signal obtained by synthesizing them; And a determination unit that outputs a determination value that is an estimated value of transmitted data, a determination value output from the determination unit or previously known transmission data, a frequency offset, and the N-system reception signal. A transmission path estimating means for estimating N transmission path characteristics for each of the N reception signals, and outputting them to the synthesizing means; and the determination value or the known transmission data and the N transmission paths. inputs the input received signal, and the current decision value or known transmitted data, M ₁ symbol (M ₁ is an integer of 1 or more) by a past decision value or known transmit data input receiving the current N systems Nos and, _{M 1} symbol only the past of N
A first stage frequency estimating unit for estimating a frequency offset based on an input received signal of a system, and a plurality of frequency offset estimating units connected stepwise after the first stage frequency offset estimating unit; , The determined value or the known transmission data, the input reception signals of the N systems, and the frequency offset output from the frequency offset estimating means at the preceding stage are input, and the current determined value and the Mi + 1 symbol (i
= 1 to S-1; S is an integer of 2 or more; M ₁ and Mi + 1 are one or more integers different from each other), the past judgment values or known transmission data, and the current N input reception signals, Mi +
Frequency offset estimating means from the second stage to the (S-1) -th stage for estimating the finely adjusted frequency offset based on the input reception signals of N systems only one symbol in the past. The N frequency offsets estimated by the frequency offset estimating means are output to the transmission path estimating means.

Further, the receiver according to claim 7 of the present invention provides:
6. The receiver according to claim 5, wherein each of the S frequency offset means inputs the N input received signals, and inputs the current N input received signals and Mi symbols (i = 1 to S). S is an integer of 2 or more; Mi is an integer of 1 or more different from each other)
A frequency offset is estimated based on known information on a transmission signal.

Further, the receiver according to claim 8 of the present invention provides:
The receiver according to claim 5, wherein the S frequency offset estimating means inputs the determination value or the known transmission data and the N-system input reception signals, respectively.
A current determination value or known transmission data, a determination value or known transmission data past by Mi symbols (i = 1 to S; S is an integer of 2 or more; Mi is an integer of 1 or more different from each other), Phase deviation detecting means for detecting a phase deviation occurring between the Mi symbols based on the N received input signals and the N received input signals in the past by Mi symbols;
Averaging the phase deviation output by the phase deviation detection means,
Phase deviation averaging means for outputting a frequency offset.

A receiver according to a ninth aspect of the present invention provides:
9. The receiver according to claim 4, wherein said phase deviation detecting means outputs a phase deviation represented by a complex number, and said phase deviation averaging means comprises a complex number generated between Mi symbols output by said phase deviation detecting means. Inputting the phase deviation of the display, converting the phase deviation of the complex representation into polar coordinates, and outputting a phase component obtained by the conversion, and inputting the phase component output by the polar coordinate conversion means, and inputting the phase per symbol. Averaging means for estimating the deviation.

According to a tenth aspect of the present invention, in the receiver according to the fourth or eighth aspect, the phase deviation detecting means outputs a phase deviation represented by a complex number,
The phase deviation averaging means is provided with an averaging means for inputting a complex-valued phase deviation generated between the Mi symbols output from the phase-deviation detecting means, and averaging the complex-valued phase deviation, and a complex output by the averaging means. Polar coordinate conversion means for inputting the displayed phase deviation and outputting a phase component obtained by converting to a polar coordinate, and dividing means for inputting the phase component output by the polar coordinate conversion means and calculating a phase deviation per symbol. , Is characterized by having.

Also, a receiver according to claim 11 of the present invention is a means for multiplying an input received signal to generate a multiplied received signal representing a known fixed value; A fixed value is input, and only the known fixed value, the current multiplied received signal, and Mi symbols (i is 1 to S; S is an integer of 2 or more, and each Mi is an integer of 1 or more different from each other) S frequency offset estimating means for estimating a frequency offset based on the past multiplied received signal,
A fine adjustment means for calculating and outputting a finely adjusted frequency offset based on the S i-th frequency offsets output by the S frequency offset estimating means, and a fine adjustment output by the fine adjustment means The frequency offset is determined by the frequency dividing means for inputting the frequency offset and outputting the frequency division value thereof, the frequency offset after frequency division outputted by the frequency dividing means, and the carrier phase and amplitude of the input received signal. Transmission path estimation means for estimating transmission path characteristics, a reception signal correction means for inputting the transmission path characteristics output by the transmission path estimation means and the input received signal, and correcting the phase and / or amplitude of the input received signal. Wherein the determination is performed on the input received signal corrected by the received signal correcting means.

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In the receiver according to the first aspect of the present invention, the received signal correcting means corrects the phase and / or the amplitude of the input received signal based on the characteristics of the input transmission path, and the judging means makes the corrected signal. A received signal is input, and a determination value that is an estimated value of transmitted data is output. Further, the transmission path estimating means determines the frequency offset, the carrier phase, and the amplitude based on the determination value output from the determining means or the known transmission data, the input frequency offset, and the input received signal. The determined transmission path characteristics are estimated and output to the received signal correction means, and the S frequency offset estimating means inputs a judgment value or known transmission data and an input reception signal, and outputs a current judgment value or a known judgment value. Transmission data, and the past determination values or known transmission data by Mi symbols (i is 1 to S; S is an integer of 2 or more, and Mi is one or more integers different from each other), and the current reception signal , M
The i-th frequency offset is estimated based on the received signal of the i-th symbol in the past, and the fine adjustment unit is finely adjusted based on the S i-th frequency offsets output from the S frequency offset estimation units. The frequency offset is calculated, and the finely adjusted frequency offset is output to the transmission path estimating means. As a result, frequency offset estimation with high accuracy and a wide estimation range can be realized.

In the receiver according to a second aspect of the present invention, the phase and / or amplitude of the input received signal is corrected based on the input transmission path characteristics, and the corrected received signal is output. A correction unit, a determination unit that receives the corrected reception signal, and outputs a determination value that is an estimated value of the transmitted data, and a determination value output from the determination unit or previously known transmission data; A transmission path estimating means for estimating a transmission path characteristic determined by the frequency offset, the carrier phase and the amplitude based on the frequency offset and the input received signal, and outputting the transmission path characteristic to the reception signal correcting means. the type judgment value or the known transmission data and said input receive signal, and the current decision value or known transmitted data, M ₁ symbol (M ₁ is an integer of 1 or more) only in the last A value or known transmit data, and the current reception signal, based on the previously received signal by M ₁ symbols, a frequency offset estimation unit in the first stage of estimating the frequency offset, the first stage of frequency offset estimating means A plurality of frequency offset estimating means connected in a stepwise manner, wherein the determination value or known transmission data, the input received signal, and the frequency offset output by the frequency offset estimating means at the preceding stage are input. , The current judgment value, and Mi + 1 symbols (i = 1 to S−1; S is 2
An integer greater than or equal to; M ₁ and Mi + 1 are one or more integers different from each other) and a past determination value or known transmission data;
Frequency offset estimating means from the second stage to the S-th stage for estimating the finely adjusted frequency offset based on the current received signal and the received signal only Mi + 1 symbols in the past;
And the frequency offset estimated by the S-stage frequency offset estimating means is output to the transmission path estimating means. As a result, frequency offset estimation with high accuracy and a wide estimation range can be realized.

Further, in the receiver according to claim 3 of the present invention, the S frequency offset estimating means inputs the received signal, respectively, and inputs a current received signal and Mi symbols (i = 1 to S S is an integer of 2 or more), and the frequency offset is estimated based on the received signal in the past and the known information on the transmitted signal. This allows
The frequency offset can be corrected with high accuracy without being affected by the determination error.

In the receiver according to claim 4 of the present invention, the phase deviation detecting means of the S frequency offset estimating means inputs the judgment value or known transmission data and the reception signal, Each of the current determination value or the known transmission data and the Mi symbol (i = 1 to S; S is 2
Based on the past judgment value or known transmission data by the above integer), the current received signal, and the received signal only Mi symbols in the past, detects a phase deviation occurring between the Mi symbols, and the phase deviation averaging means detects The phase deviation output from the phase deviation detecting means is averaged to output a frequency offset. That is, the frequency offset is estimated from the phase deviation generated between the Mi symbols based on the judgment value obtained by the judgment means or the known transmission signal in advance, so that the time constant of the averaging can be reduced as compared with the related art. Accurate and fast convergence frequency offset estimation can be realized. In addition, since the influence of the determination error is 1 / Mi of the related art, even when the determination error occurs relatively frequently, the operation can be performed with high accuracy.

Further, in the receiver according to the fifth aspect of the present invention, the synthesizing means may receive the N systems (N is an integer of 1 or more).
Are corrected based on the N transmission path characteristics respectively input, and a composite signal obtained by combining them is output. The determination means inputs the composite signal, and the estimated value of the transmitted data is A certain determination value is output, and the transmission path estimating means inputs the determination value or the previously known transmission data output from the determining means, the input frequency offset, and the N-system input reception signals, Estimate N transmission path characteristics for each of the N input reception signals, output them to the combining means, and S frequency offset estimating means determine whether the determination value or known transmission data and Mi
Symbol (i is 1 to S; S is an integer of 2 or more, and each M
i is one or more integers different from each other) based on the past determination value or known transmission data, the current N input reception signals, and the N previous N system input reception signals by Mi symbols. Estimating the i-th frequency offset of the input received signal, the fine adjustment means inputs the S frequency offsets output by the S frequency offset estimating means, performs fine adjustment of the frequency offset for transmission path estimation,
The finely adjusted frequency offset is output to the transmission path estimating means. As a result, frequency offset estimation with high accuracy and a wide estimation range can be realized.

Further, in the receiver according to claim 6 of the present invention, the received N systems (N is an integer of 1 or more) of received input signals are corrected based on the N transmission line characteristics respectively input. Synthesizing means for outputting a synthesized signal obtained by synthesizing them, judgment means for inputting the synthesized signal and outputting a judgment value which is an estimated value of transmitted data, judgment value outputted from the judgment means or A transmission path for inputting known transmission data, a frequency offset, and the N-system reception signals, estimating N-system transmission path characteristics for each of the N-system reception signals, and outputting them to the combining means. an estimation unit, wherein the determination value or known transmit data inputs the input reception signal of N lines, and current determination value or known transmitted data, M ₁ symbol (M ₁ is an integer of 1 or more) by the last Size of The value or known transmission data, an input reception signal of the current N systems, M ₁ symbols only past N
A first stage frequency estimating unit for estimating a frequency offset based on an input received signal of a system, and a plurality of frequency offset estimating units connected stepwise after the first stage frequency offset estimating unit; , The determined value or the known transmission data, the input reception signals of the N systems, and the frequency offset output from the frequency offset estimating means at the preceding stage are input, and the current determined value and the Mi + 1 symbol (i
= 1 to S-1; S is an integer of 2 or more; M ₁ and Mi + 1 are one or more integers different from each other), the past judgment values or known transmission data, and the current N input reception signals, Mi +
Frequency offset estimating means from the second stage to the (S-1) -th stage for estimating the finely adjusted frequency offset based on the input reception signals of N systems only one symbol in the past. The N frequency offsets estimated by the frequency offset estimating means are output to the transmission path estimating means. As a result, frequency offset estimation with high accuracy and a wide estimation range can be realized.

In the receiver according to claim 7 of the present invention, each of the S frequency offset means receives the N input received signals, and receives the current N input received signals and Mi. N past symbols (i = 1 to S; S is an integer of 2 or more; Mi is an integer of 1 or more different from each other)
The frequency offset is estimated based on the input received signal of the system and the known information on the transmission signal.
Thus, maximum ratio combining diversity and frequency offset correction can be realized with high accuracy without being affected by a determination error.

Further, in the receiver according to claim 8 of the present invention, the phase deviation detecting means of the S frequency offset estimating means determines whether or not the determination value or known transmission data and the N-system input reception signal have been transmitted. Is input, and the current judgment value or known transmission data and the past judgment value or known transmission data by Mi symbols (i = 1 to S; S is an integer of 2 or more; Mi is an integer of 1 or more different from each other) A phase deviation occurring between the Mi symbols based on the current N systems of input reception signals and the N previous N systems of input reception signals, and phase deviation averaging means averaging the phase deviations; Outputs frequency offset.

As described above, since the frequency offset is estimated from the phase deviation generated between the Mi symbols based on the judgment value obtained by the judgment means or the known transmission signal in advance, the time constant of the averaging is reduced as compared with the related art. Therefore, frequency offset estimation with high accuracy and fast convergence can be realized. In addition, since the influence of the determination error is 1 / Mi of the related art, even when the determination error occurs relatively frequently, the operation can be performed with high accuracy.

In the receiver according to the ninth aspect of the present invention, the phase deviation detecting means outputs a phase deviation represented by a complex number, and the polar coordinate conversion means of the phase deviation averaging means comprises:
The phase deviation detecting means receives the input of the complex-valued phase deviation generated between the Mi symbols and outputs a phase component obtained by converting the complex-valued phase deviation into polar coordinates. The averaging means outputs the polar coordinates. The phase component output from the conversion means is input, and the phase deviation per symbol is estimated. In the complex representation of the phase deviation, for example, the cosine value of the phase deviation is a real part, and the sine value is an imaginary part. Thus, the calculation of the arc tangent is performed after the averaging, and the phase jump can be prevented.

In the receiver according to a tenth aspect of the present invention, the phase deviation detecting means outputs a phase deviation represented by a complex number, and the averaging means of the phase deviation averaging means comprises a phase deviation detecting means. Input the complex-valued phase deviation generated between the Mi symbols, averages the complex-valued phase deviation, and converts the complex-valued phase deviation output by the averaging means into polar coordinates. The dividing means inputs the phase component output from the polar coordinate converting means, and calculates the phase deviation per symbol. In the complex representation of the phase deviation, for example, the cosine value of the phase deviation is a real part, and the sine value is an imaginary part. As a result, the averaging is performed after the arc tangent calculation, and the processing of complex numbers can be reduced, and even if the calculation accuracy of the arc tangent is not sufficient, the deterioration in accuracy due to the arc tangent processing can be improved.

Further, in the receiver according to the eleventh aspect of the present invention, the received signal is multiplied to remove the modulation component, so that it is not necessary to use the judgment value or the known transmission data in the frequency offset estimation.

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Next, an embodiment of the present invention will be described with reference to the drawings.

Embodiment 1 of the Invention FIG. 1 is a configuration diagram of a receiver having an AFC function according to Embodiment 1 of the present invention. In the figure, 11 is a reception signal input terminal, 12 is a reception signal from the reception signal input terminal 11, a judgment value from the judgment circuit 15, and a frequency offset from the frequency offset estimation circuit A16 to input a transmission line characteristic. A transmission path estimating circuit for estimating 13; a complex conjugate circuit for calculating a complex conjugate value of the transmission path characteristic output from the transmission path estimating circuit 12;
Is a multiplication circuit that calculates a multiplication value of the complex conjugate value output from the complex conjugate circuit 13 and the reception signal from the reception signal input terminal 11, and 15 is a multiplication circuit that receives the multiplication value output from the multiplication circuit 14 and transmits the multiplication value. A decision circuit 16 outputs a decision value which is an estimated value of data. A frequency offset estimating circuit A 16 receives a decision value output from the decision circuit and a reception signal from the reception signal input terminal 11 and outputs a frequency offset. 17 is a judgment value output terminal.

FIG. 2 is a diagram showing the internal configuration of the frequency offset estimating circuit A16 in FIG. 1. In FIG. 2, reference numeral 11 denotes a reception signal input terminal, reference numeral 17 denotes a judgment value input terminal, and reference numeral 21 denotes a reception signal from the reception signal input terminal 11. A signal and a judgment value from the judgment value input terminal 17 are input, and phase deviation detection circuits A and 22 for detecting a phase deviation average the phase deviation outputted from the phase deviation detection circuit A21, and estimate the frequency offset. Are the frequency offset output terminals.

FIG. 3 is a block diagram showing an example of the internal configuration of the phase deviation detection circuit A21 in FIG.
11 is a reception signal input terminal, 17 is a judgment value input terminal, 31
Is a received signal phase deviation detection circuit A, 32 which receives a received signal from the received signal input terminal 11 and outputs a phase deviation of the received signal (a value obtained by displaying a complex symbol representing the result of M symbol delay detection of the received signal in complex number). Is a decision value phase deviation detection circuit A which outputs a phase deviation of the decision value from the decision value input terminal 17 (a value representing the phase deviation between M symbols of the decision value in a complex number); A complex conjugate circuit for calculating a complex conjugate value of a phase deviation of the output judgment value (a value obtained by expressing the phase deviation between M symbols of the judgment value in a complex number); 34 is a complex conjugate value output from the complex conjugate circuit 33; A multiplication circuit that calculates a multiplication value by a phase deviation of the reception signal output from the reception signal phase deviation detection circuit A31 (a value obtained by displaying a complex symbol representing the result of M symbol delay detection of the reception signal in a complex number). 35 is a phase difference output terminal.

FIG. 4 is a configuration diagram showing an example of the internal configuration of the reception signal phase deviation detection circuit A31 in FIG. 3. In the drawing, reference numeral 11 denotes a reception signal input terminal, and 41 denotes a reception signal from the reception signal input terminal 11. An M symbol delay circuit for delaying the signal by M symbols and outputting the signal, 42 a complex conjugate circuit for calculating a complex conjugate value of the delay signal output from the M symbol delay circuit 41, 43 a reception signal from the reception signal input terminal 11 A multiplication circuit for calculating a multiplication value of the complex conjugate value output from the complex conjugate circuit 42 and a reception signal phase deviation output terminal 44. Note that the judgment value phase deviation detection circuit A in FIG.
32 can be configured in the same manner as the reception signal phase deviation detection circuit A31 (FIG. 4).

FIG. 5 is a block diagram showing an example of the internal configuration of the phase deviation averaging circuit A22 in FIG. 2. Reference numeral 35 denotes a phase deviation input terminal, and 51 denotes an arctangent value of the phase deviation from the phase deviation input terminal 35. Is a division circuit that divides the arc tangent value output by the arc tangent circuit 51 by M, 53 is an average of the division values output by the division circuit 52,
An averaging circuit 23 for outputting the estimated value of the frequency offset is a frequency offset output terminal.

FIG. 6 is a block diagram showing another example of the internal configuration of the phase deviation averaging circuit A22 in FIG.
Is an averaging circuit for averaging the complexly displayed phase deviation from the phase deviation input terminal 35, and 62 is an arc tangent for calculating the arc tangent of the complex displayed average output from the averaging circuit 61. A circuit 63 divides the arc tangent value output from the arc tangent circuit 62 by M and outputs an estimated value of the frequency offset, and 23 is a frequency offset output terminal.

Next, the operation of the receiver according to the present embodiment will be described. In FIG. 1, a transmission path estimating circuit 12 includes a determination value output from a determination circuit 15 and a reception signal input terminal 11.
, And a frequency offset, and outputs an estimated value of the transmission path characteristic. The complex conjugate circuit 13 calculates a complex conjugate value of the estimated value of the transmission path output from the transmission path estimating circuit 12 and outputs it to the multiplying circuit 14.

The multiplication circuit 14 calculates a multiplication value of the complex conjugate value output from the complex conjugate circuit 13 and the reception signal from the reception signal input terminal 11 and outputs the result to the determination circuit 15. In the determination circuit 15, from the multiplied value output from the multiplication circuit 14,
A judgment value, which is an estimated value of the transmitted data, is judged and outputted from a judgment value output terminal 17. Further, in the frequency offset estimation circuit A16, the judgment value output from the judgment circuit 15 and the reception signal from the reception signal input terminal 11 are input,
The estimated value of the frequency offset of the received signal is output to the transmission path estimation circuit 12.

Here, the frequency offset estimating circuit A16
Will be described with reference to FIG. In the figure, a phase deviation detection circuit A21 is connected to a reception signal input terminal 11
And the judgment value from the judgment value input terminal 17, and calculates the phase deviation of the reception signal by the phase deviation averaging circuit A2.
Output to 2. The phase deviation averaging circuit A22 averages the phase deviation output from the phase deviation detection circuit A21, and outputs the estimated value of the frequency offset to the frequency offset output terminal 2.
Output from 3.

Next, the phase deviation detection circuit A2 in FIG.
The operation 1 will be described with reference to the configuration example of FIG. In FIG. 3, a received signal phase deviation detection circuit A31 receives a received signal from a received signal input terminal 11 and receives the received signal, thereby obtaining a phase deviation of the received signal (a value obtained by complexly displaying the result of M symbol delay detection of the received signal represented by a complex number). Is output to the multiplication circuit 34.

On the other hand, the judgment value phase deviation detection circuit A32 receives the judgment value from the judgment value input terminal 17 and determines the phase deviation of the judgment value (a value obtained by expressing the phase deviation between M symbols of the judgment value in a complex number). Output to the complex conjugate circuit 33. The complex conjugate circuit 33 receives the phase deviation of the decision value output from the decision value phase deviation detection circuit A32 (a value representing the phase deviation between M symbols of the decision value in a complex number) and calculates the complex conjugate value. , To the multiplication circuit 34.

In the multiplication circuit 34, the complex conjugate value output from the complex conjugate circuit 33 and the received signal phase deviation detection circuit A31
Is multiplied by the phase deviation of the received signal output by the above (a value obtained by displaying the complex symbol-decoded M-symbol delayed detection result of the received signal as a complex number), and the result is output from the phase deviation output terminal 35.

Next, the operation of the reception signal phase deviation detection circuit A31 in FIG. 3 will be described using the configuration example in FIG. In FIG. 4, an M symbol delay circuit 41 delays the received signal input from the received signal input terminal 11 by M symbols and outputs the delayed signal to the complex conjugate circuit 42. The complex conjugate circuit 42 calculates a complex conjugate value of the delay signal output from the M symbol delay circuit 41 and outputs the complex conjugate value to the multiplication circuit 43.

The multiplication circuit 43 calculates the multiplication value of the complex conjugate value output from the complex conjugate circuit 42 and the reception signal from the reception signal input terminal 11, and calculates the phase deviation of the reception signal (complex number of the reception signal represented by a complex number). The M symbol differential detection result is represented by M
The result of correction using the phase deviation of the determination value between symbols is displayed as a complex value) from the reception signal phase deviation output terminal 44. Note that the judgment value phase deviation detection circuit A32 operates in the same manner.

Next, the phase deviation averaging circuit A2 in FIG.
Operation 2 will be described with reference to the configuration example of FIG. In FIG. 5, the arc tangent circuit 51 includes a phase deviation input terminal 35.
, And calculates the arc tangent value of the complex-displayed phase deviation from, and outputs the arc tangent value to the division circuit 52. The division circuit 52 divides the arc tangent value output from the arc tangent circuit 51 by M, and outputs the result of the division to the averaging circuit 53. The averaging circuit 53 averages the division values output from the division circuit 52, and outputs the average value from the frequency offset output terminal 23 as an estimated value of the frequency offset.

The phase deviation averaging circuit A2 in FIG.
Operation 2 will be described with reference to another configuration example in FIG. 6, the averaging circuit 61 averages the complexly displayed phase deviation from the phase deviation input terminal 35 and outputs the result to the arctangent circuit 62. In the arc tangent circuit 62, the averaging circuit 61
Is calculated, and the result is output to the division circuit 63. The division circuit 63 divides the arc tangent value output by the arc tangent circuit 62 by M, and outputs the division value from the frequency offset output terminal 23 as an estimated value of the frequency offset.

Next, the operation of the present embodiment described above will be described more specifically (qualitatively).

In FIG. 1, assuming that the received signal at time n is rn and the tap coefficient of the transmission line characteristic is gn, the output of the multiplying circuit 14 is obtained by correcting the phase of the received signal rn based on the phase of the tap coefficient gn. Expression (25) is output.

G n ^* · rn (25) Here, assuming that the transmission signal is, for example, a four-phase PSK, the determination circuit 15 determines that the multiplied value is the first value on the complex plane.
If it is in the quadrant, the judgment value Jn is set to exp (jπ / 4),
Exp (j3π / 4) when in the quadrant, exp (j5π / 4) when in the third quadrant, exp when in the fourth quadrant
(J7π / 4). In this case, as the determination value, not only the hard determination value but also the above-described soft determination value can be output. When the output of the soft decision value is required, a multiplied value is output, for example, as shown in Expression (25).

Next, the transmission path estimating circuit 12 calculates an estimated value of the transmission path characteristic using the judgment value Jn and the estimated value Δωn of the frequency offset output from the frequency offset estimating circuit A16. Here, the case where the LMS algorithm is used will be described. That is, the transmission path estimation circuit 12
Calculates the estimated tap coefficient by the equation (26) using the above determination value Jn.

Gn + 1 = {gn + δ (rn−gn · Jn) Jn ^* ｝ exp (jΔωn) (26) The parentheses in the expression (26) indicate the update of the tap coefficient gn based on the LMS algorithm. And exp (jΔωn) is a term for correcting the phase rotation component due to the frequency offset.

Next, an example of the internal operation of the frequency offset estimating circuit A16 will be specifically described with reference to FIG. The phase deviation detecting circuit A21 calculates the complex-displayed phase deviation occurring between M symbols by the equation (27) using the received signal rn and the judgment value Jn.

ΔW′n = (Jn · Jn−M ^* ) ^* rn · rn−M ^* (27) When the phase deviation averaging circuit A22 is configured as shown in FIG. Deviation detection circuit A21
The frequency offset is calculated from the phase deviation ΔWn output from. In the case of the configuration as shown in FIG. 6, the frequency offset is calculated by the equations (29) and (30).

Δωn + 1 = (1−α) Δωn + α arctan (ΔW′n) / M (28) ΔWn + 1 = (1−α) ΔWn + αΔW′n (29) Δωn + 1 = arctan ( ΔWn + 1) / M (30) Further, the expression (28) is the expression (31) and the expression (29) is the expression (3)
2) can be replaced with the respective expressions.

[0123]

(Equation 2) Here, α and K are values related to the time constant of the averaging circuit 53 or 61.

The difference between the configurations of FIGS. 5 and 6 is the order of averaging and arctangent calculation. As shown in FIG. 6, by performing averaging before calculating the arctangent and averaging on the complex plane, it is possible to prevent a phase jump. On the other hand, FIG.
When the averaging is performed after the calculation of the arc tangent, the circuit becomes simpler, and even when the calculation accuracy of the arc tangent is low, the deterioration of the accuracy due to the arc tangent processing can be improved.

In the frequency offset estimation, M
Since the operation of obtaining the phase deviation per symbol from the symbol phase deviation includes the effect of averaging for suppressing phase fluctuation due to noise, the time constant of averaging in the averaging circuit 53 or 61 is set to a relatively large value. , And frequency offset estimation with high accuracy and fast convergence can be performed.

Further, the influence of a decision error when the decision of the current received signal is erroneous can be suppressed to 1 / M as compared with the case where the decision is made based on the phase deviation of one symbol. It is possible to operate with high accuracy even at a frequently occurring low C / N.

As described above, in the present embodiment,
The received signal is corrected according to the transmission path characteristics with respect to the received signal, and the result is used to output a judgment value that is an estimated value of the transmitted data, and the frequency offset is set to the current judgment value, and the judgment value of the M symbol past is judged. By estimating from the current received signal and the received signal in the past M symbols, the frequency offset, the determination value, estimating the channel characteristics from the received signal, and multiplying the received signal by the complex conjugate of the channel characteristics,
Phase rotation due to frequency offset can be eliminated.

In the above description, LMS is used for transmission path estimation.
Although the case where the algorithm is used has been described, the transmission path estimation may be performed by an adaptive algorithm such as the RLS algorithm. As described above, if the transmission channel estimation is performed successively using the adaptive algorithm, it is possible to follow the variation of the transmission channel characteristics even when the variation is high speed.

In the above description, the case where the judgment value is used to calculate the phase deviation has been described, but a known transmission signal may be used instead of the judgment value. Further, in the configuration of the phase deviation detection circuit A21 shown in FIG. 3, a judgment value phase deviation detection circuit A32 when a known transmission signal is input in advance.
Can be used in place of the judgment value phase deviation detection circuit A32.

Further, by outputting the soft decision value, the bit error rate characteristics of the subsequent Viterbi decoder can be improved.

Embodiment 2 of the Invention Next, FIG. 7 is a configuration diagram of a receiver having an AFC function according to a second embodiment of the present invention. In the figure, the same or corresponding components as in the first embodiment (FIG. 1) are denoted by the same reference numerals. The difference between the configuration of the present embodiment and the first embodiment is the frequency offset estimation part. The following description focuses on the frequency offset estimation part.

In FIG. 7, reference numeral 77 denotes a reception signal input terminal 1
An arc tangent circuit for calculating an arc tangent value of the received signal from No. 1 is a frequency offset estimating circuit B for outputting a frequency offset based on the received signal from the received signal input terminal 11.

FIG. 8 is a configuration diagram showing the internal configuration of the frequency offset estimation circuit B76 in FIG. In the figure, 1
1 is a reception signal input terminal, 17 is a judgment value input terminal, 81-
1 to 81-S input the reception signal from the reception signal input terminal 11 and the judgment value from the judgment value input terminal 17,
M _1, M _2, ..., the phase difference detecting circuit B1～BS for outputting a phase deviation occurring between M _S symbols to each phase difference averaging circuit B1~BS (82-1~82-S), 82-1~82
-S is a phase deviation detection circuit B1 to BS (81-1 to 81-
The phase deviation averaging circuits B1 to BS, 83-1 for averaging the phase deviations output from S) are phase deviation averaging circuits B1
(82-1) The fine adjustment circuit which performs the fine adjustment of the frequency offset by inputting the estimated value of the frequency offset output from (82-1) and the estimated value of the frequency offset output from the phase deviation averaging circuit B2 (82-2). 1, 83-2 to 83-S-
1 are phase deviation averaging circuits B3 to BS (82-3
-82-S) and the estimated value of the frequency offset, and fine adjustment circuits 1 to S-2 (83-1 to 83-S-2).
Input the estimated value of the frequency offset output by the sub-controller, and fine-adjust circuits 2 to S-1 and 8 for fine-adjustment of the frequency offset
4 is a frequency offset output terminal.

Next, FIG. 9 is a configuration diagram showing an example of the internal configuration of the phase deviation detection circuit B1 (81-1) in FIG. In the figure, the received signal input terminal, the decision value input terminal 17, 91-1 inputs the received signal from the reception signal input terminal 11, the received signal phase difference detecting the phase difference of M ₁ symbols of the received signal 11 detection circuit B1,92-1 determination value by entering the decision value from the input terminal 17, the determination value phase difference detecting circuit for detecting the phase difference of M ₁ symbol determination value B1,
93-1 is a reception signal phase deviation detection circuit B1 (91-1)
And a phase deviation of the judgment value output from the judgment value phase deviation detection circuit B1 (92-1), and subtracts the phase deviation of the judgment value from the phase deviation of the reception signal. , 94-1 are phase deviation output terminals.
Note that the phase deviation detection circuits B2 to BS (81-2 to 81-
The configuration of S) has the same configuration, and the M ₁ symbol is M ₂ ,
..., it is the same, except that the M _S symbol.

Next, FIG. 10 is a configuration diagram showing an example of the internal configuration of the reception signal phase deviation detection circuit B1 (91-1) in FIG. In the figure, 11 is a reception signal input terminal, 101
M _1-symbol delay circuit the received signal is M ₁ symbol delay from -1 reception signal input terminal 11, 102 - M
A subtraction circuit for subtracting the delay signal output from the _one- symbol delay circuit 101-1 from the reception signal from the reception signal input terminal 11 is a subtraction circuit. Reference numeral 103-1 is a reception signal phase deviation output terminal. The reception signal phase deviation detection circuits B2 to BS (9
1-2~91-S) configurations are similar structure, M ₁ symbols M _2, ..., is the same except that the M _S symbols. Further, the judgment value phase deviation detection circuits B1 to BS (92-
1-92-S) has the same configuration.

FIG. 11 is a diagram showing an example of the internal configuration of the phase deviation averaging circuit B1 (82-1) in FIG. In the figure, 94-1 is a phase deviation input terminal, 111-1
Divider circuit for dividing the phase deviation of the phase difference input terminal 94-1 by M _1, the 112-1 averaging circuit for averaging the quotient output from the dividing circuit 111-1, 113-1 frequency offset output Terminal. Note that the phase deviation averaging circuits B2 to BS (82-2 to 82-S) also have M
The configuration is the same except that ₁ becomes M ₂ ,..., M _S.

Next, FIG. 12 shows the fine adjustment circuit 1 in FIG.
It is a lineblock diagram showing an example of an internal configuration of (83-1). In the figure, 113-1 is a frequency offset input terminal A (output of the phase deviation averaging circuit B1), 113-2 is a frequency offset input terminal B (output of the phase deviation averaging circuit B2), 121
-1 is a subtraction circuit for calculating the difference between two frequency offsets from the frequency offset input terminal A113-1 and the frequency offset input terminal B113-2, and 122-1 is the remainder of the subtraction value output by the subtraction circuit 121-1. The remainder circuit 1 to be calculated, 123-1 is a frequency offset input terminal A1
13-1 and the remainder circuit 1 (122
-1) an addition circuit for performing addition with the remainder output by 124
-1 is a frequency offset output terminal. The fine adjustment circuits 2 to S-1 (83-2 to 83-S-1) have the same configuration.

Next, the operation of the receiver according to the present embodiment will be described. The components denoted by the same reference numerals as those of the first embodiment perform the same operations as those of the first embodiment, and the difference between the first embodiment and the first embodiment is the portion for estimating the frequency offset. Therefore, only this portion will be described.

The operation of the frequency offset estimating circuit B76 will be described with reference to the configuration example of FIG. 8, phase deviation detection circuits B1 to BS (81-1 to 81-
S) inputs the reception signal from the reception signal input terminal 11 and the judgment value from the judgment value input terminal 17, and outputs M ₁ , M ₂ ,.
Phase phase deviation occurring between M _S symbols deviation averaging circuit B
1 to BS (82-1 to 82-S).

The phase deviation averaging circuits B1 to BS (82-1 to 82-1)
82-S), the phase deviation detection circuits B1 to BS (81-S)
1 to 81-S), the phase deviation of the S system output is input, the phase deviation is averaged, and the phase deviation per symbol is finely adjusted by the fine adjustment circuits 1 to S-2 (83-1 to 8-8).
3-S-1). Fine adjustment circuits 1 to S-2
In (83-1 to 83-S-1), frequency offsets of two systems are input, and fine adjustment of the frequency offset in a wide estimation range is performed by the high-accuracy frequency offset, and the result is output.

Next, the phase deviation detection circuit B1 in FIG.
The operation of (81-1) will be described using the configuration example of FIG. In FIG. 9, a reception signal phase deviation detection circuit B1
(91-1) detects phase difference generated between M ₁ symbols of the received signal input from reception signal input terminal 11. The decision value phase difference detecting circuit B1 (92-1), for detecting a phase difference generated between M ₁ symbol decision value input from the decision value input terminal 17.

Further, in the subtraction circuit 93-1, the phase deviation outputted from the reception signal phase deviation detection circuit B1 (91-1) is calculated based on the phase deviation outputted from the judgment value phase deviation detection circuit B1 (92-1). And outputs the subtracted value from the phase deviation output terminal 94-1 as a phase deviation. Incidentally, for the phase difference detecting circuit B2~BS (81-2~81-S), M 1 is M _2, M _3, ..., which is the same operation except that the M _S.

Next, the operation of the reception signal phase deviation detection circuit B1 (91-1) in FIG. 9 will be described using the configuration example of FIG. In FIG. 10, M _1-symbol delay circuit 101-1, the received signal from the reception signal input terminal 11 by M _1-symbol delay and outputs to the subtraction circuit 102-1. The subtraction circuit 102-1 is connected to the reception signal input terminal 11
From the received signal from, M _1-symbol delay circuit 101-1
, And outputs the subtracted value from the received signal phase deviation output terminal 103-1. Incidentally, also the received signal phase difference detecting circuit B2~BS (91-2~91-S), M 1 is M _2, M _3, ..., a similar operation except that the M _S, also in FIG. 9 The judgment value phase deviation detection circuits B1 to BS (92-1 to 92-S) perform the same operation.

Next, the phase deviation averaging circuit B1 in FIG.
The operation of (82-1) will be described using the configuration example of FIG. The division circuit 111-1 has a phase deviation input terminal 9
The phase deviation from 4-1 is divided by M ₁ and the averaging circuit 112
Output to -1. In the averaging circuit 112-1, the division circuit 1
11-1 averages the divided values output, and uses the result as a frequency offset as a frequency offset output terminal 113-
Output from 1. The phase deviation averaging circuits B2 to BS (8
2-2~82-S) for also, M ₁ is M _2, M _3,
.., M _S is the same operation.

Further, the fine adjustment circuit 1 (83-
The operation 1) will be described with reference to the configuration example of FIG. The subtraction circuit 121-1 subtracts the frequency offset from the frequency offset input terminal B (113-2) from the frequency offset from the frequency offset input terminal A (113-1), and outputs the subtracted value to the remainder circuit 1. (122-
Output to 1). The remainder circuit 1 (122-1) calculates a remainder of 2π / M ₂ of the subtraction value output from the subtraction circuit 121-1. However, the output range is [-π / M ₂ , π / M ₂ )
It is.

The addition circuit 123-1 adds the frequency offset from the frequency offset input terminal A (113-1) to the remainder output from the remainder circuit 1 (122-1), and uses the result as a frequency offset to obtain the frequency offset. Output from the offset output terminal 124-1. The fine adjustment circuit 2
To S-1 (83-2 to 83-S-1), M ₂
But M _3, M _4, ..., is the same operation except that the M _S.

The operation of the present embodiment described above will be described more specifically (qualitatively). For simplicity of explanation, it is assumed that S = 2 and M ₁ > M ₂ . In FIG. 8, time n
The phase of the transmission signal at γn and the phase of the reception signal at γn
Then, the outputs of the phase deviation detection circuits B1 (81-1) and B2 (81-2) are (3
Expressions 3) and (34) are obtained.

[0148] Δω '(1) n = ( γn -γn- M 1) - (Θn -Θn- M 1) ... (33) Δω' (2) n = (γn -γn- M 2) - (Θn - (N−M ₂ ) (34) Then, the phase deviation averaging circuits B1 and B2 (82-1, 8)
In 2-2), Δω ′ (1) n and Δω ′ (2) n are set to 1 / M ₁ and 1 / M ₂ respectively, and averaging is performed to suppress fluctuation due to noise. Equations (35) and (36) are this operation.

Δω (1) n + 1 = (1−α) Δω (1) n + αΔω ′ (1) n / M ₁ (35) Δω (2) n + 1 = (1−α) Δω (2 ) n + αΔω ′ (2) n / M ₂ (36) Equations (35) and (36) are equivalent even if the order of division and averaging is changed. Where Δω (1) n, Δω (2) n
Are phase deviation averaging circuits B1 and B2 (82-1, 82-
This is the estimated value of the frequency offset output from 2).
Further, the expressions (35) and (36) can be replaced with the expressions (37) and (38).

[0150]

(Equation 3) Here, α and K are averaging circuits 112-1 and 112-2.
And the phase deviation averaging circuits B1 to BS (82
-1 to 82-S), the time constant may be different.

In the fine adjustment circuit 1 (83-1), the frequency offset estimated values Δω (1) n and Δω (2) n
The frequency offset Δωn is calculated by the equation.

Δωn = MOD (Δω (1) n−Δω (2) n, 2π / M ₂ ) + Δω (1) n MOD (x, y) = mod (x + y / 2, y) −y / 2 ( 39) Here, mod (x, y) is a remainder operation, and MOD
(X, y) is a remainder operation in which the range of the remainder result is [−y / 2, y / 2).

FIG. 19 specifically shows the principle of the processing of equation (39). In the figure, 191 is the actual frequency offset (unknown on the receiving side), 192 is the estimated range of frequency offset Δω (1) n (M ₁ = 4), and 193 is the estimated range of frequency offset Δω (2) n (M ₂ = 8), 194 is a frequency offset Δω (1) n, 195 is Δω (1) n to Δω (2) n
196 is a frequency offset Δω (2) n, and 197 is an error component of Δω (2) n and a point projected to the estimated range of Δω (2) n. Is a fine adjustment component of the frequency offset Δω (1) n, and 199 is a fine adjustment result.

[0154] In the frequency offset estimation, as the value of M _i increases, the fluctuation of the phase deviation due to noise is suppressed strongly, the detection accuracy of the phase deviation is increased, and also impact on decision error and 1 / M _i Become. However, since the estimation range of the frequency offset is [−π / M _i , π / M _i ), the estimation range becomes narrow in inverse proportion to M _i .

Therefore, in the fine adjustment circuit 1 (83-1),
Phase deviation averaging circuits B1 and B2 (82-1, 82-2)
, A relatively wide frequency offset Δω
By calculating the remainder of the difference between (1) n and the frequency offset Δω (2) n with relatively high accuracy, the point when Δω (1) n is projected onto the estimation range of Δω (2) n and Δω ( 2) An error 197 of n is detected, and Δω (1) n is finely adjusted by this error (198).
Thus, a frequency offset (199) close to the actual frequency offset is estimated.

As described above, in the present embodiment,
Estimating a plurality of frequency offsets having different estimation accuracy and estimation ranges in parallel makes a wide estimation range and high-precision frequency offset estimation, and performs a correction for the frequency offset based on the estimation value to obtain a complex conjugate of a transmission path characteristic. Is multiplied by the received signal, thereby realizing wide-range, high-precision frequency offset removal.

In the above description, the phase deviation averaging circuits B1 to B1
The case where the time constants of the BSs (82-1 to 82-S) are all the same is shown, but the time constants are different values in the phase deviation averaging circuits B1 to BS (82-1 to 82-S). May be used.

Further, in the above description, a plurality of frequency offsets having different estimation accuracy and estimation range are estimated in parallel, and a wide range and high accuracy frequency offset estimation is realized from them. By performing the offset estimation in tandem, it is also possible to realize a wide range and highly accurate frequency offset estimation.

In the above description, the case where the input and estimation processing of the frequency offset estimating circuit is performed only by the phase has been described. However, as in the first embodiment, the input and estimation processing can be performed as complex numbers. Conversely, the estimation of the frequency offset in the first embodiment can be performed using only the phase as in the present embodiment.

In the above description, LMS is used for transmission path estimation.
Although the case where the algorithm is used has been described, the transmission path estimation may be performed by an adaptive algorithm such as the RLS algorithm. As described above, if the transmission channel estimation is performed successively using the adaptive algorithm, it is possible to follow the variation of the transmission channel characteristics even when the variation is high speed.

Although the case where the judgment value is used to calculate the phase deviation has been described, a known transmission signal may be used instead of the judgment value. Further, judgment value phase deviation detection circuits B1 to BS (92-92) when a known transmission signal is input in advance.
1 to 92-S) are stored in the table shown in FIG.
Judgment phase deviation detecting circuits B1 to BS (92-1)
To 92-S).

Further, by outputting the soft decision value, the bit error rate characteristics of the subsequent Viterbi decoder can be improved.

Embodiment 3 of the Invention Next, FIG. 13 is a configuration diagram of a receiver having an AFC function according to the third embodiment of the present invention. In the figure, the same or corresponding components as those of the first or second embodiment are denoted by the same reference numerals.

In FIG. 13, 11-1 to 11-N are reception signal input terminals, 133-1 to 133-N are complex conjugate circuits for calculating complex conjugates, and 134-1 to 134-N are complex conjugate circuits 133-133. The multiplication circuits 137 multiply the complex conjugate values output from 1 to N and the reception signals from the reception signal input terminals 11-1 to 11-N.
4-N an addition circuit for adding the multiplied values output by the output circuit; 15 a determination circuit that outputs a determination value that is an estimated value of transmitted data based on the added value output from the addition circuit 137;
136 is the judgment value and the reception signal input terminals 11-1 to 11-
A frequency offset estimating circuit C, 132 for estimating a frequency offset from the received signal from N and a frequency offset output from the frequency offset estimating circuit C136;
The judgment value output by the judgment circuit 15 and the reception signal input terminal 1
A transmission path estimating circuit that outputs transmission path characteristics corresponding to each reception signal from reception signals from 1-1 to 11-N.

FIG. 14 is a configuration diagram showing an example of the internal configuration of the frequency offset estimating circuit C136 in FIG.
In the figure, 11-1 to 11-N are reception signal input terminals, 17 is a judgment value input terminal, and 141 is a reception signal input terminal 11-1 to 11-N.
11-N reception signals from N and determination value input terminal 17
The phase deviation detecting circuits C and 142 for detecting the phase deviation occurring between the M symbols of the received signal according to the judgment value from the average of the phase deviation outputted from the phase detecting circuit C141 and outputting the frequency offset. Circuit A,
143 is a frequency offset output terminal.

FIG. 15 is a configuration diagram showing an example of the internal configuration of the phase deviation detection circuit C141 in FIG. In the figure, 11-1 to 11-N are reception signal input terminals, 17 is a judgment value input terminal, and 151-1 to 151-N are N system reception signals from the reception signal input terminals 11-1 to 11-N. Phase deviation of each received signal (M of the received signal expressed as a complex number)
Received signal phase deviation detection circuits A1 to AN (156) for detecting symbol delay detection results (complex numbers) are received signal phase deviation detection circuits A1 to AN (151-1 to 151-).
N), an addition circuit for adding the phase deviation of the N received signals output from the N received signals (a value obtained by displaying the complex symbol of the M symbol delay detection result of the received signal as a complex number), and 152 denotes a judgment value from the judgment value input terminal 17. A judgment value phase deviation detection circuit A 153 for detecting a phase deviation (a value obtained by expressing a phase deviation between M symbols of a judgment value in a complex number) is a judgment value phase deviation detection circuit A1.
A complex conjugate circuit that outputs a complex conjugate of a phase difference of the decision value output by 52 (a value representing the phase deviation between M symbols of the decision value in a complex number), 154 denotes an addition value output by the addition circuit 156, and a complex conjugate circuit A multiplication circuit 155 that performs multiplication with the complex conjugate value output from 153 is a phase deviation output terminal.

Next, the operation of the receiver according to the present embodiment will be described. Note that components denoted by the same reference numerals as those in Embodiment 1 perform the same operation. This embodiment is different from the first embodiment in that a determination value obtained from a diversity-combined signal is used to estimate transmission path characteristics corresponding to each received signal from N-system received signals, This is a portion for estimating the frequency offset from the N systems of received signals, and these portions will be mainly described.

In FIG. 13, complex conjugate circuit 133-1
１３133-N input the transmission path characteristics corresponding to the N-system received signals output from the transmission path estimation circuit 132, and output the complex conjugate values. Multiplication circuits 134-1 to 134-N
Are the complex conjugate values output from the complex conjugate circuits 133-1 to 133-N and the reception signal input terminals 11-1 to 11-N
And outputs the multiplied value with the received signal.

The adding circuit 137 includes multiplying circuits 133-1 to 133-1.
The N multiplied values output by 133-N are added. The determination circuit 15 determines a determination value that is an estimated value of the transmitted data from the addition result output from the addition circuit 137, and outputs the determination value from the determination value output terminal 17. The frequency offset estimating circuit C136 receives the judgment value output from the judging circuit 15 and the N received signals from the received signal input terminals 11-1 to 11-N, and outputs an estimated value of the frequency offset.

Further, in the transmission channel estimation circuit 132, the judgment value output by the judgment circuit 15 and the reception signal input terminal 11-
N-system received signals are input from 1 to 11-N, and estimated values of transmission path characteristics (N) for each of the received signals are output.

Next, the operation of the frequency offset estimating circuit C136 in FIG. 13 will be described with reference to FIG. In FIG. 14, a phase deviation detection circuit C141 includes reception signals from reception signal input terminals 11-1 to 11-N,
A decision value is inputted from a decision value input terminal 17, and a phase deviation occurring between M symbols is output. Phase deviation averaging circuit A1
Reference numeral 42 averages the phase deviation output from the phase deviation detection circuit C141, calculates the phase deviation per symbol, and outputs the result from the frequency offset output terminal 143 as an estimated value of the frequency offset.

Next, the phase deviation detection circuit C in FIG.
The operation of 141 will be described with reference to FIG. FIG.
5, the received signal phase deviation detection circuits A1 to AN (1
51-1 to 151-N) are reception signal input terminals 11-1.
11-N, and outputs a phase deviation of the received signal (a value obtained by displaying a complex symbol representing the result of the M symbol differential detection of the received signal as a complex number).

In addition circuit 156, phase deviations of N reception signals output from reception signal phase deviation detection circuits A1 to AN (151-1 to 151-N) (results of M symbol delay detection of reception signals represented by complex numbers). Is represented as a complex number) and the result of this addition is output.

The judgment value phase deviation detection circuit A152 inputs the judgment value from the judgment value input terminal 17, and converts the phase deviation of the judgment value (a value representing the phase deviation between M symbols of the judgment value in a complex number) into a complex conjugate circuit. 153.

The complex conjugate circuit 153 calculates the complex conjugate value of the phase deviation of the decision value output from the decision value phase deviation detection circuit A 152 (a value obtained by expressing the phase deviation between M symbols of the decision value in a complex number). Is output.

The multiplication circuit 154 includes a complex conjugate circuit 153
Is multiplied by the complex conjugate value output by the adder 156 and the addition result output by the adder circuit 156, and the result is calculated as the phase deviation (M symbol differential detection result of the received signal represented by a complex number is used as the determination value between M symbols). The result corrected by the phase deviation is output from the phase deviation output terminal 155 as a complex value).

The operation of the present embodiment described above will be described more specifically (qualitatively). In FIG. 13, time n
, R (N) n, and the estimated tap coefficient of the transmission line for the N received signals is g (1).
n, ..., g (N) n. The addition circuit 137 calculates the addition value of the equation (40).

[0178]

(Equation 4) Here, for example, assuming that the transmission modulation signal is a four-phase PSK, the determination circuit 15 sets the determination value Jn to exp (jπ / 4) when the added value is in the first quadrant on the complex plane, and is in the second quadrant. Exp (j3π / 4) when in the third quadrant, exp (j5π / 4), and in the fourth quadrant exp (j
7π / 4). In this case, not only the hard decision value but also the above-described soft decision value can be output as the decision value at this time. When the output of the soft decision value is required, an addition value as shown in, for example, Expression (40) is output.

Next, the transmission path estimation circuit 132 uses the judgment value Jn and the frequency offset estimation value Δωn output from the frequency offset estimation circuit C136 to divide the transmission path characteristic estimation value into each of the N systems of received signals. Calculated for Here, the case where the LMS algorithm is used will be described. The transmission path estimating circuit 132 calculates the estimated tap coefficients for each of the N systems of received signals by using equation (41) using the above determination value Jn.

G (p) n + 1 = ｛g (p) n + δ (r (p) n−g (p) nJn) Jn ^* ｝ exp (jΔωn) (p = 1,..., N) 41) The expression in parentheses in equation (41) is the update of the tap coefficient g (p) n based on the LMS algorithm, and exp (j Δωn
) Is a term for correcting the phase rotation component due to the frequency offset.

Next, the frequency offset estimating circuit C136
An example of the internal operation in will be specifically described with reference to FIG. In addition, about the phase deviation averaging circuit A142,
Since it is the same as the first embodiment, the phase deviation detection circuit C1
Only 41 will be described.

The phase deviation detecting circuit C141 calculates the phase deviation occurring between the M symbols by the equation (42) using the N-system received signals r (p) n and the above-mentioned judgment value Jn.

[0183]

(Equation 5) As described above, in the present embodiment, diversity combining is performed from transmission path characteristics and received signals for each received signal, and a determination value that is an estimated value of data transmitted using the result is output. From the decision value using the diversity combining result and the received signal for each antenna, the characteristics of the transmission path for each antenna are estimated, and this estimated value is used as the transmission path characteristic for each received signal, and its complex conjugate and reception By performing diversity combining in the form of multiplying signals and taking the sum, it is possible to realize maximum ratio combining diversity. Further, by estimating the frequency offset from the N received signals and the determination value and rotating the phase of the transmission path characteristic by the frequency offset, the bit error rate characteristic in the presence of the frequency offset can be improved.

Also, according to the present embodiment, diversity combining is performed using transmission path characteristics that can express carrier phase and envelope amplitude for each received signal in a unified manner, and a decision is made using the result of the diversity combining. By estimating the transmission path characteristics using the values, there is phase uncertainty in the judgment value output, but since there is no relative phase error in the transmission path characteristics for the N-system received signals, external Without entering information to remove relative phase errors,
A maximum ratio combining diversity receiver can be provided stably, and as a result, the bit error rate characteristics can be improved.

In the above description, the case where the LMS algorithm is used for the transmission path estimation has been described. However, the transmission path estimation may be performed by an adaptive algorithm such as the RLS algorithm. Using an adaptive algorithm like this,
By performing the successive transmission path estimation, it is possible to follow the fluctuation of the transmission path characteristics even when the fluctuation is high.

In the above description, the case where the judgment value is used to calculate the phase deviation has been described, but a known transmission signal may be used instead of the judgment value. Further, a determination value phase deviation detection circuit A15 when a known transmission signal is input in advance.
2 may be used in place of the determination value phase deviation detection circuit A152 in FIG.

Further, as in the second embodiment, it is possible to perform the processing of the frequency offset estimating circuit C using only the phase information. Further, a plurality of frequency offsets are estimated, and the fine adjustment of the frequency offset is performed based on the result. By doing
It is possible to realize frequency offset estimation with a wide estimation range and high accuracy.

Embodiment 4 of the Invention Next, FIG. 16 is a configuration diagram of a receiver having an AFC function according to Embodiment 4 of the present invention. In the figure, the same or equivalent components as those of the third embodiment are denoted by the same reference numerals.

In FIG. 16, reference numerals 11-1 to 11-N denote received signal input terminals, reference numerals 133-1 to 133-N denote complex conjugate circuits for calculating complex conjugate values, and reference numerals 134-1 to 134-N denote complex conjugate circuits 133. 137 are multiplication circuits for multiplying the complex conjugate values output from the reception signal input terminals 11-1 to 11-N by the reception signals from the reception signal input terminals 11-1 to 11-N.
An adder circuit for adding the multiplied values output from 4-1 to 134-N; a determination circuit 15 for outputting a determination value that is an estimated value of transmitted data based on the added value output from the addition circuit 137; 166 is the judgment value, the reception signal input terminal 11
-1 to 11-N, and transmission channel estimation circuit 1
The frequency offset estimating circuits D and 132 for estimating the frequency offset from the transmission path characteristics output by the frequency output circuit 32 output the frequency offset output from the frequency offset estimating circuit D166, the determination value output by the determination circuit 15, and the received signal input terminal 11 A transmission path estimation circuit that outputs transmission path characteristics corresponding to each reception signal from reception signals from -1 to 11-N.

FIG. 17 is a configuration diagram showing an example of the internal configuration of the frequency offset estimation circuit D166 in FIG.
In the figure, 11-1 to 11-N are reception signal input terminals, and 171
-1 to 171-N are transmission path characteristic input terminals, 17 is a judgment value input terminal, 172-1 to 172-N are N-system reception signals from the reception signal input terminals 11-1 to 11-N, and transmission path A reception signal phase error detection circuit for detecting a phase error of a reception signal based on N transmission line characteristics from the characteristic input terminals 171-1 to 171-N and a judgment value from the judgment value input terminal 17, and 173 indicates a reception signal. Phase error detection circuit 172-1
Addition circuits A and 174 for adding N phase errors output from .about.172-N calculate an arc tangent value of an addition value output from the addition circuit A173, and 175 output from an arctangent circuit 174. Inverse tangent value and the delay circuit 17
7 is an averaging circuit for averaging the addition value output from the addition circuit B175, 177 is a delay circuit for delaying one symbol, and 178 is a frequency offset output. Terminal.

FIG. 18 is a configuration diagram showing an example of the internal configuration of the reception signal phase error detection circuit 172-1 in FIG. In the figure, reference numeral 11-1 denotes a reception signal input terminal;
-1 is a transmission line characteristic input terminal, 17 is a judgment value input terminal, 1
81-1 is a multiplication circuit A for calculating a multiplication value of the transmission line characteristic from the transmission line characteristic input terminal 171-1 and the judgment value from the judgment value input terminal 17, and 182-1 is a multiplication circuit 181-1.
183-1 is a complex conjugate circuit that calculates a complex conjugate value of the multiplied value output from the multiplexing circuit 183-1, and multiplies the complex conjugate value output from the complex conjugate circuit 182-1 by the reception signal from the reception signal input terminal 11-1. A multiplication circuit B for calculating the value, 184-1 is a reception signal phase error output terminal.

Next, the operation of the receiver according to the present embodiment will be described. Note that the same operations as those of the third embodiment are denoted by the same reference numerals. The operation of the present embodiment is the same as that of the third embodiment except for the operation of estimating the frequency offset. Therefore, only the part for estimating the frequency offset will be described.

First, the operation of the frequency offset estimating circuit D166 in FIG. 16 will be described using the configuration example in FIG. Received signal phase error detection circuit 172-1 to 17-1
72-N is an N-system reception signal from the reception signal input terminals 11-1 to 11-N, a transmission line characteristic input terminal 171-1 to 17-N.
The transmission path characteristics of the N systems from 171-N and the judgment value from the judgment value input terminal 17 are input, the phase error of each received signal is detected, and the result is output.

The addition circuit A 173 adds N phase errors output from the reception signal phase error detection circuits 172-1 to 172-N, and outputs the added value to the arc tangent circuit 174. The arc tangent circuit 174 calculates the arc tangent value of the added value output from the addition circuit A 173, and outputs the calculated arc tangent value to the addition circuit B 175.

In the adder circuit B175, the arc tangent circuit 174
Is added to the delay signal output from the delay circuit 177, and the added value is output to the averaging circuit 176. The averaging circuit 176 averages the added value output from the adding circuit B175, and uses the averaged result as an estimated value of the frequency offset.
Output from 78. The delay circuit 177 includes an averaging circuit 176
Are delayed by one symbol and output to the adder circuit B175.

Next, the operation of the received signal phase error detection circuit 172-1 in FIG. 17 will be described using the configuration example of FIG. The multiplication circuit A181-1 calculates a multiplication value of the transmission path characteristic from the transmission path characteristic input terminal 171-1 and the judgment value from the judgment value input terminal 17, and outputs the result to the complex conjugate circuit 182-1.

In complex conjugate circuit 182-1, multiplication circuit A
The complex conjugate value of the output from 181-1 is calculated, and the complex conjugate value is output to the multiplication circuit B183-1. Multiplication circuit B
In 183-1, a multiplication value of the complex conjugate value output from the complex conjugate circuit 182-1 and the reception signal from the reception signal input terminal 11-1 is calculated, and the multiplication value is received as a phase error of the reception signal. The signal is output from the signal phase error output terminal 184-1.

The operation of the present embodiment described above will be described more specifically. In FIG. 17, N at time n
, R (N) n, and the estimated tap coefficients of the transmission path for the N systems of received signals are g (1) n,.
(N) n, and the judgment value is Jn. The adder A173 outputs (4
3) Calculate the added value of the equation.

[0199]

(Equation 6) Equation (43) is obtained by combining the phase error between the received signal and the estimated received signal by the maximum ratio, and the added value output from the adding circuit B175 becomes equation (44), which is detected at time n. Frequency offset.

Δω′n = εn + Δωn−1 (44) Finally, Δω′n is averaged by the averaging circuit 176 as in the second embodiment.

As described above, in the present embodiment, diversity combining is performed from the transmission path characteristics and the received signal for each of the received signals, and the determination value, which is the estimated value of the data transmitted using the result, is determined. Output and estimate the characteristics of the transmission path for each received signal from the decision value using the diversity combining result and each received signal, and use this estimated value as the transmission path characteristic for each received signal and its complex conjugate. By performing diversity combining by multiplying the received signals and taking the sum, it is possible to realize maximum ratio combining diversity. Further, a frequency offset is estimated from the N received signals, the transmission path characteristics corresponding to the N reception signals, and the determination value, and the phase offset of the transmission path characteristics is performed by using the frequency offset. Can be improved.

Further, according to the present embodiment, diversity combining is performed using transmission path characteristics that can express carrier phase and envelope amplitude for each received signal in a unified manner, and a decision value using the result of the diversity combining is obtained. , The phase uncertainty exists in the judgment value output, but there is no relative phase error in the transmission path characteristics for the N-system received signals. A maximum ratio combining diversity receiver can be provided stably without inputting information for removing a phase error, and as a result, a bit error rate characteristic can be improved.

In the above description, the case where the LMS algorithm is used for transmission path estimation has been described. However, the transmission path estimation may be performed using an adaptive algorithm such as the RLS algorithm. As described above, if the transmission channel estimation is performed successively using the adaptive algorithm, it is possible to follow the variation of the transmission channel characteristics even when the variation is high speed.

In the above description, the case where the judgment value is used to calculate the phase deviation has been described, but a known transmission signal may be used instead of the judgment value. Further, as in the second embodiment, it is possible to perform the processing of the frequency offset estimating circuit C using only the phase information, and to estimate a plurality of frequency offsets and finely adjust the frequency offset from the result. As a result, highly accurate frequency offset estimation with a wide estimation range can be realized.

Further, by outputting the soft decision value, the bit error rate characteristics of the subsequent Viterbi decoder can be improved.

Embodiment 5 of the Invention FIG. 25 is a configuration diagram of a frequency offset estimating circuit in a receiver having an AFC function according to Embodiment 5 of the present invention. Note that AF
The configuration of the receiver having the C function is basically the same as that of the second embodiment.
7 is the same as FIG.

In FIG. 25, reference numeral 303 denotes a multiplication circuit;
6 is a frequency offset estimating circuit as shown in FIG. 8, for example, 305 is a frequency dividing circuit for inputting the output frequency offset and removing the influence of multiplication, and 317 is a fixed data input terminal and is a judgment value output in FIG. It corresponds to the terminal 17. Reference numeral 11 corresponds to the reception signal input terminal 11 in FIG. Reference numeral 307 denotes a frequency offset output terminal.

Next, the operation of the receiver according to the present embodiment will be described. For example, if the modulation signal is four-phase PSK, the multiplication circuit 303 multiplies the reception signal by four to remove the modulation component. Next, the frequency offset estimating circuit 376 calculates
For example, the frequency offset in the quadrupled reception signal is estimated according to the operation described in the second embodiment. At this time, since the modulation component has been removed, there is no need to input a judgment value or known transmission data from outside, and it is sufficient to assume fixed transmission data. By using this assumption, for example, the determination value phase deviation detection circuit B1 (92-1) in FIG. 9 can be eliminated. The frequency dividing circuit 305 receives the estimated value of the frequency offset in the quadrupled signal, removes the influence of the multiplication, and outputs the frequency offset as the divided value.

As described above, the receiver according to the fifth embodiment eliminates the need to externally input a judgment value or known transmission data by removing the modulation signal by multiplying the reception signal.

That is, in the present embodiment, a fixed value is used instead of the decision value used for estimating the frequency offset or the known transmission data as in the above embodiments, so that the configuration of the receiver is simplified. Can be

[0211] The receiver according to the present invention can be implemented not only in the embodiments described above, but also by combining or replacing the components of the embodiments.

[0212]

As described above, according to the first aspect of the present invention,
According to the receiver according to the above, the received signal correction means corrects the phase and / or amplitude of the input received signal based on the input transmission path characteristics, and the determination means inputs the corrected received signal and transmits A judgment value that is an estimated value of the obtained data is output. Further, the transmission path estimating means determines the frequency offset, the carrier phase, and the amplitude based on the determination value output from the determining means or the known transmission data, the input frequency offset, and the input received signal. The determined transmission path characteristics are estimated and output to the received signal correction means, and the S frequency offset estimating means inputs a judgment value or known transmission data and an input reception signal, and outputs a current judgment value or a known judgment value. And the Mi symbol (i is 1 to
S: S is an integer of 2 or more, and Mi is 1 different from each other
The i-th frequency offset is estimated based on the past decision value or known transmission data by the above integer), the present reception signal, and the reception signal only by the Mi symbol in the past. Since the finely adjusted frequency offset is calculated based on the S i-th frequency offsets output from the offset estimating means, and the finely adjusted frequency offset is output to the transmission path estimating means, high precision is achieved. And frequency offset estimation in a wide estimation range.

Further, according to the receiver according to the second aspect of the present invention, the received signal correcting means corrects the phase and / or the amplitude of the input received signal based on the characteristics of the input transmission path,
The corrected reception signal is output, the determination means receives the corrected reception signal, outputs a determination value that is an estimated value of the transmitted data, and the transmission path estimation means outputs the determination value. Based on the judgment value or the previously known transmission data, the input frequency offset, and the input reception signal,
The transmission path characteristics determined by the frequency offset, the carrier phase, and the amplitude are estimated and output to the reception signal correction unit, and the frequency offset estimation unit of the first stage detects the judgment value or the known transmission data and the input reception signal. enter the door, and the current decision value or known transmitted data, M ₁ symbol (M ₁ is an integer of 1 or more) by a past decision value or known transmit data, and the current reception signal, M ₁ symbols The frequency offset is estimated based on the received signal only in the past, and the S-1 frequency offset estimating means connected stepwise after the first-stage frequency offset estimating means respectively determines the determination value or the known value. The transmission data, the input reception signal, and the frequency offset output by the frequency offset estimating means at the preceding stage are input, and the current determination value, Mi + 1
Symbol (i = 1~S-1; S is an integer of 2 or more; M ₁ and Mi + 1 is different from an integer of 1 or more with each other) and past decision value or known transmit data only, and the current reception signal,
The frequency offset finely adjusted is estimated based on the received signal of Mi + 1 symbols in the past, and the frequency offset estimated by the frequency offset estimating means of the S-th stage, which is the final stage, is output to the transmission path estimating means. I have to. Thereby, highly accurate frequency offset estimation in a wide estimation range can be realized.

According to the receiver of claim 3 of the present invention, each of the S frequency offset estimating means inputs the received signal, and outputs a current received signal and a Mi symbol (i = 1 To S; S is an integer of 2 or more), the frequency offset is estimated based on the received signal in the past and the known information about the transmitted signal, so that the frequency offset can be corrected with high accuracy without being affected by the determination error. Can be realized.

According to the receiver of claim 4 of the present invention, the phase deviation detecting means of the S frequency offset estimating means inputs the judgment value or known transmission data and the received signal. Then, respectively, the present judgment value or known transmission data, the judgment value or known transmission data past by Mi symbols (i = 1 to S; S is an integer of 2 or more), the current reception signal, and Mi Based on the previous received signal only for the symbol, the phase deviation occurring between the Mi symbols is detected, and the phase deviation averaging means averages the phase deviation outputted from the phase deviation detecting means, and outputs the frequency offset. As a result, the time constant of averaging can be made smaller than in the past, and the effect of a decision error becomes 1 / Mi of the past, so that a frequency offset estimation with high accuracy and fast convergence can be realized. You.

Further, according to the receiver according to claim 5 of the present invention, the synthesizing means converts the received N systems (N is an integer of 1 or more) of input reception signals into N transmission paths, respectively. Correcting based on the characteristics, outputting a synthesized signal obtained by synthesizing them, determining means inputting the synthesized signal, outputting a judgment value which is an estimated value of transmitted data, and transmitting path estimating means, A determination value or known transmission data, a frequency offset to be input, and an N-system input reception signal output from the means, and N-system transmission path characteristics for each of the N-system input reception signals , And outputs them to the synthesizing unit. The S frequency offset estimating units determine whether the judgment value or the known transmission data and the Mi symbol (i is 1 to S; S is an integer of 2 or more; Each Mi is different (The above integer), based on the past judgment value or known transmission data, the current N received input signals, and the N received input signals of the N symbols past the Mi symbol, based on the N received input signals. The i frequency offset is estimated, and the fine adjustment means inputs the S frequency offsets output from the S frequency offset estimating means, finely adjusts the frequency offset for channel estimation, and performs the fine adjustment. The frequency offset is output to the transmission path estimating means, so that the maximum ratio combining diversity can be realized, the frequency offset can be corrected, and the frequency offset can be estimated with high accuracy and in a wide estimation range.

Further, according to the receiver according to claim 6 of the present invention, the received N-system (N is an integer equal to or greater than 1) input received signal is converted based on N input channel characteristics. Correcting means for outputting a synthesized signal obtained by synthesizing them, judgment means for inputting the synthesized signal and outputting a judgment value which is an estimated value of transmitted data, and judgment value outputted from the judgment means Or input known transmission data, a frequency offset, and the received signals of the N systems,
A transmission path estimating means for estimating N transmission path characteristics for each of the N reception signals and outputting them to the synthesizing means; the determination value or known transmission data and the N reception reception signals; type and a current determination value or known transmitted data, M ₁ symbol (M ₁ is an integer of 1 or more) and only past decision value or known transmit data, an input reception signal of the current N systems, M _First- stage frequency estimating means for estimating a frequency offset based on N symbols of input reception signals in the past by _one symbol, and a plurality of frequencies connected stepwise following the first-stage frequency offset estimating means Offset estimating means, the determination value or known transmission data, the N-system input reception signal,
Inputs the frequency offset output from the previous stage of the frequency offset estimating means, and the current determination value, Mi + 1 symbols (i = 1~S-1; S is an integer of 2 or more; M ₁ and Mi + 1
Is an integer of 1 or more different from each other), or a past determination value or known transmission data, a current N input reception signals,
Frequency offset estimating means from the second stage to the S-1th stage for estimating the finely adjusted frequency offset based on the past N received input signals by Mi + 1 symbols, The N frequency offsets estimated by the frequency offset estimating means at the stage are output to the transmission path estimating means, and a plurality of frequency offsets having different precisions and estimation ranges are estimated. Frequency offset estimation with a wide estimation range can be realized.

Further, according to the receiver according to claim 7 of the present invention, the S frequency offset units each include:
The input reception signals of the N systems are input, and N input reception signals of the current N systems and N symbols of the past N symbols (i = 1 to S; S is an integer of 2 or more; Mi is an integer of 1 or more different from each other). The frequency offset is estimated based on the input received signal of the system and the known information on the transmission signal, and the maximum ratio combining diversity and the correction of the frequency offset are realized with high accuracy without being affected by the determination error. be able to.

[0219] According to the receiver according to claim 8 of the present invention, the phase deviation detecting means of the S frequency offset estimating means includes the judgment value or the known transmission data and the input and reception of the N systems. A signal is input, and the current judgment value or known transmission data and the Mi symbol (i = 1 to S; S
Is an integer of 2 or more; Mi is an integer of 1 or more different from each other) and the past determination value or known transmission data, the current N input reception signals, and the N symbol past N input reception signals by Mi symbols. The phase deviation averaging means detects the phase deviation occurring between the Mi symbols, and outputs the frequency offset. The time constant of the averaging can be reduced as compared with the conventional technique. Since the effect of the error is 1 / Mi compared to the conventional case, it is possible to realize frequency offset estimation with high accuracy and fast convergence.

According to the receiver of the ninth aspect of the present invention, the phase deviation detecting means outputs a phase deviation represented by a complex number, and the polar coordinate conversion means of the phase deviation averaging means outputs the phase deviation. Upon receiving the input of the complex-valued phase deviation generated between the Mi symbols output by the detection means, the complex-valued phase deviation is converted into polar coordinates, and the phase component is output. The phase component to be output is input, and the phase deviation per symbol is estimated. If the cosine value of the phase deviation is a real part and the sine value is an imaginary part, for example, the complex tangent of the phase deviation is calculated. Is performed after averaging, and a phase jump can be prevented.

According to the receiver of the present invention, the phase deviation detecting means outputs a phase deviation represented by a complex number, and the averaging means of the phase deviation averaging means comprises:
The phase deviation of the complex number generated between the Mi symbols output by the phase deviation detecting means is input, the phase deviation of the complex number is averaged, and the polar coordinate conversion means inputs the complex displayed phase deviation output by the averaging means. Then, the phase component obtained by converting to polar coordinates is output, the dividing means inputs the phase component output by the polar coordinate converting means, calculates the phase deviation per symbol, and displays the complex number representation of the phase deviation. For example, when the cosine value of the phase deviation is a real part and the sine value is an imaginary part, averaging is performed after the arc tangent calculation, so that the averaging process can be simplified, and the calculation accuracy of the arc tangent is not sufficient. Even in this case, it is possible to improve the accuracy deterioration due to arctangent processing.

According to the receiver according to the eleventh aspect of the present invention, it is not necessary to use a decision value or known transmission data in frequency offset estimation by removing a modulation component from a received signal by a multiplication process. This has the effect.

[0223]

[0224]

[0225]

[0226]

[0227]

[0228]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a receiver having an AFC function according to Embodiment 1 of the present invention.

FIG. 2 is a configuration diagram of the inside of a frequency offset estimation circuit A in FIG. 1;

FIG. 3 is a configuration diagram illustrating an example of an internal configuration of a phase deviation detection circuit A in FIG. 2;

4 is a configuration diagram showing an example of an internal configuration of a reception signal phase deviation detection circuit A in FIG.

FIG. 5 is a configuration diagram showing an example of an internal configuration of a phase deviation averaging circuit A in FIG. 2;

6 is a configuration diagram showing another example of the configuration inside the phase deviation averaging circuit A in FIG. 2;

FIG. 7 is a configuration diagram of a receiver having an AFC function according to a second embodiment of the present invention.

8 is a configuration diagram illustrating an internal configuration of a frequency offset estimation circuit B in FIG. 7;

9 is a configuration diagram illustrating an example of an internal configuration of a phase deviation detection circuit B1 in FIG.

10 is a reception signal phase deviation detection circuit B in FIG. 9;
FIG. 2 is a configuration diagram illustrating an example of an internal configuration of the first embodiment;

11 is a configuration diagram illustrating an example of an internal configuration of a phase deviation averaging circuit B1 in FIG. 8;

12 is a configuration diagram illustrating an example of an internal configuration of the fine adjustment circuit 1 in FIG.

FIG. 13 is a configuration diagram of a receiver having an AFC function according to a third embodiment of the present invention.

14 is a configuration diagram showing an example of an internal configuration of a frequency offset estimation circuit C in FIG.

15 is a configuration diagram illustrating an example of an internal configuration of a phase deviation detection circuit C in FIG. 14;

FIG. 16 is a configuration diagram of a receiver having an AFC function according to Embodiment 4 of the present invention.

17 is a configuration diagram illustrating an example of an internal configuration of a frequency offset estimation circuit D in FIG. 16;

18 is a configuration diagram illustrating an example of an internal configuration of a reception signal phase error detection circuit in FIG.

FIG. 19 is a diagram illustrating the principle of a fine adjustment circuit.

FIG. 20 is a configuration diagram of a conventional carrier phase synchronization circuit.

FIG. 21 is a configuration diagram of a conventional diversity receiver.

FIG. 22 is a configuration diagram of a receiver having an AFC function of Conventional Example 1.

FIG. 23 is a configuration diagram of a receiver having an AFC function according to Conventional Example 2.

FIG. 24 is a configuration diagram of a receiver having diversity of the third conventional example.

FIG. 25 is a configuration diagram of a frequency offset estimating circuit in a receiver having an AFC function according to Embodiment 5 of the present invention.

[Explanation of symbols]

11 reception signal input terminal, 11-1 to 11-N reception signal input terminal, 12 transmission line estimation circuit, 13 complex conjugate circuit, 14 multiplication circuit, 15 judgment circuit, 16 frequency offset estimation circuit A, 17 judgment value output terminal, 17 judgment value output terminal (input terminal), 21 phase deviation detection circuit A,
22 phase deviation averaging circuit A, 23 frequency offset output terminal, 31 received signal phase deviation detection circuit A, 32 judgment value phase deviation detection circuit A, 33 complex conjugate circuit, 34
Multiplication circuit, 35 phase deviation output terminal, 41 M symbol delay circuit, 42 complex conjugate circuit, 43 multiplication circuit, 44
Received signal phase deviation output terminal, 51 Arc tangent circuit, 52
Dividing circuit, 53 averaging circuit, 61 averaging circuit, 62 arc tangent circuit, 63 dividing circuit, 76 frequency offset estimating circuit B, 77 arc tangent circuit, 81-1 to 81-S Phase deviation detecting circuit B, 82-1 to 82 -S phase deviation averaging circuit B, 83-1 to 83-S-1 fine adjustment circuit, 91-
1-91-S Received signal phase deviation detection circuit B, 92-1
９２92-S Judgment value phase deviation detection circuit B, 93-1 subtraction circuit, 94-1 phase deviation output terminal (input terminal), 1
_{01-1~101-S M 1, M 2} , ..., M S -symbol delay circuit, 102-1 subtraction circuit, 103-1 received signal phase difference output terminal, 111-1 to 111-S dividing circuit, 112-1 Averaging circuit, 113-1 frequency offset output terminal (frequency offset input terminal A), 113
-2 frequency offset input terminal B, 121-1 subtraction circuit, 122-1 remainder circuit, 123-1 addition circuit, 1
24-1 frequency offset output terminal, 132 transmission line estimation circuit, 133-1 to 133-N complex conjugate circuit,
34-1 to 134-N Multiplication circuit, 136 Frequency offset estimation circuit C, 137 addition circuit, 141 Phase deviation detection circuit C, 142 Phase deviation averaging circuit A, 143
Frequency offset output terminal, 151-1 to 151-N
Received signal phase deviation detection circuit A, 152 Judgment value phase deviation detection circuit A, 153 Complex conjugate circuit, 154 Multiplication circuit, 156 Addition circuit, 166 Frequency offset estimation circuit D, 171-1 to 171-N Transmission path characteristic input terminal, 172-1 to 172-N Received signal phase error detection circuit, 173 addition circuit A, 174 arctangent circuit, 175
Adder circuit B, 176 average circuit, 177 delay circuit, 1
78 frequency offset output terminal, 181-1 to 181
-N multiplication circuit A, 182-1 to 182-N complex conjugate circuit, 183-1 to 183-N multiplication circuit B, 184-
1-184-N Received signal phase error output terminal, 191
Actual frequency offset, 192 Frequency offset Δ
ω (1) n estimation range, 193 frequency offset Δω (2) n estimation range, 194 frequency offset Δω (1) n, 195
Frequency offset Δω (1) n is converted to frequency offset Δω
(2) The point projected to the estimation range of n, 196 The frequency offset Δω (2) n, 197 The point projected to the estimation range of the frequency offset Δω (1) n and the frequency offset Δω (2 ) n error component, 198 fine adjustment component of frequency offset Δω (1) n, 199 fine adjustment result, 20
1 reception signal input terminal, 202 phase synchronization information input terminal, 203 multiplication circuit, 204 averaging circuit, 205 frequency divider circuit, 206 phase uncertainty elimination circuit, 207 phase information output terminal, 211-1 to 211-N reception signal input Terminal, 212-1 to 212-N phase synchronization information input terminal,
213-1 to 213-N envelope detection circuit, 214-1 to 213-N
214-N phase shift circuit, 215-1 to 215-N phase detection circuit, 216-1 to 216-N amplifier circuit, 217
Addition circuit, 218 judgment circuit, 219 judgment value output terminal, 220 reception signal input terminal, 221 arctangent circuit, 2
22 delay circuit, 223 subtraction circuit, 224 addition circuit, 225 judgment circuit, 226 subtraction circuit, 227 average circuit, 228 judgment value output terminal, 231 reception signal input terminal, 232 delay circuit, 233 multiplication circuit A, 234
Low-pass filter, 235 L multiplying circuit, 236 averaging circuit, 237 L frequency dividing circuit, 238 complex conjugate circuit, 23
9 Multiplication circuit B, 2310 judgment circuit, 2311 judgment value output terminal, 241-1, 241-2 reception wave input terminal,
242-1, 222-2 Oscillation circuit A, 243-1, 241-2
43-2 Multiplier A, 244-1, 244-2 Band Filter A, 245 Adder, 246 Band Filter B, 247 Delay, 248 Multiplier B, 249
Band filter C, 2410 synthesized signal output terminal, 303
Multiplying circuit, 305, frequency dividing circuit, 307 output terminal, 317 fixed data input terminal, 376 frequency offset estimating circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-252966 (JP, A) JP-A-5-110617 (JP, A) JP-A-7-235917 (JP, A) JP-A-7-205 66842 (JP, A) JP-A-8-56244 (JP, A) JP-A-5-207088 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27 / 38 H04B 1/10 H04B 7/26 H04L 1/06

Claims (11)

(57) [Claims] 1. The phase and / or amplitude of an input received signal,
Received signal correction means for correcting based on the input transmission path characteristics and outputting the corrected received signal, and inputting the corrected received signal and outputting a judgment value which is an estimated value of transmitted data Determining means, based on a determination value output from the determining means or previously known transmission data, an input frequency offset, and the input received signal, determined by the frequency offset, the carrier phase, and the amplitude. A transmission path estimating means for estimating the transmission path characteristic and outputting the same to the received signal correcting means; and inputting the judgment value or the known transmission data and the input reception signal to obtain a current judgment value or the known transmission data. When,
Mi symbol (i is 1 to S; S is an integer of 2 or more,
Mi is one or more integers different from each other) S frequency offsets for estimating the i-th frequency offset based on the past determination value or known transmission data by the present reception signal and the reception signal by the Mi symbol in the past Estimating means, calculating a finely adjusted frequency offset based on the S i-th frequency offsets output by the S frequency offset estimating means, and transmitting the finely adjusted frequency offset to the transmission path estimating means. A fine adjustment means for outputting, and a receiver. 2. The phase and / or amplitude of an input received signal,
Received signal correction means for correcting based on the input transmission path characteristics and outputting the corrected received signal, and inputting the corrected received signal and outputting a judgment value which is an estimated value of transmitted data Determining means, based on a determination value output from the determining means or previously known transmission data, an input frequency offset, and the input received signal, determined by the frequency offset, the carrier phase, and the amplitude. Estimate the transmission path characteristics
A transmission path estimating means for outputting it to the received signal correcting means, and inputting the judgment value or known transmission data and the input reception signal, and a current judgment value or known transmission data,
M ₁ symbol (M ₁ is an integer of 1 or more) and only past decision value or known transmit data, and the current reception signal, M ₁
A first-stage frequency offset estimating unit for estimating a frequency offset based on a received signal of only a symbol in the past, and a plurality of frequency offset estimating units connected stepwise following the first-stage frequency offset estimating unit. Inputting the judgment value or known transmission data, the input received signal, and the frequency offset output by the frequency offset estimating means in the preceding stage, and inputting the current judgment value and Mi + 1
Symbol (i = 1~S-1; S is an integer of 2 or more; M ₁ and Mi + 1 is different from an integer of 1 or more with each other) and past decision value or known transmit data only, and the current reception signal,
A frequency offset estimating means from a second stage to an S-th stage for estimating a fine-tuned frequency offset based on a received signal in the past by Mi + 1 symbols, and the S-stage frequency offset estimating device The frequency offset estimated by the above is output to the transmission path estimating means. 3. The S number of frequency offset estimating units each receive the received signal and receive a current received signal and a previous received symbol by Mi symbols (i = 1 to S; S is an integer of 2 or more). The receiver according to claim 1, wherein the frequency offset is estimated based on the signal and known information about the transmission signal. 4. The S frequency offset estimating means inputs the judgment value or known transmission data and the received signal, and respectively receives a current judgment value or known transmission data and a Mi symbol (i = 1 to S; S is an integer of 2 or more), and detects a phase deviation occurring between Mi symbols based on a past determination value or known transmission data, a current reception signal, and a reception signal only Mi symbols in the past. Phase deviation detecting means, and averaging the phase deviation outputted by the phase deviation detecting means,
The receiver according to claim 1, further comprising: a phase deviation averaging unit that outputs a frequency offset. 5. A synthesizing means for correcting received N input signals (N is an integer of 1 or more) based on N input channel characteristics, and outputting a synthesized signal obtained by synthesizing them. And a determination unit that receives the synthesized signal and outputs a determination value that is an estimated value of the transmitted data; a determination value output from the determination unit or previously known transmission data; and an input frequency offset. Transmission line estimation means for receiving the N input reception signals, estimating N transmission line characteristics for each of the N input reception signals, and outputting them to the synthesizing means; Alternatively, the known transmission data and the determined symbol or known transmission data by the Mi symbol (i is 1 to S; S is an integer of 2 or more, and each Mi is an integer of 1 or more different from each other) and the current N Entering the system S frequency offset estimating means for estimating the i-th frequency offset of the N-system input received signal based on the received signal and the N-system input received signals in the past by Mi symbols, and the S frequency-offset estimation Fine adjustment means for inputting the S frequency offsets output by the means, finely adjusting the frequency offset for transmission path estimation, and outputting the finely adjusted frequency offset to the transmission path estimation means. Receiver. 6. A synthesizing means for correcting N received (N is an integer of 1 or more) input received signals based on N input channel characteristics and outputting a synthesized signal obtained by synthesizing them. A determination unit that receives the combined signal and outputs a determination value that is an estimated value of transmitted data; a determination value output from the determination unit or transmission data that is known in advance; a frequency offset; A transmission line estimating means for receiving the N-system reception signals, estimating N-system transmission path characteristics for each of the N-system reception signals, and outputting them to the synthesizing means; and the determination value or the known transmission data. and the inputs the input reception signal of N lines, and current determination value or known transmitted data, M ₁ symbol (M ₁ is an integer of 1 or more) and only past decision value or known transmit data, the current N An input reception signal of integration, based on the input received signal of the past N systems by M ₁ symbols, a frequency estimation unit of the first stage of estimating the frequency offset, following the frequency offset estimating means of the first stage stage A plurality of frequency offset estimating means connected in series, the determination value or known transmission data, the input reception signals of the N systems, and the frequency offset output by the frequency offset estimating means of the previous stage is input, the current determination value, Mi + 1 symbols (i = 1~S-1; S is an integer of 2 or more; M ₁ and Mi + 1 is different an integer of 1 or more) by a past decision value or known transmit data And a frequency from the second stage to the S-1 stage for estimating a finely adjusted frequency offset based on the current N input received signals and the N previously received input signals of Mi + 1 symbols. Oh Sets and estimation means, having a receiver frequency offset of said N lines frequency offset estimation means has estimated the second S stage is characterized in that it is output to the channel estimation unit. 7. The S number of frequency offset means respectively receives the N input received signals, and inputs the current N input received signals and Mi symbols (i = 1 to S; S is 2 or more). 6. The receiver according to claim 5, wherein the frequency offset is estimated based on N received input signals of past N systems and Mi which is one or more integers different from each other and known information on the transmission signal. . 8. The S frequency offset estimating means receives the determination value or known transmission data and the N-system input received signals, respectively, and receives a current determination value or known transmission data and Mi. Symbol (i = 1 to S; S is an integer of 2 or more; Mi is an integer of 1 or more different from each other), past judgment values or known transmission data, current N input reception signals, and only past Mi symbols A phase deviation detecting means for detecting a phase deviation occurring between Mi symbols based on the N received signals of the N systems, and averaging the phase deviation outputted by the phase deviation detecting means,
The receiver according to claim 5, further comprising: a phase deviation averaging unit that outputs a frequency offset. 9. The phase deviation detecting means outputs a phase deviation represented by a complex number, and the phase deviation averaging means inputs a complex number phase deviation generated between Mi symbols output by the phase deviation detecting means. Polar coordinate conversion means for outputting a phase component obtained by converting the complex-valued phase deviation into polar coordinates, and averaging means for inputting the phase component output by the polar coordinate conversion means and estimating a phase deviation per symbol. The receiver according to claim 4, comprising: 10. The phase deviation detecting means outputs a phase deviation represented by a complex number, and the phase deviation averaging means inputs a complex-valued phase deviation generated between Mi symbols output by the phase deviation detecting means. An averaging means for averaging the complex-valued phase deviation; a complex-valued phase deviation output from the averaging means; a polar coordinate conversion means for outputting a phase component obtained by converting the phase deviation into polar coordinates; and the polar coordinate conversion. 9. The receiver according to claim 4, further comprising: division means for inputting a phase component output from the means and calculating a phase deviation per symbol. 11. A means for multiplying an input received signal to generate a multiplied received signal representing a known fixed value, inputting the multiplied received signal and a known fixed value, and inputting the known fixed value And the current multiplied received signal and Mi symbols (i is 1 to S; S is an integer of 2 or more and each Mi is an integer of 1 or more different from each other) based on the past multiplied received signal and a frequency offset. S frequency offset estimating means for estimating, and fine adjustment means for calculating and outputting a finely adjusted frequency offset based on the S i-th frequency offsets output by the S frequency offset estimating means; A frequency dividing means for inputting the finely adjusted frequency offset output by the fine adjusting means, and outputting a frequency division value thereof; and a frequency offset after frequency division outputted by the frequency dividing means,
A transmission path estimating means for estimating a transmission path characteristic determined by a carrier phase and an amplitude of the input received signal; inputting the transmission path characteristic output by the transmission path estimating means and the input received signal; A receiver, comprising: reception signal correction means for correcting the phase and / or amplitude of a reception signal, wherein the determination is performed on the input reception signal corrected by the reception signal correction means.