JP3098473B2 - Information processing apparatus and information processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing system for performing large-scale data processing, and more particularly to an information processing device for transferring array data in a storage device between a plurality of devices.

[0002]

2. Description of the Related Art Conventionally, data transfer between a plurality of information processing apparatuses is performed by accessing each address of the sub-array data when accessing the entire sub-array data in the two-dimensional array data as shown in Japanese Patent Application Laid-Open No. 05-108581. Instructions were broken down into units, and instructions were issued by dividing the total number of transfer elements by the number of subarray data elements.

[0003]

The first problem is that when accessing the entire sub-array data in two-dimensional array data, the total number of transfer elements is divided by the number of sub-array data elements regardless of the number of sub-array data elements. Therefore, the data transfer instruction must be issued correspondingly, and the transfer efficiency at the time of data transfer is low.

[0004]

A first information processing apparatus according to the present invention has a storage unit, at least one processor, a data transfer circuit, and a transfer control circuit.
Instruction type, number of subarray data elements, total number of transfer elements, distance between source elements, distance between source subarrays, source base address, distance between destination elements, distance between destination subarrays and destination base address, the transfer control circuit determines that the storage unit for storing the transfer command from the processor, the number of subarrays data elements constituting the two-dimensional array stored in the main storage unit is a predetermined value a transfer length comparator circuit, wherein when the transfer length comparator circuit determination in is the number of predetermined elements, the transfer length replacement circuit replacing the sub-array number data elements to the total number of transfer elements, the distance between the transfer source element And a distance changing circuit for changing the distance to the distance between the transfer source sub-arrays, and the transfer circuit executes the transfer in accordance with an instruction from the transfer control circuit.

[0005] A second information processing apparatus according to the present invention is the first information processing apparatus according to the present invention, wherein:
If the difference between the total transfer element and the sub-array number data element is larger than a predetermined value, changing the number of subarrays data element to the total number of transfer elements, the distance between the transfer source element to a distance between the transfer source sub-arrays Replace.

An information processing system according to the present invention has a first information processing apparatus according to the present invention or a second information processing apparatus according to the present invention as a node, and has a connection device for connecting the nodes.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an information processing system according to the present invention. The information processing system includes first, second, third, and fourth nodes 1, 2, 3, and 4, which are information processing devices that perform data transfer, and an inter-node connection device 5.

Next, the operation of data transfer between nodes will be described.

The transfer instruction in the two-dimensional array data issued from the source node to the destination node is composed of transfer units RQ, DATA, and AD of the sub-array data which is a part of the two-dimensional array data in the node. Broken down into instructions
Instructions are issued by dividing the total number of transfer elements by the number of subarray data elements. The sub-array data represents a set of data that exists in the one-dimensional direction in an array constituting the two-dimensional array data. When transferring the two-dimensional array data from the first node 1 to the third node 3, the first node 1 sends an instruction and data to the third node 3 for each decomposed sub-array. The third node 3 receiving the instruction and the data generates an address in the sub-array data from the address in the instruction, information on the number of elements, and information on the distance between elements, and stores the data in a predetermined storage address of the third node 3 I do.

FIG. 2 is a block diagram showing the configuration of a node in which the information processing apparatus of the present invention is the first node 1.

In FIG. 2, a first node 1 includes a first operation processor 15, a second operation processor 16, a storage unit 12, an inter-node instruction issuing unit 11, a sub-array data decomposition processing unit 14, and a connection unit 13. Be composed.
First operation processor 15 and second operation processor 16
The storage unit 12, the inter-node instruction issuing unit 11, and the sub-array data decomposition processing device 14 are connected by a connection device 13. The inter-node instruction issuing means 11 includes a transfer length comparing circuit 12
0, transfer length replacement circuit 119, transfer source element distance replacement circuit 118, transfer destination element distance replacement circuit 11
7, instruction reception register 122, instruction holding register 1
16, an instruction output register 112, a memory instruction output register 111, a selector 115, an address generation circuit 113,
It comprises a transfer destination address generation circuit 114 and an instruction disassembly control circuit 121. Instruction reception register 122
Receives an inter-node transfer command from the connection device 13 and stores the command.

Next, the operation of the first node 1 will be described. When the inter-node transfer instruction is issued from the first arithmetic processor 15, the connection device 13 identifies the inter-node transfer instruction,
An instruction is sent to the inter-node instruction issuing means 11. The inter-node instruction issuing means 11 sends an instruction including an address and data corresponding to the instruction to the transfer destination node via the inter-node connecting device 5. In the transfer destination node, the inter-node connection device 5
Is input to the sub-array data decomposition processor 14 and the data is stored in the storage unit 12 from the address and data accompanying the instruction. The transfer instruction between nodes includes the instruction type, the number of subarray data elements, the total number of transfer elements, the distance between source elements, the distance between source subarrays, the source base address, the distance between destination elements, the distance between destination subarrays, and the destination. It consists of a base address. For each element of these instructions, the instruction type is CMD of the instruction reception register 122, and the number of subarray data elements is L in the instruction reception register 122.
1, the total number of transfer elements is L in the instruction reception register 122.
The distance between transfer source elements is DL1 of the instruction reception register 122, the distance between transfer source subarrays is DL2 of the instruction reception register 122, the source base address is BL in the instruction reception register 122, and the distance between transfer destination elements is the instruction. DR1 of the reception register 122, the distance between the transfer destination sub-arrays is DR2 of the instruction reception register 122, and the transfer destination base address is the BR of the instruction reception register 122.
Is stored.

The instruction issued from the first arithmetic processor 15 and received by the inter-node instruction issuing means 11 via the connection device 13 is a selector 115, a transfer length comparing circuit 120,
Transfer length replacement circuit 119, element distance replacement circuit 1
18 and the transfer destination element distance replacing circuit 117. The transfer length comparison time 120 is the instruction reception register 1
22, the number of subarray data elements L in the instruction accepted
1 is determined to be 1 and the result is transferred to the transfer length replacing circuit 1
19 and an inter-element distance replacement circuit 118. The transfer length replacement circuit 119 includes a sub-array data element number L1
Is 1, the sub-array data can be processed as one data in the sub-array data. Therefore, the total number of transfer elements L is selected instead of the number of sub-array data elements L1, otherwise, the number of sub-array data elements L1 is selected. To the selector 115. Element distance replacement circuit 118
Is the distance D1 between the source sub-arrays instead of the distance DL1 between the source elements when the number L1 of sub-array data elements is 1.
In the other cases, the transfer source element distance DL1 is selected and sent to the selector 115. The inter-element distance replacement circuit 8-2 uses the inter-destination sub-array distance DR2 instead of the inter-destination element distance DR1 when the number of sub-array data elements L1 is 1, and the inter-destination element distance DR1 otherwise. Select and send to selector 115. The selector 115 receives an instruction received from the instruction holding register 116 when an instruction disassembling operation is being performed on an instruction received from the instruction receiving register 122 and the instruction holding register 116, and receives an instruction from the instruction receiving register 122 otherwise. Instruction disassembly control circuit 12
1 and sent to the instruction holding register 116. The instruction disassembly control circuit 121 is activated after receiving the instruction in the instruction reception register 122, and generates a control signal until the instruction is disassembled. The instruction holding register 116 sets the instruction selected by the selector 115 and sends it to the instruction output register 112, the address generation circuit 113, and the transfer destination address generation circuit 114. The address generation circuit 113 and the transfer destination address generation circuit 114 calculate an address in each instruction when the data transfer instruction received from the instruction holding register 116 is decomposed into a plurality of instructions,
Memory instruction output register 111 and instruction output register 11
2 and selector 115. The address generation circuit 113 calculates the source address BL, and the destination address generation circuit 114 calculates the destination address BR. The memory instruction output register 111 generates the number of sub-array data elements L1, the distance between transfer source elements DL1, and the transfer source address BL received from the address generation circuit 113 to the storage unit 12, the instruction received from the instruction holding register 116, and the transfer destination address generation. The transfer destination address BR received from the circuit 114 is written into the instruction output register 112, and the instruction in the instruction output register 112 is issued to the transfer destination node through the inter-node connection device 5. Note that the transfer destination node may be its own node.

Next, a description will be given of a case where the sub-array data is transferred without degeneration and a case where the sub-array data is degenerated and transferred in the present invention.

First, a case in which no degeneration is performed will be described. FIG. 3 shows the operation of the inter-node transfer instruction when the number of elements in the sub-array is not 1 and the sub-array data is not degenerated.

The source main storage address BL, the destination main storage address BR, the total number of transfer elements L, the number of subarray data elements L1, the distance between elements in the source subarray DL1, the distance between elements in the destination subarray DR1, the source subarray An inter-distance DL2 and a transfer-destination sub-array distance DR2 are used. The batch transfer of the sub-array data in the two-dimensional array data between nodes is performed by using the address BL on the storage unit 12 in the transfer source node.
Is the start address, the distance DL1 between the elements in the transfer source sub-array.
The sub-array data stored at the distant address stores the number of elements L1 and the data of the total number of transfer elements L at the source sub-array distance DL2.
The transfer is performed to the address indicated by the transfer destination sub-array distance DR2 as a collection of data of the number of sub-array data elements L1 having the transfer destination sub-array internal element distance DR1 starting from the address BR on No. 2. In FIG. 4, L1 is 1,
An operation explanatory diagram when L is 256 is shown. In this case, a set of 1 subarray data elements having an inter-element distance DL1 from the address BL on the storage unit 12 in the source node is stored in the destination node as data of a total 256 elements at an inter-subarray distance DL2. The data is transferred at an interval DR2 as a group of data of the number of subarray data elements 1 having an inter-element distance DR1 from the address BR on the unit 12. At this time, 256 transfer instructions need to be issued. In the transfer destination node, the sub-array data decomposing processor 14 receives the instruction and the address associated with the instruction and the data corresponding to the address, and stores the data corresponding to the address in the storage unit 12 in the transfer destination node through the connection device 13.

Next, the case of degenerate transfer will be described. In FIG. 5, L1 is 1 and L is 256. The operation of the information processing apparatus at this time will be described with reference to FIG.
The data transfer command RQ0 sent from the first arithmetic processor 15 is sent to the connection device 13. Connection device 13
Sends a data transfer instruction RQ0 to the instruction reception register 122 in the inter-node instruction issuing means 111. The instruction reception register 122 stores the instruction code CMD in the selector 1
15 to the instruction disassembly control circuit 121, the transfer length comparison circuit 120, the transfer length replacement circuit 119, and the instruction disassembly control circuit 121 to transfer the total number of transfer elements L to the transfer length replacement circuit 119, the selector 115, and the instruction. The disassembly control circuit 121 sends the inter-element distance DL1 in the transfer source sub-array to the inter-element distance replacement circuit 118, and the transfer source inter-array distance DL2 to the inter-element distance replacement circuit 118 and the selector 115.
L to the selector 115, the inter-element distance DR1 in the destination sub-array to the destination element distance replacing circuit 117 and the selector 115, and the destination inter-array distance DR2 to the destination element distance replacing circuit 117 and the selector 115.
And the transfer destination base address BR to the selector 115. The transfer length comparison circuit 120 determines whether or not L1 is 1, and since L1 is 1, sends a replacement instruction to the transfer length replacement circuit 119, the inter-element distance replacement circuit 118, and the transfer destination inter-element distance replacement circuit 117. I do. The transfer length replacing circuit 119 includes a transfer length comparing circuit 1
In response to the replacement instruction at 20, the selector 1 replaces L1 (1 in this case) with L (256 in this case).
15 Upon receiving the replacement instruction from the transfer length comparison circuit 120, the inter-element distance replacement circuit 118 replaces the inter-element distance DL1 in the transfer source sub-array with the transfer source sub-array distance DL2 and sends it to the selector 115.
Upon receiving the replacement instruction in the transfer length comparing circuit 120, the transfer destination element distance replacing circuit 117 changes the distance DR1 between elements in the transfer destination sub-array to the distance DR between transfer destination sub-arrays.
2 and sends it to the selector 115. Selector 1
The instruction 15 selects an instruction received from the instruction reception register 122 because the instruction received from the instruction reception register 122 and the instruction holding register 116 is not in an instruction disassembling operation, and sends the selected instruction to the instruction holding register 116. The instruction holding register 116 sets an instruction received from the selector 115 and sends it to the address generation circuit 113, the destination address generation circuit 114, and the memory instruction output register 111. Transfer destination address generation circuit 11
4 calculates the addresses BL and BR in the data transfer instruction during the disassembly operation received from the instruction holding register 116, and since the number of elements is one, the memory instruction output register 111 and the instruction output register 1 are designated as BL and BR, respectively.
12 is sent. In the transfer instruction between nodes in FIG. 5, L1 =
1, since L = 256, a group of 256 sub-array data elements having a distance DL1 between elements in the source sub-array from the address BL on the storage unit 12 in the source node is calculated by the total transfer elements in the distance DL2 between the source sub-arrays. Number 256
And transfer to the transfer destination node. At this time, the number of transfer instructions that need to be issued is one. Instruction output register 1
12 is a CM received from the instruction holding register 116
Instruction R composed of D, L1 = 256, DR1, BR
Q1 is issued to the transfer destination node through the inter-node connecting device 5. At the source node, the number of subarray data elements L
1. The element distance DL1 in the transfer source sub-array and the transfer source address BL are sent to the storage unit 12 in the own node to access the storage unit 12, and the data corresponding to the address is transferred to the transfer destination through the connection device 13 and the connection device 5 between the nodes. Send to node. In the transfer destination node, the sub-array data decomposition processing unit 14 receives the instruction and the address associated with the instruction and the data corresponding to the address.
3, the data corresponding to the address is stored in the storage unit 12 within the transfer destination node. FIG. 6 is a block diagram of a first node 1 having, as a node, an information processing device that performs degenerate transfer when the number L1 of subarray data elements is not 1, but is relatively small and the total number L of transfer elements is large. It is.
The configuration difference from FIG.
A transfer source address replacement circuit 123 and a transfer destination address replacement circuit 124 for replacing addresses are provided between the instruction holding register 116 and the instruction holding register 116. The transfer length comparison circuit 120 compares the number of sub-array data elements L1 and the total number of transfer elements L. If the number of sub-array data elements L1 is smaller than L for L, the transfer length replacement circuit 119 and the inter-element distance replacement circuit 118,
A transfer length, an inter-element distance, and an address replacement instruction are sent to the transfer destination element distance replacement circuit 117, the transfer source address replacement circuit 123, and the transfer destination address replacement circuit 124, respectively. Transfer length replacement circuit 11
No. 9 replaces the number L1 of subarray data elements with L1 for L. The inter-element distance replacement circuit 118 calculates the value of DL2 (n = n) by multiplying the inter-element distance DL1 in the transfer source sub-array by n.
1, 2,... N, where n indicates the number of transfers). Transfer destination element distance replacement circuit 11
7 is replaced with the value of DR2 (n = 1, 2,... N, where n indicates the number of transfers), which is n times the distance DR1 between elements in the transfer destination sub-array. The transfer source address replacement circuit 123 adds a value DL1 multiplied by m to the transfer source address BL (m = 0, 1, 2,..., N−1,
Here, n indicates the number of the transfer). The transfer destination address replacement circuit 124 obtains a value obtained by adding DR1 which is obtained by multiplying the transfer destination address BR by m (m = 0,
1, 2,..., N−1, where n indicates the number of transfers). As a result, as shown in FIG. 7, elements are collected one by one from each sub-array data and transferred by one instruction, and this is performed L1 times, so that the smaller the number L1 of sub-array data elements, the smaller the number of instructions. Data transfer can be realized.

[0019]

The first effect is that when the number of elements in the sub-array data is 1, the distance between elements in the sub-array is replaced with the distance between the sub-arrays, and the number of elements in the sub-array data is replaced with the total number of transfer elements. Thus, the number of data transfer instructions that must be issued for the total number of transfer elements is one.
The data transfer can be performed at once, and the efficiency of the data transfer can be increased by performing the data transfer collectively.

The second effect is that even when the number of elements of the sub-array data is not 1, but is relatively small and the total number of transfer elements is large, the data transfer can be performed collectively and the transfer efficiency can be improved. Can be raised.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional batch transfer operation of sub-array data.

FIG. 4 is an explanatory diagram of a conventional sub-array data transfer operation when the total number of transfer elements is 256.

FIG. 5 is an explanatory diagram of the operation of the second embodiment of the present invention when the total number of transfer elements is 256.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is an explanatory diagram of an operation according to the third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st node 2 2nd node 3 3rd node 4 4th node 5 Inter-node connection device 11 Inter-node command issuing means 12 Storage unit 13 Connection device 14 Sub-array data decomposition processing device 15 First arithmetic processor 16 Second arithmetic processor 111 Memory instruction output register 112 Instruction output register 113 Address generation circuit 114 Destination address generation circuit 115 Selector 116 Instruction holding register 117 Transfer destination element distance replacement circuit 118 Element distance replacement circuit 119 Transfer length replacement circuit 120 Transfer length comparison circuit 121 Instruction disassembly control circuit 122 Instruction reception register 123 Transfer source address replacement circuit 124 Transfer destination address replacement circuit

Claims (3)

(57) [Claims] An information processing apparatus includes a storage unit, at least one processor, a data transfer circuit, and a transfer control circuit, wherein a transfer instruction includes an instruction type, a number of sub-array data elements, a total number of transfer elements, and a distance between transfer source elements. A transfer unit for storing the transfer instruction from the processor, the transfer control circuit comprising: a transfer source sub-array distance, a transfer source base address, a transfer destination element distance, a transfer destination sub-array distance, and a transfer destination base address. When the transfer length comparator circuit determines that the number of subarrays data elements constituting the two-dimensional array stored in the main storage unit is a predetermined value, the determination result in the transfer length comparator circuit is given when a number of elements, the transfer length replacement circuit replacing the sub-array number data elements to the total number of transfer elements, wherein the source element distance the transfer source sub-arrays between distance It has a distance replacement circuit substituting the information processing apparatus and executes the transfer by an instruction of the transfer control circuit in the transfer circuit. 2. A said replacement circuit, wherein, when the subarrays number of data elements difference total transfer element number is greater than a predetermined value, changing the number of subarrays data element to the total number of transfer elements, wherein the source element 2. The information processing apparatus according to claim 1, wherein an inter-distance is replaced with the inter- source sub-array distance. 3. An information processing system, wherein the information processing device according to claim 1 or 2 is a node, and the node is connected by a connection device.