JP3097841B2 - Method of manufacturing photomask and active element array substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photomask for manufacturing an active element array substrate constituting a display panel of a liquid crystal display, and a method for manufacturing an active element array substrate using the photomask. .

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device has been widely used as a means for displaying an image in information equipment such as OA equipment and a television. 2. Description of the Related Art A liquid crystal display panel serving as a display screen of a liquid crystal display device is provided with a thin film transistor (hereinafter, referred to as a TFT) for driving liquid crystal. Here, a substrate on which a TFT as an active element, a pixel electrode, a source wiring, a gate wiring, and the like are formed is referred to as an active element array substrate.

In order to increase the aperture ratio on the display screen of such a liquid crystal display panel, there is an active element array substrate having a pixel electrode formed on the uppermost layer on the substrate. This active element array substrate manufacturing method, Shinjo et al., High aperture ratio 11.3 inches SVGA manufactured by a shortened process method
TFT-LCD, 1996 Active Matrix Liquid Crystal Display International Conference (AM-LCD 96) Proceedings, pp. 201-204 (M. Sinjou et al., AHigh Aperture Ratio 11.3 inch)
-diagonal SVGA TFT-LCDs Fabricated by Reduced Proc
ess Method, Digest of Technical Papers 1996 Intern
ational Workshop on Active-Matrix Liquid Crystal
Displays (AM-LCD 96), pp. 201-204 are known.

FIG. 9 is a sectional view showing the structure of the conventional active element array substrate. In this figure, the active element array substrate includes a substrate 1 made of glass, a source electrode 2 of the TFT, a drain electrode 3 of the TFT, a TFT 4 and a TF.
The gate electrode wiring 5 of T, the source wiring 6b connected to the source electrode 2, the interlayer insulating film 7, the contact hole 7a, the pixel electrode 8, etc. are formed. The contact hole 7a is a hole formed in the interlayer insulating film 7 for connecting the drain electrode 3 and the pixel electrode 8.

To manufacture an active element array substrate having such a structure, first, a substrate 1 made of glass is
Indium Tin Oxide (hereinafter ITO)
) Is formed. Next, a TFT 4 is formed by forming amorphous Si and SiN as a channel layer and a gate insulating film, respectively, so as to extend over the source electrode 2 and the drain electrode 3. And T
A gate is provided on the semiconductor layer of FT4, and a gate electrode wiring 5 is formed integrally with the gate. Further, a source wiring 6b is formed integrally with the source electrode 2.

Next, a photosensitive and low dielectric constant (relative dielectric constant = 3.5) interlayer insulating material film 7c is spin-coated on the entire surface of the substrate to a thickness of 1.5 μm. Then, exposure and development are performed using a photomask having a predetermined pattern to form a contact hole 7 a on the drain electrode 3.
Next, ITO is formed again on the entire surface of the interlayer insulating film 7 including the contact hole 7a. Then, the pixel electrode 8 is formed by a photo-etching process. In this case, the pixel electrode 8 is connected to the drain electrode 3 via the contact hole 7a, and the gate electrode wiring 5 via the interlayer insulating film 7.
The pixel electrode 8 is formed on the upper portion and the source line 6.

As described above, since the interlayer insulating film 7 exists between the pixel electrode 8 and the TFT 4, the pixel electrode 8 in the uppermost layer can be formed to extend over the gate electrode wiring 5 and the source wiring 6b. For this reason, the effective area (aperture ratio) of the pixel electrode 8
Can be increased. Further, by forming the interlayer insulating film 7 to be thick by spin coating, the parasitic capacitance of the gate electrode wiring 5 and the source wiring 6 with respect to the pixel electrode 8 can be reduced. Therefore, it is possible to obtain a liquid crystal display panel having a large aperture ratio while suppressing the occurrence of crosstalk.

[0008]

However, in the above-described conventional photomask and the method of manufacturing an active element array substrate using the photomask, the pixel electrode is formed on the thick interlayer insulating film 7 as described above. When forming 8, there is a problem that a short circuit may occur between a plurality of mounting terminals formed adjacently on the substrate 1 to supply power to the respective TFTs 4 for the reason described below. there were.

The occurrence of a short circuit between the mounting terminals will be described below with reference to FIGS. FIG. 10 is a plan view of a mounting terminal portion in a conventional method for manufacturing an active element array substrate using a photomask pattern. 10A is a partially transparent plan view before forming a pixel electrode, and FIG. 10B is a partially transparent plan view after forming a pixel electrode. 11 and FIG.
FIG. 11 is a cross-sectional view of the active element array substrate showing a process from a step of forming an interlayer insulating film to a step of forming a pixel electrode in a cross section taken along a line AB in FIGS.

Referring to FIGS. 10 to 12, a mounting terminal 6a is provided at a mounting terminal portion of the substrate 1 to supply power to the source wiring 6b. The interlayer insulating material film 7c shown in FIG.
Is a photosensitive interlayer insulating material film applied before the pixel electrode material film is formed. The photomask 20 has the opening 2
0a and a light-shielding portion 20b, and is exposed by ultraviolet rays 21.

First, in forming the interlayer insulating film 7, FIG.
0 (a) and FIG. 11 (a), the mounting terminals 6a
Is formed on the entire surface of the substrate 1 on which is formed the interlayer insulating material film 7c.
Is spin-coated. Next, the interlayer insulating material film 7c on the mounting terminals 6a is exposed to ultraviolet rays 21 using the first photomask 20 having the openings 20a and the light shielding portions 20b.

Next, the interlayer insulating material film 7c is developed to form a contact hole 7a, and the interlayer insulating material film 7c is removed from these portions so as to expose the mounting terminals 6a. In this way, as shown in FIGS. 10A and 11B, an end portion 7b of the interlayer insulating film is formed. In this case, the angle of the inclined surface of the end portion 7b of the interlayer insulating film with respect to the substrate 1 is close to 90 °, and the inclined angle depends on the exposure machine and the resolution of development.

Next, as shown in FIG.
A pixel electrode material film 8a made of TO is formed. Then, for the photo-etching process for forming the pixel electrode 8,
A resist 9 is applied on the entire surface. Here, in the vicinity of the end portion 7b of the interlayer insulating film, the film thickness of the resist 9 in the portion indicated by the arrow T1 is larger than the film thickness of the flat portion indicated by the arrow T2. This is a phenomenon that occurs because the interlayer insulating film 7 is thick.

Next, the resist 9 is exposed using a second photomask. The photomask is as shown in FIG.
It has a mask pattern corresponding to the arrangement pattern of the mounting terminals 6a. Next, when development is performed after exposure, FIG.
As shown by the arrow P in (d), a part of the resist 9 may be left at the bottom of the interlayer insulating film end 7b. This portion is called a resist residue (residue) 9a.

When such a resist residue 9a is generated,
As a matter of course, in the next step of etching the pixel electrode material film 8a, FIG. 10B and FIG.
As shown in FIG. 7, a pixel electrode material residue 8b is generated. For this reason, a short circuit occurs between the adjacent mounting terminals 6a.

In order to prevent such a resist residue 9a, it is conceivable to (1) reduce the thickness of the resist 9 or (2) excessively expose and develop the resist 9. In the former case, there is a concern that the pinhole density of the resist 9 will increase, and in the latter case, there is a concern that the productivity may be reduced due to the extension of the production tact and the size of the resist pattern may be reduced.

The inventions of claims 1 to 3 of the present application have been made in view of such conventional problems, and use a thick interlayer insulating film without changing the production tact, and It is an object of the present invention to realize a photomask which can prevent a short circuit between mounting terminals in the vicinity of the above. It is another object of the present invention to establish a method for manufacturing an active element array substrate using the photomask.

[0018]

In order to solve such a problem, the invention according to claim 1 of the present application is used when manufacturing an array substrate of active elements for driving liquid crystal of each pixel of a liquid crystal display panel, A photomask for forming an interlayer insulating film that insulates a pixel electrode and the active element from each other, and is a contact hole that passes irradiation light of an exposure device to connect the active element and the pixel electrode of a specific pixel. A pattern and, in a plurality of mounting terminal portions serving as external signal lines to be applied to each of the active elements, an opening pattern for passing irradiation light of an exposure device, in order to remove a part of the formed interlayer insulating material film; And a boundary pattern having a pitch smaller than the resolution of the exposure device between the light-shielding portion pattern that shields the irradiation light of the exposure device and the opening pattern. In which it characterized in that a down.

According to a second aspect of the present invention, in the photomask according to the first aspect, the boundary pattern is an uneven pattern having a pitch smaller than the resolution of the exposure machine. is there.

According to a third aspect of the present invention, in the photomask of the first aspect, the boundary pattern is a stripe pattern having a pitch smaller than the resolution of the exposure machine. is there.

According to a fourth aspect of the present invention, in a liquid crystal display panel for displaying an image by driving a liquid crystal sandwiched between two substrates through a plurality of pixel electrodes, the liquid crystal of each pixel is driven. A method for manufacturing an active element array substrate, comprising: a first step of arranging a plurality of active elements for driving liquid crystal of each pixel on one of the two substrates; For the drive electrodes of the active element formed in the step, a signal line for coupling to the outer peripheral portion of the substrate is formed using a conductive electrode film, and the signal line is coupled to the outer peripheral portion of the substrate with the signal line. A second step of forming the mounted terminals using the electrode film, a third step of applying an interlayer insulating material film to the electrode film formed in the second step, Interlayer insulating material formed in the process Respect, fourth performing development processing and exposure by the exposure apparatus using the photomask of claim 1, wherein
And a fifth step of forming a pixel electrode material film after the fourth step, and applying a photosensitive resist to the pixel electrode material film formed in the fifth step. A sixth step of performing exposure and development processing using a mask, connecting to a specific drive electrode of the active element, and forming a pixel electrode that applies a drive voltage to the liquid crystal. is there.

According to a fifth aspect of the present invention, in the method for manufacturing an active element array substrate according to the fourth aspect, the active element is a thin film transistor, and the contact hole of the interlayer insulating film obtained in the fourth step is , And is connected to a drain electrode of the thin film transistor.

According to a sixth aspect of the present invention, in the method for manufacturing an active element array substrate of the fourth aspect, the interlayer insulating material film used in the third step is a photosensitive organic film. Is what you do.

According to a seventh aspect of the present invention, in the method of manufacturing an active element array substrate according to the fourth aspect, the pixel electrode material film used in the fifth step is indium tin oxide. It is assumed that.

[0025]

(Embodiment) A photomask pattern and a method for manufacturing an active element array substrate using the photomask pattern according to an embodiment of the present invention will be described below with reference to the drawings. The electrodes or various films having the same functions as those of the conventional example will be described using the same reference numerals as those of the conventional example.

FIG. 1 is an explanatory diagram of a pattern of a photomask used in a manufacturing process of an active element array substrate according to the present embodiment. The photomask 20A in this figure shows only the pattern of the mounting terminal portion, and does not show the pattern around the TFT. This photomask 20A has an opening 20
a and the pattern of the light shielding portion 20b, and the boundary portion 20c
The feature is that a new pattern is provided. The light-shielding portion 20b is a pattern for blocking ultraviolet light output from the exposure device so as to leave the interlayer insulating material film 7c, and the opening 20a is a pattern having the opposite effect. The opening 20a is positioned in a portion of the active element array substrate where the mounting terminals 6a are located.

The boundary portion 20c is provided with a resolution (also called a resolution) of an exposure machine used in a process of processing the interlayer insulating material film 7c.
This is a portion where an uneven edge pattern having a smaller pitch is formed. This exposure machine
The entire liquid crystal display panel is exposed, and its exposure range is wider than that of a semiconductor wafer exposure machine, and its resolution is, for example, about several μm (for example, 4 μm). Therefore, the pitch of the unevenness of the boundary portion 20c is set to 2 μm here.

FIG. 2 and FIG. 3 are explanatory views showing a cross-sectional structure of a manufacturing process of an active element portion in the active element array substrate. 4 and 5 are explanatory views showing a cross-sectional structure in a manufacturing process of a mounting terminal portion in the active element array substrate. 6 and 7 are plan views showing the contents of the manufacturing process of the mounting terminal portion in the active element array substrate.

As shown in FIG. 2A, the structure of the active element section of the present embodiment is different from that of the conventional example shown in FIG. Of the two substrates that make up the liquid crystal panel,
A large number of active element portions are formed in a matrix on the upper surface of one substrate 1. The manufacturing process of the active element portion will be described below.

First, as a first step, a glass substrate (# 1737, dimension: 370 × 470 mm ² , manufactured by Corning Incorporated) having a thickness of 35 mm by a sputtering method using Ar gas.
A 0 nm AlZr alloy (Zr: 1 at.%) Is formed. Then, the gate electrode wiring 5 is formed by etching using the gate pattern.

Next, a plasma enhanced chemical vapor deposition (hereinafter referred to as P
The first SiNx to a thickness of 200 nm
The gate insulating film 11 is formed on the entire surface of the substrate 1. Then, amorphous Si for forming the channel layer 12 is formed.
Is deposited to a thickness of 50 nm. Further, a second SiNx to be a channel protective film 13 is deposited to a thickness of 150 nm.

Next, P is added as an impurity by the P-CVD method, and amorphous Si having a thickness of 50 nm is made n-type. Then the second
In the step (b), the thickness of the source electrode 2 and the drain electrode 3 becomes 100 n by a sputtering method using Ar gas.
m of Ti and 350 nm of Al are formed respectively. This Ti and A
The l film is called an electrode film 6. Next, the channel layer 12, the contact layer 14, the source electrode 2, and the drain electrode 3 are respectively formed by etching the amorphous Si, the n-type amorphous SI, and the electrode film 6.

The formation of the electrode film 6, which is a material of the source electrode 2, the drain electrode 3, and the mounting terminal 6a, is performed on the entire surface of the substrate.
The mounting terminal 6a is formed by the mounting electrode section shown in FIG.

Next, as a third step, as shown in FIGS. 2B and 4A, an interlayer insulating material made of a photosensitive organic material (manufactured by Nippon Synthetic Rubber Co., Ltd .; PC-302) is formed on the entire surface of the substrate. Is spin-coated (1000 rpm for 15 sec) to form an interlayer insulating material film 7c having a thickness of 2.5 μm. Thereafter, the photomask 20A described with reference to FIG. FIG. 6B shows a state where the photomask 20A is positioned at the mounting terminal portion of the substrate. The boundary 20c of the photomask 20A is positioned in a direction crossing the mounting terminal 6a at right angles. In FIG. 6B, the outer shape of the photomask 20A shown by a solid line is larger than that of the substrate 1 shown by a broken line. The exposure machine used at this time is, for example, manufactured by Canon Inc., and has an MPA-3000 (mirror projection 1: 1, NA = 0.083, resolution = about 4 μm).

Next, as a fourth step, the exposed interlayer insulating material film 7c is developed and dried to form a contact hole 7a and to remove the portion of the interlayer insulating material film 7c facing the opening 20a. . This state is shown in FIG.
(C), FIG. 4 (b) and FIG. 7 (c). Boundary part 20c
Since the resolution of the exposure device is lower than the pitch of the concave / convex pattern, the intensity distribution of the incident light becomes broad at the boundary 20c. Therefore, the contour reproduction accuracy of the etching of the interlayer insulating material film 7c in this portion is deteriorated. As a result, as shown in FIG.
1, the inclination of the end portion 7b of the interlayer insulating film became gentler.

At this time, the taper angle of the interlayer insulating film 7 at the contact hole 7a is about 70 degrees,
The taper angle at b was about 45-55 degrees. The variation of the taper angle of the interlayer insulating film end 7b in the range of about 45 to 55 degrees is due to the effect of the pattern of the boundary 20c.

Next, as a fifth step, Ar,
By sputtering using an O ₂ mixed gas, ITO
Is formed to a thickness of about 100 nm to form a pixel electrode material film 8a. Next, as a sixth step, a positive photosensitive resist (manufactured by Tokyo Ohkasha; OFPR-5000) is spin-coated (1200 rp) on the entire surface.
m20 sec) to form a resist film 9. This state is shown in FIG.
(C) and FIG. 7 (d). Here, as shown by an arrow T2 in FIG. 5C, the thickness of the resist film 9 is about 2 μm excluding the vicinity of the interlayer insulating film end 7b and the vicinity of the contact hole 7a. In the vicinity of the interlayer insulating film end 7b;
That is, the portion indicated by the arrow T3 was about 2.2 μm.

Next, the resist film 9 is exposed (the condition is 20 mJ / c
m ² ) and develop. As the developing conditions, NMD-3 manufactured by Tokyo Ohkasha Co., Ltd. was used, and the immersion time was 90 seconds. Then, a resist pattern 9b as shown in FIG. 3D is formed. At this time, even in the vicinity of the interlayer insulating film end portion 7b where the film thickness of the resist film 9 was somewhat thicker than the surroundings, the resist residue 9a as shown in the prior art did not occur. This state is shown in FIG.

Next, wet etching is performed using the resist pattern 9b as a mask. Thus, the pixel electrode 8 connected to the drain electrode 3 is formed through the contact hole 7a. This state is shown in FIGS. 3D and 5D. Since there is no resist residue 9a, as shown in FIGS. 5D and 7D, no pixel electrode material residue 8b was generated. Finally, the resist pattern 9b is removed to obtain an active element array substrate. This state is shown in FIG.
(E), FIG. 5 (e), and FIG. 7 (e).

According to the above-described embodiment, even if a thick interlayer insulating film is used, a short circuit between the mounting terminals 6a can be prevented without changing the production tact.

In the above description, the pattern of the boundary 20c is an uneven pattern, and the pitch and height of the projections are each 2 μm. However, the pattern shape of the boundary 20c is smaller than the resolution of the exposing machine, and The taper angle of the interlayer insulating film 7 at the end 7b of the insulating film is reduced, and the resist residue 9
The shape is not limited as long as a does not occur. For example, when the resolution of the exposure machine is about 4 μm as in the present embodiment, any combination of uneven patterns may be used as long as the pitch and height of the unevenness are smaller than 4 μm. As shown in the photomask 20B of FIG. 8, the pattern of the boundary portion 20c may be a stripe pattern in which a thin line is provided through a narrow space, and the line and the stripe may be plural. In this case, the width of the line and the space is smaller than 4 μm.

Although the pixel electrode material film 8a is entirely removed near the interlayer insulating film end 7b, the pixel electrode material film 8a may be configured to cover the exposed mounting terminals 6a. Further, although the active element is a TFT, it is apparent that a non-linear two-terminal element such as a MIM may be used.

[0043]

As described above, according to the present invention, a boundary pattern smaller than the resolution of an exposure machine is provided as a photomask pattern corresponding to the formation of the edge of the interlayer insulating film. Even in the case of a film, it is possible to eliminate a resist residue in a later step at an end portion of the interlayer insulating film.
Therefore, when manufacturing a liquid crystal panel having a high aperture ratio using a thick interlayer insulating film without changing the production tact, a short circuit between mounting terminals can be prevented.

[Brief description of the drawings]

FIG. 1 is a pattern diagram (part 1) of a photomask according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process (part 1) around the active element of the active element array substrate according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing step (part 2) around the active element of the active element array substrate according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing step (part 1) around the mounting terminal portion of the active element array substrate according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing step (part 2) around the mounting terminal portion of the active element array substrate according to the embodiment of the present invention.

FIG. 6 is a plan view illustrating a manufacturing step (part 1) around the mounting terminal portion of the active element array substrate according to the embodiment of the present invention.

FIG. 7 is a plan view showing a manufacturing step (part 2) around the mounting terminal portion of the active element array substrate according to the embodiment of the present invention.

FIG. 8 is a pattern diagram (part 2) of a photomask according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a structure around an active element of an active element array substrate in a conventional example.

FIG. 10 is a plan view showing a manufacturing process around a mounting terminal portion of an active element array substrate in a conventional example.

FIG. 11 is a cross-sectional view showing a manufacturing step (part 1) around a mounting terminal portion of an active element array substrate in a conventional example.

FIG. 12 is a cross-sectional view showing a manufacturing step (part 2) around the mounting terminal portion of the active element array substrate in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Source electrode 3 Drain electrode 4 TFT 5 Gate electrode wiring 6 Electrode film 6a Mounting terminal 6b Source wiring 7 Interlayer insulating film 7a Contact hole 7b Interlayer insulating film edge 7c Interlayer insulating material film 8 Pixel electrode 8a Pixel electrode material film 8b Pixel electrode material residue 9 Resist 9a Resist residue 9b Resist pattern 11 Gate insulating film 12 Channel layer 13 Channel protective film 14 Contact layer 20A, 20B Photomask 20a Opening 20b Light shield 20c Boundary 21 UV

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-10407 (JP, A) JP-A-7-281416 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/1368

Claims (7)

(57) [Claims] 1. A photomask for use in manufacturing an array substrate of active elements for driving liquid crystal of each pixel of a liquid crystal display panel, and for forming an interlayer insulating film for insulating a pixel electrode and the active elements. In order to connect the active element and the pixel electrode of a specific pixel, a contact hole pattern for passing irradiation light of an exposure device, and a plurality of mounting terminal portions serving as external signal lines to be applied to each of the active elements are formed. An opening pattern that allows irradiation light from an exposure device to pass therethrough, and a light-shielding portion pattern that shields the irradiation light from the exposure device and the opening pattern. A photomask, wherein a boundary pattern having a pitch smaller than the resolution of the exposure machine is provided between the two. 2. The photomask according to claim 1, wherein the boundary portion pattern is an uneven pattern having a pitch smaller than the resolution of the exposure device. 3. The photomask according to claim 1, wherein the boundary pattern is a stripe pattern having a pitch smaller than the resolution of the exposure device. 4. A method of manufacturing an active element array substrate for driving a liquid crystal of each pixel in a liquid crystal display panel for displaying an image by driving a liquid crystal sandwiched between two substrates through a plurality of pixel electrodes. A first step of arranging a plurality of active elements for driving liquid crystal of each pixel on one of the two substrates; and the active element formed in the first step. For the drive electrode, a signal line for coupling with the outer peripheral portion of the substrate is formed using a conductive electrode film, and a mounting terminal coupled to the signal line is formed on the outer peripheral portion of the substrate with the electrode film. A second step of forming an interlayer insulating material film on the electrode film formed in the second step; and an interlayer insulating material formed in the third step. For the membrane,
A fourth step of performing exposure and development processing by an exposure machine using the photomask according to claim 1, a fifth step of forming a pixel electrode material film after the fourth step, and a fifth step A photosensitive resist is applied to the pixel electrode material film formed by the above, exposed and developed using a resist mask, connected to a specific drive electrode of the active element, and a drive voltage is applied to the liquid crystal. And a sixth step of forming a given pixel electrode. 5. The thin film transistor according to claim 4, wherein the active element is a thin film transistor, and the contact hole of the interlayer insulating film obtained in the fourth step communicates with a drain electrode of the thin film transistor. Method for manufacturing an active element array substrate. 6. The method according to claim 4, wherein the interlayer insulating film used in the third step is a photosensitive organic film. 7. The pixel electrode material film used in the fifth step is made of indium tin oxide.
A method for manufacturing the active element array substrate according to the above.