JP3086245B2 - Other system access designation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] In a configuration where a system in which a CPU, a main storage device, a channel device, and the like are connected to an internal bus is duplicated, each internal bus is used to realize communication between the two systems. With regard to another system access designation device in a duplex processor system provided with a bus crossing control device capable of transmitting and receiving mutual bus transfer information with an interface pulled in, the purpose of the present invention is to efficiently determine reception conditions in the duplex processor system. A system in which the CPU, main storage device, channel device, etc. are connected to the bus is duplicated.In order to realize communication between the two systems, each internal bus interface is pulled in, and mutual bus transfer information is transmitted and received. Transmitting to said internal bus in a duplex processor system with a possible bus crossing controller A system identification signal line indicating the identification of the system and the receiving system is provided, and the bus intersection control device receives the system identification signal and the own system number determined by the work order, and receives the bus transfer information of the bus intersection control device. A system determination circuit for determining a condition is provided, and a reception control is started on a crossing control unit that transfers data to another system based on the determination result of the system determination circuit.

[Industrial Application Field] The present invention has a dual configuration in which a CPU (central processing unit), a main storage device (MM), a channel device (DCH), and the like are connected to an internal bus. To realize communication, pull in each internal bus interface,
The present invention relates to a different-system access designating device in a duplex processor system provided with a bus crossing controller (BXC) capable of transmitting and receiving mutual bus transfer information.

In this type of system, it is necessary to always go through BXC, but since the internal bus is the same, without being aware of BXC, CPU
Can access MM and CPU of other systems.
In this case, it is desirable to access the MM and CPU of the other system as efficiently as possible.

[Prior Art] FIG. 5 is a conceptual diagram of a configuration of a conventional system. The system shown in the figure has a CPU (central processing unit) 1 and MM (main storage device)
2 system and a DCH (channel device) 3 connected to an internal bus 4, a system 0 system 10, and a CPU 11, an MM 12 and a DCH 13
4 and a first system 20 connected to each other via respective BXCs (bus crossing control devices) 5 and 15 to form a duplex system. Where CPU1, MM2 and DC
A system in which H3 is connected to the internal bus 4 is called a processor system. The same applies to the first system. In such a redundant system, the internal bus is the same, and the CPU can access another system MM or CPU without being aware of the BXC.

FIG. 6 is a diagram showing an example of a transfer format on the internal bus. The example shown in the figure is configured in units of 32 bits, and includes a control command A, an address B, and data C. The control command A includes a transfer destination device number 1a, a transfer source device number 2a, and a control order 3a. Here, as the control order 3a, for example, commands such as memory write, memory read, and return of read data are entered. Address B indicates an address in the data transfer destination device, and data C is normal data.

Transfer information including an identification number assigned to a device on the bus as shown in FIG. 6 as a transfer destination device number is transferred by a procedure as shown in FIG. 7 (split transfer method). CP
U interprets the control order in the control command from the control command and the address on the internal bus, reads the contents of the corresponding address in the memory (MM) (), and if read, returns the read data following the control command () . Where CP
If the MM accessed by U is another system, the sequence shown in the figure is performed via BXC. In this transfer procedure, information is received by identifying a transfer destination device number by a determination circuit on the device side.

As described above, a device connected to the internal bus when performing inter-processor communication is not aware of the BXC. However, the BXC constantly monitors the transfer information on the internal bus, determines whether the transfer information has been received, and relays it to another processor.

Regarding the BXC reception determination in the inter-processor communication, there are the following methods for performing the reception determination.

(1) The device identification number in the system is uniquely determined. Therefore, the BXC has a device number table for the devices on its own bus, and constantly monitors whether the transfer destination device number in the transfer information on the bus is a device on another bus.

(2) At least device identification numbers in the same system are uniquely determined. The device on the transmitting side sets the transfer destination device number to 0 along with the device identification number assigned to the device on the bus.
Set the system identification number of system or system. The BXC always monitors whether the communication is from the system identification number in the transfer destination device number in the transfer information on the bus to another system device.

FIG. 8 is a diagram showing a format example of a transfer destination device number according to the conventional method. In (a), only the device identification number is written in correspondence with the method (1). In contrast,
In the method shown in (b), the system identification number and the device identification number are written in correspondence with the method shown in (2). In each case, these data are stored in 8 bits.

FIG. 9 is a diagram showing an example of a conventional circuit configuration for determining a reception condition, which is a circuit for realizing the method (1). This circuit is contained within the BXC. In the figure, reference numeral 30 denotes a device number table in which uniquely determined device numbers are stored. Reference numeral 31 denotes a reception register for receiving device number data from the internal bus, and 32 denotes a collation circuit for collating both data by receiving the data read from the device number table 30 on one side and receiving the output of the reception register 31 on the other side. is there. The number of the matching circuits 32 is also n corresponding to the number of the device number table 30. A gate 33 receives the output of each matching circuit 32, and outputs a signal for activating the cross control circuit if at least one matching match is found.

Some of the circuits configured as described above have a match between the data read from the device number table 30 and the received data of the reception register 31, and only when the device number is a device number of another system. , Gate 33 activates the cross control circuit.

[Problem to be Solved by the Invention] In the case of the method described in (1) above, once registration is performed, the transmitting side device does not need to be aware of the system of the transfer destination device. However, system management is indispensable for registration / update of the device number table 30 held in the BXC, and there is a problem that the load on the processor is large.
Also, in the case of the method shown in (2), since the system identification number is included in the transfer information having a limited field length, there is a problem that the range of the device identification number is relatively reduced.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a different-system access designation device that can efficiently determine a reception condition in a duplex processor system.

[Means for Solving the Problems] FIG. 1 is a principle block diagram of the present invention. The same components as those in FIG. 5 are denoted by the same reference numerals. In the figure, 0
System is central processing unit (CPU) 1, main storage unit (MM)
2, Channel device (DCH) 3 and bus crossing controller (BXC)
The first system includes the CPU 11, the MM 12, the DCH 13, and the bus crossing controller (BXC) 40. Since the system 1 is exactly the same as the system 0,
Hereinafter, the system 0 will be described.

Reference numeral 4 denotes an internal bus, which comprises a data bus 4a composed of addresses and data and a system identification signal line 4b. The system identification signal line 4b is connected to a source identification signal and a destination identification signal.
It consists of different types of signal lines. The bus intersection control device 30 includes a system determination circuit 31 and an intersection control unit 32. The system determination circuit 31 determines the reception condition of the bus transfer information of the bus intersection control device 32 in response to the system identification signal and the own system number determined by the work order.

[Operation] The system determination circuit 31 has its own system number and system identification signal line
The reception condition of the bus transfer information of the bus intersection control device 30 is determined based on the transmission source identification signal and the reception destination identification signal from 4b. For example, the reception condition determination means that if the own system number is "0" and the destination system identification number is "1", it is determined that data transfer is necessary, and data is transferred to another system. The reception of the control unit 32 is started. As described above, according to the present invention, instead of including the system identification signal in the transfer information, the system identification signal is put on the bus, and the transmission side device refers to this signal when communicating with the other system, so that the BXC bus can be used. The receiving condition of the transfer information can be determined, and the receiving condition in the duplex processor system can be efficiently determined.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention, and shows an internal configuration of a bus intersection control device (BXC). 1 are denoted by the same reference numerals. 4c is a control signal line for transmitting a control signal such as a synchronization signal. Therefore, the internal bus 4 includes a data bus 4a, a system identification signal line 4b, and a control signal line 4c.

Reference numeral 31 denotes a system determination circuit that receives a transmission system identification signal, a reception system identification signal from the system identification signal line 4b, and an own system number as a work order, and determines reception conditions in the duplex processor system. G in the figure is a buffer. Reference numeral 32 denotes an intersection control unit that controls transmission and reception of data to and from another system, and includes an intersection control circuit 32a and a reception register 32b. Reference numeral 33 denotes a delay / differentiation circuit that receives the synchronization signal from the control signal line 4c and delays / differentiates to generate a pulse a. The gate. The output of the AND gate 34 is supplied to the intersection control circuit 32a as a start signal. The operation of the circuit configured as described above will be described below.

The system determination circuit 31 receives the source system identification signal, the destination system identification signal, and the own system number, constantly monitors the status of the internal bus 4, and determines the reception condition in the duplex processor system. A built-in system determination condition table is used to determine the reception condition.

FIG. 3 is a diagram showing a configuration example of a system determination condition table. As shown in the figure, there are four combinations of the source identification signal and the destination identification signal. For these combinations, determination is made as shown in the figure depending on whether the own system number is “0” system or “1” system. If the transmission source is “0” and the destination is “0”, the signal does not pass to other systems. Therefore, in this case, if the own system number is “1”, it is abnormal, and the system determination circuit 31 issues an abnormality notification. If the own system number is "0", it is ignored.

Next, when the transmission source is “0” and the reception destination is “1”, if the own system number is “0”, it indicates data transmission to another system. At this time, information is received. Transmit to other systems. Therefore, the system determination circuit 31 outputs a reception designation signal. The AND of the reception designation signal and the output pulse of the delay / differentiation circuit 33 is given to the cross control circuit 32a as a start signal. The intersection control unit 32a passes the data (control order, address, data) received by the reception register 32b to another system.

Next, the source is “0”, the destination is “1”, and the own system number is “1”.
In this case, since the numbers of the transmission systems do not match, an abnormality occurs and the system determination circuit 31 issues an abnormality notification. Next, when the transmission source is “1” and the reception destination is “0”, the system determination circuit of the first system performs the system determination, and when the own system number is “0”, an abnormality notification is issued. When the system number is “1”, the reception processing as described above is performed. When both the transmission source and the reception destination are "1", the data is transferred within the own system. When the own system number is "0", an error notification is issued, and when the own system number is "1", it is ignored. I do. As described above, according to the present invention, the reception condition determination in the duplex processor system can be efficiently performed, and an error in system designation can be detected at an early stage.

FIG. 4 is a time chart showing the operation of each part of the circuit shown in FIG. (A) is a clock signal c and a control signal line
Given from 4c. (B) is a synchronization signal, which is also supplied from the control signal line 4c. (C) is the data on the data bus 4a, (d) is the output a of the delay / differentiation circuit 33, (e) is the reception designation signal which is the output of the system determination circuit 31, and (f) is the output of the AND gate 34. There is a certain start signal.

The control order is placed on the data bus 4a in synchronization with the clock c.
Signals are placed in the order of address and data. On the other hand, the delay / differentiation circuit 33 delays the synchronization signal shown in (b) and differentiates it to produce a pulse as shown in (d). Here, when the system determination circuit 31 outputs a "1" level reception designation signal as shown in FIG. 9E due to the satisfaction of the reception condition, the pulse a passes through the AND gate 34, and the start signal as shown in FIG. And activates the intersection control circuit 32a. In response to this start signal, the cross control circuit 32a transfers the data (control order, address, data) coming in through the reception register 32b to another system.

Although the operation of the “0” system has been mainly described above, the operation of the “1” system is exactly the same.

[Effects of the Invention] As described above in detail, according to the present invention, the system determination circuit 31 determines the own system number and the transmission source system identification signal and the reception destination system identification signal from the system identification signal line 4b by construction. Based on this, the reception condition of the bus transfer information of the bus intersection control device 30 is determined, and a system identification signal is put on the bus instead of including the system identification signal in the transfer information. By referring to the signal, the reception condition of the BXC bus transfer information can be determined, and the influence on the accommodation range of the device identification number can be eliminated, and the reception condition determination in the duplex processor system can be efficiently performed. be able to. Also,
According to the present invention, by providing a system determination table as shown in FIG. 3 in the system determination circuit 31, a system identification signal indicating the identification of the transmission source system and the reception destination system, and the own system number by construction work Therefore, an error in system designation can be detected at an early stage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing an example of the configuration of a system determination condition table, and FIG. 5 is a time chart showing the operation of each unit, FIG. 5 is a conceptual diagram of the configuration of a conventional system, FIG. 6 is a diagram showing an example of a transfer format on an internal bus, FIG. FIG. 9 is a diagram showing an example of a format of a transfer destination device number according to a conventional method, and FIG. 9 is a diagram showing an example of a circuit configuration for determining a reception condition. In FIG. 1, 1 and 11 are a CPU, 2 and 12 are main storage devices, 3 and 13 are channel devices, 4 is an internal bus, 4a is a data bus, 4b is a system identification signal line, 30.40 is a bus crossing control device, 31 and 41 are system determination circuits, and 32 and 42 are intersection control units.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshiaki Wakimura 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Tadayoshi Komachiya 1-16-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-61-173365 (JP, A) JP-A-61-292769 (JP, A) JP-A-2-153436 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/18-11/20 G06F 13/00-13/378 G06F 15/16-15/177

Claims (2)

(57) [Claims] A system in which a CPU (1), a main storage device (2), a channel device (3), and the like are connected to an internal bus (4) is duplicated to realize communication between the two systems. For this purpose, the bus crossing control device (30) capable of receiving each internal bus interface and transmitting and receiving mutual bus transfer information
In the duplex processor system, a system identification signal line (4b) for identifying a source system and a destination system is provided on the internal bus (4), and the system identification signal is provided in a bus intersection control device (30). The bus intersection control device (3
A system determination circuit (31) for determining the reception condition of the bus transfer information of (0) is provided, and an intersection control unit (32) for transferring data to another system based on the determination result of the system determination circuit (31). ) Is configured to start the reception. 2. The system determination circuit (31), when determining the receiving condition, detects a system designation error from a system identification signal indicating the identification of a transmission source system and a reception destination system and a self-system number by construction. 2. The other-system access specification device according to claim 1, wherein the detection can be performed at an early stage.