JP3084567B2 - Lock control circuit for 2-wire electric lock - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a lock control circuit for a two-wire electric lock.

[Prior Art] This type of two-wire electric lock supplies a multiplexed signal in which a lock processing voltage is superimposed on a control pulse for locking and unlocking a signal processing unit, and the signal processing unit is connected to a capacitor side from the signal processing unit. Is configured to supply the drive voltage to charge the capacitor,
As shown in FIG. 7, when the locking and unlocking signals are sent, the lock control circuit closes the switching means S and discharges the charging voltage VC of the capacitor C to the solenoid L connected with the diode D in parallel. The lock is configured to be locked and unlocked. When a lock operating device is operated to send a lock / unlock signal to the signal processing unit, the signal processing unit (not shown) is shown in FIG. 8A). As described above, a multiplex signal Vin in which a control pulse of 24 V and a lock driving voltage of 24 V are superimposed on a reference voltage of 12 V is supplied. The multiplexed signal Vin is decoded by a control signal discriminating circuit (not shown). The lock driving voltage is supplied to turn on the switching means (see FIG. 8 (c), the electric charge (see FIG. 8b) stored in the capacitor C) is supplied to the lock solenoid L side to perform the control. It has become.

[Problems to be Solved by the Invention] However, in such a conventional control circuit for an electric lock, charging takes a long time because a large-capacity capacitor is charged through a current-limiting resistor. It takes time to increase the voltage in the latter half of charging, and there is a problem in that if the charging is to be accelerated, the rush current at the start of charging increases.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem that a lock control circuit of a two-wire electric lock has, and it is an object of the present invention to provide a two-wire electric lock capable of suppressing inrush current to a capacitor and accelerating charging. It is intended to provide a lock control circuit.

[Means for Solving the Problems] To achieve the above object, the present invention proposed in claim 1 is to provide a current limiting circuit between a signal processing unit and a capacitor and a charging voltage of the capacitor to a predetermined level. A DC-DC converter for boosting the voltage and a switching means for shutting off the power supply different from the switching means for turning on and off are provided, and the switching means for shutting off the power supply is closed only during the charging period of the capacitor.

Further, the present invention proposed in claim 2 is a current limiting switching circuit comprising a combination of a constant current limiting transistor and an ON / OFF controllable FET between a signal processing unit and a capacitor; It is characterized in that a DC-DC converter for raising the charging voltage of the capacitor to a predetermined level is provided.

According to the lock operation circuit of the two-wire electric lock of the present invention,
In both cases, the inrush current in the initial stage of charging the capacitor is suppressed by the current limiting function, and the charging current to the capacitor is controlled by the DC-DC converter at a constant current, so that the charging voltage to the capacitor can be changed freely. it can.

Also, in addition to the above operation, when discharging the capacitor,
Since the system power supply is shut off, the system power supply is not overloaded.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a basic configuration of a two-wire electric lock system, and FIG. 2 shows a configuration of a lock control circuit.

In these figures, 1 is a signal processing unit, 2 is a current limiting circuit, 3 is a DC-DC converter, and a large-capacity capacitor C is provided on the output side of the DC-DC converter 3. Two solenoids SLA and SLB for blocking and unlocking are connected in parallel to diodes DA and DB for surge absorption via SA and SB.

In such a configuration, by operating the unlocking / locking switch (not shown) of the lock, the signal terminals P1-P2 of the system receive the reference voltage signal 12V, the control pulse of 24V and the lock drive voltage of 24V. A multiplexed signal Vin as shown in FIG. 3a) is transmitted, and the capacitor C has a predetermined voltage level Vco.
(See FIG. 3b)), the switching means SA or SB is turned on (see FIG. 3d)).
The solenoid SLA or SLB is energized and driven by the charging voltage of the capacitor C.

The switching means SA and SB separate the control pulse from the multiplexed signal Vin supplied to the signal terminals P1-P2 of the system and detect it by the control signal determination circuit 5 to determine whether the lock is locked or unlocked. For this purpose, an AC signal indicating the distinction between locking and unlocking is superimposed on the multiplexed signal Vin by the lock state detecting unit added to the lock and is discriminated by the lock state discriminating circuit 4 and the signal processing unit 1 To be sent to The signal processing unit 1 determines whether the lock is locked or unlocked based on the determination signal from the lock state determination circuit 4, and outputs a control signal determination circuit 5.
When a lock / unlock command signal is sent, the necessary switching SA and SB are turned on.

According to the lock control circuit having such a configuration, it is possible to prevent the occurrence of an inrush current at the time of starting charging of the large-capacity capacitor C required for driving the solenoid, and furthermore, the boost operation of the DC-DC converter 3 Since the capacitor C is charged by a constant current, the large-capacity capacitor C for driving the lock solenoid can be charged quickly and quickly, and the charging completion voltage VC0 of the capacitor C can be easily changed.

Further, in this lock control circuit, a switching means S0 for shutting off the power supply different from the switching means SA and SB on the lock solenoid side is provided between the system power supply from the signal processing unit 1 and the current limiting circuit 2. The switching means S0 for shutting off the power supply is turned on only when the capacitor C is charged (see FIG. 3C).

That is, the signal processing unit 1 determines whether the lock is locked or unlocked based on the determination signal of the lock state determination circuit 4. In addition to the switching means SA and SB, the switching means S0 is also turned on.

FIG. 4 shows another example of the lock control circuit. In this lock control circuit, a DC-DC converter 3 'having a current limiting function having a built-in current limiting circuit is used. A switching means S0 for power cut-off different from the switching means SA and SB on the lock solenoid side is provided between the DC converter 3 ', and the switching means S0 for power cut-off is connected to the capacitor C. Is turned on only when charging is performed.

According to the lock control circuit having such a configuration, an inrush current at the start of charging the capacitor C can be prevented by the current limiting circuit built in the DC-DC converter 3 '. The capacitor C is rapidly charged by constant current charging. In addition, the switching means S0 is turned on only during the period until the charging of the capacitor C is started and reaches the charging completion voltage Vco preset by the DC-DC converter 3, so that the lock solenoid SL
When power is supplied to A and SLB, the capacitor C is disconnected from the system power supply.

Therefore, when such switching means S0 is not provided, the occurrence of the inrush current I 'as shown in FIG. No overload.

Such a lock control circuit is particularly useful for a lock system in which the current limit level of the current limit circuit 2 cannot be suppressed so much as to accelerate charging of the capacitor C. 3 (a) to 3 (f) show the operation of the lock control circuit with a time chart.

 FIG. 5 shows a basic configuration of the second invention.

In the figure, only one lock solenoid L is shown for the purpose of explaining the principle, but the feature of this lock control circuit is that a resistor is provided between the system power supply of the signal processing unit 1 and the capacitor C.
The present invention is characterized in that a current limiting switching circuit is configured by combining a constant current limiting transistor TR in which R1 and R2 are connected as shown in the figure and an FET1 capable of on / off control. Similarly, the DC-DC converter 3 is configured to increase the charging voltage of the capacitor C to a predetermined level. The signal processing unit determines whether the lock is locked or unlocked based on a determination signal from a lock state determination circuit, and controls the signal. The necessary switching SA, SB and S0 are turned on when a signal for designating locking / unlocking is sent by the signal determination circuit. Here, the FET 1 starts charging the capacitor C and is turned on only during the charging period until the charging is completed. The charging of the capacitor C is discharged by the FET 2.

According to the lock control circuit having such a configuration, the current I flowing from the system power supply into the current limiting transistor TR is I =
If VBER1 (here, VBE is the base-emitter voltage of the transistor TR) is exceeded, FET1 is turned off.
The converter 3 has a current limiting function to control the current supplied to the DC-DC converter 3.

As a result, at the start of charging of the capacitor C, after the current limited to a certain level shown in FIG.
Until the constant current charging is completed by the step-up action of the DC-DC converter 3, a further suppressed level of current flows into the DC-DC converter 3.

Then, after the capacitor C reaches the charging completion voltage Vco, the FET 1 is turned off to cut off from the system power supply, and the FET 2
Is turned on, the charging voltage of the capacitor C is discharged to the solenoid L to lock and unlock.

 FIGS. 6 (a) to 6 (d) show the above operation.

[Effects of the Invention] According to the lock control circuit for a two-wire electric lock of the present invention, the rush current in the initial stage of charging the capacitor is suppressed, and the DC
-The charging current to the capacitor is controlled by the DC converter at a constant current so that the charging voltage to the capacitor can be changed freely, so that it is possible to cope with lock solenoids having different driving forces.

In addition, since the system power supply can be cut off at the time of discharging the capacitor, in addition to the above effects, the system power supply is not overloaded.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a two-wire lock control circuit including a lock control circuit of the first invention, FIG. 2 is a configuration diagram of a lock control circuit of the first invention, and FIG. FIG. 4 is a block diagram showing another example of the lock control circuit according to the first embodiment of the present invention, and FIG.
6 is a block diagram of the lock control circuit of the present invention, FIG. 6 is an explanatory diagram of its operation, FIG. 7 is a block diagram of a conventional lock control circuit, and FIG. 8 is an explanatory diagram of its operation. (Explanation of symbols) 1 ... Signal processing unit 2 ... Current limiting circuit 3 ... DC-DC converter SA, SB ... Switching means C ... Capacitor SLA, SLB ... Solenoid S0 ... Power supply switching means TR …… Constant current control transistors FET1, FET2 …… Transistors that can be turned on and off

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) E05B 47/00 H02H 3/087 H02H 9/02 H02J 1/00 306 H02J 13/00 311

Claims (2)

(57) [Claims] A multiplexed signal in which a control pulse and a lock driving voltage are superimposed on a signal of a reference level is supplied to a signal processing unit, and the signal processing unit supplies a lock driving voltage to a capacitor. A lock control circuit for a two-wire electric lock, wherein the switching means is turned on to supply the charging voltage of the capacitor to the lock solenoid, wherein a current limiting circuit is provided between the signal processing unit and the capacitor; A DC-DC converter for boosting the charging voltage of the capacitor to a predetermined level; and a switching means for shutting off the power supply different from the switching means for turning on and off the power supply. A lock control circuit for a two-wire electric lock that is configured to be closed only. 2. A multiplexed signal in which a control pulse and a lock driving voltage are superimposed on a signal of a reference level is supplied to a signal processing unit, and the signal processing unit supplies a lock driving voltage to a capacitor, and performs a locking and unlocking operation. In a lock control circuit of a two-wire electric lock in which the switching means is turned on and the charging voltage of the capacitor is supplied to the lock solenoid, a constant current limiting transistor is provided between the signal processing unit and the capacitor. , A current-limited switching circuit combining FETs capable of on / off control, and a DC-DC for boosting the charging voltage of the capacitor to a predetermined level
A lock control circuit for a two-wire electric lock, comprising a converter and a converter.