JP3083786B2 - Memory update history storage device and memory update history storage method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory update history storage device and a memory update history storage method for storing update history information of a main memory necessary for realizing a memory state recovery function for restoring the contents of a main memory of a computer system. .

[0002]

2. Description of the Related Art In a normal computer system, once a program is executed, once the process proceeds,
It is generally not possible to return to an earlier state and resume processing.

However, in the following various applied technologies, it is desired to have a function of returning the contents of the memory to the previous state and continuing the processing from that point (memory state recovery function).

[0004] If any error occurs during execution of the software debugging program, the cause of the error can be analyzed by going back to the previous state.

Fault Tolerant System When processing cannot be continued due to some kind of failure during the operation of the system, it is possible to continue the operation without stopping the system by returning to the previous state and restarting the processing therefrom. it can.

[0006] Such a fault-tolerant technique is:
For example, Philip A Bernstein, “Sequoia: A Fault-Tolera
nt Tightly Coupled Multiprocessor for Transaction
Processing, "IEEE Computer, Vol. 21, No. 2, 1988.

Backtracking In a logic programming language, backtracking of the execution state is a basic operation. By using the function of returning the contents of the memory to the previous state, back tracking can be realized.

One of the techniques considered as a method for realizing the memory state recovery function as described above is a "backward method". Such techniques are, for example, Rok Sosi
c, “History Cache: Hardware Support for Reverse E
xecutrrion, ”Computer Architecture News, Vol.22, N
o.5, 1994.

FIG. 6 shows a configuration of a typical conventional computer system required to realize a memory state recovery function using the "backward method". FIG.
In this system, N CPUs 31 to 32 and N caches 41 to 42 corresponding to each CPU are provided. The caches 41 to 42 are connected to the memory control unit 60 via the bus 50.

The memory controller 60 is connected to the main memory 70 and the before image buffer 80, and controls access to the main memory 70 and the before image buffer 80. Before image buffer 8
0 is for storing update history information including a pair of pre-update data of the main memory 70 and its address.

When a write request to the main memory 70 is issued, the memory control unit 60 reads the pre-update data to be written from the main memory 70 prior to the actual write access to the main memory 70 and associates the read data with the read data. Is written to the before image buffer 80.

With this configuration, when a failure occurs, the contents of the main memory 70 can be restored to the state before the failure only by writing back the update history information of the before image buffer 80 to the main memory 70. Become.

[0013]

However, in this method, the memory control unit 60 has a before image buffer 8
An existing memory controller is used because it is necessary to incorporate a buffer access control function for controlling access to 0 and a state saving control function for controlling various functions necessary for saving the state of the main memory 70. And a new memory controller must be developed. Therefore, it is practically difficult to realize the memory state recovery function by diverting the existing computer system as it is.

According to the present invention, a memory update history storage device and a memory update history storage device capable of easily realizing a memory state recovery function by diverting an existing computer system without modifying a memory control unit of the existing computer system. The aim is to provide a method.

[0015]

SUMMARY OF THE INVENTION The present invention provides a cache
At least one CPU with or without
And read / write control connected to this main memory.
Memory controller and the cache or CP
U and a bus connected to the memory controller
A computer system, wherein the computer system
In the event of a system failure, the contents of the main memory are
Memory update to save update history information necessary for restoration
In the new history storage device, the contents stored in the main memory and
And the update history information as a set of the storage address
Buffer connected to the buffer and the bus.
And monitor transactions issued to the bus.
The write access to the cache by the CPU.
A cache request from the cache or CPU
In response to a write transaction output to the bus
Therefore, writing to the corresponding address of the main memory is not possible.
Before the operation is performed, the above storage contents are read from the storage address.
A read transaction through the bus
Buffer access control for outputting to the memory controller
And control means .

In this memory update history storage device, buffer access control means is provided separately from the memory controller, and it is connected to the bus. The buffer access control means does not operate when a write access request to the main memory is sent to the memory controller. Transactions to be issued, for example, data in main memory for a write-through cache
Copy transactions such as write transactions
Bakku invalidation transactions to instruct disabling (write back) type of the corresponding cache line to other caches that may be connected to the bus if a cache
Etc., to operate automatically in response to. When these Toranzakushi <br/> ® emission is detected, the buffer access control means, its
By using an address specified by these transactions, a read transaction for reading data on the main storage, which is the target of the write access request, is issued on the bus. Then, the data read from the main memory to the bus by the memory controller in response to the read transaction and the address corresponding to the data are written into the buffer by the buffer access control means.

As described above, by providing the buffer access control means which can operate independently of the memory controller, the existing computer system can be easily used without modification without modifying the memory controller of the existing computer system. It is possible to realize a memory state recovery function.

Since data before updating is collected not when writing data to the main memory but when writing data to the cache, when applied to a system using a system recovery method by checkpoint rollback, At the time of a checkpoint, it is only necessary to write the update data held in the cache to the main memory, and it is not necessary to save the pre-update data in the buffer at this point, so that the overhead of the checkpoint process can be reduced.

Further, the buffer access control means may be arranged so that a transaction issued from a cache reads data from a corresponding cache line of a main memory or another cache which can be connected to a bus, and a corresponding cache line of another cache. If the transaction is a read or invalidation transaction that instructs invalidation, the transaction is not issued on the bus, and the data and corresponding address read on the bus by the cache read and invalidation transaction are used as is. And store it in a buffer.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention.

As shown in FIG. 1, the computer system according to the present embodiment has N CPUs (processors) 14 to 1.
5. N caches 17 to 18 corresponding to each CPU are provided. The caches 17 and 18 include a memory control unit 20 and a before image buffer control unit 21.
Are connected via a bus 16.

The memory controller is a normal memory controller for controlling access to the main memory 12. The before image buffer control unit 21 controls the before image buffer 13 that stores a set of the pre-update data of the main memory 12 and its address in a stack format, and includes a bus interface control unit 211, a state storage control unit 212, a bus transaction response control unit 213, a buffer access control unit 214, and a bus transaction issuance control unit 215.

The bus interface control section 211 is directly connected to the bus 16 and controls the bus and snoops (monitors bus transactions). That is, the bus interface control unit 211 constantly monitors the bus 16 and operates according to the transaction issued to the bus 16. The state storage control unit 212 controls various functions necessary for storing the state of the main memory 12. The bus transaction response control unit 213 controls a function of returning a response to a transaction issued to the bus 16. The buffer access control unit 214 is connected to the before image buffer 13 and controls access to the before image buffer. The bus transaction issuance control unit 215 controls a function of issuing a bus transaction necessary for storing the state of the main memory 12 in the before image buffer 13.

The caches 17 and 18 are copy-back type caches, and implement a protocol for maintaining data consistency according to a method described below.
These caches 17 and 18 respectively have a corresponding CP.
If the U (processors) 14 to 15 have a primary cache, they function as secondary caches. Further, the caches 17 and 18 themselves may be built in the corresponding CPU.

Each of the caches 17 and 18 has a data memory for holding cache line data and a tag memory for holding information for managing each cache line data stored in the data memory.

FIG. 2 shows an example of the tag memory. The tag memory stores an address tag indicating the cache line address (ADDR) of the corresponding cache line data, and 3-bit data indicating the state of the cache line data. The state of the cache line data is valid (V: Valid), modified (M: Modi).
, and shared (S: Shared) are managed by a combination of 3-bit values. The valid (V) indicates that the corresponding cache line data is valid (“1”). Modified (M)
Indicates that the cache has been updated.
Shared (S) indicates that the same cache line data is held in the cache of another processor. Modified (M) indicates that the cache has been updated. Shared (S) indicates that the same cache line data is held in the cache of another processor. Due to the combination of these three bit values, as shown in FIG. 3, the cache line data takes four states: invalid, clean exclusive, clean shared, and modified.

The bus transactions associated with the copy back cache include the following. "Read-Line": Read transaction of cache line data from the main memory to the cache. This is issued when a valid cache line data does not exist in the cache and a cache miss occurs in response to a read access to a cache line at a certain address from the CPU.

A cache miss indicates that the address indicating the cache line data to be accessed is not stored in the tag memory, and that the address is stored but the valid bit (V) is invalid ("0"). This is the case. On the other hand, a cache hit occurs when the address of the target cache line data is stored in the tag memory and the valid bit (V) indicates valid ("1").

"Read-Line-with-In"
validate "... Reads cache line data from the main memory to the cache and invalidates the data stored in other caches.
Issued when a cache miss occurs in response to a write access from the CPU. That is, when a cache miss occurs due to a write access from the CPU, it can be expected that inconsistency will occur at that time with another cache holding the same cache line data. This is because the cache line data to be written is rewritten after the cache memory is refilled from the main memory into the cache. Therefore, CP
When a cache miss occurs in response to a write access from U, a transaction is executed to simultaneously instruct to read cache line data and invalidate data stored in another cache.

"Write-Line": A write transaction of cache line data from the cache to the main memory. This is because when the cache line data is explicitly written to the main memory 12 in accordance with an instruction from the CPU, when it is necessary to replace the cache line data and the update data is written to the main memory 12, and when the request from another CPU is received. Update data according to the main memory 1
Issued when writing to 12.

"Invalidate": A transaction for invalidating data stored in another cache.
This is issued in response to a write access from the CPU when the line exists in the cache but is clean shared. Clean Shared
The same cache line data exists in another cache, and these cache line data have the same value. In this transaction, an address indicating the cache line data to be invalidated is transferred, and no data transfer is performed.

In addition, the following bus transaction is supported.・ "Read-Line-none-Snoop" ...
The other caches do not snoop, and the memory control unit always responds and reads the line data from the main memory. In this embodiment, it is not issued from the processor cache.

It is to be noted that the transaction is often supported in addition to the transaction described above, but the description is omitted because it is not directly related to the following description. Also, the cache 17
In the case where .about.18 are incorporated in the corresponding CPUs, the above-mentioned transactions are issued by the CPUs themselves.

The bus 16 is composed of a processor bus capable of supporting a multiprocessor configuration, and includes a shared response signal line 161, a modified response signal line 162, a bus command signal line 163, an address /
The data signal line 164 is included. Generally, it also includes a signal line for performing arbitration in addition to the above, but since it does not directly relate to the following description, the description is omitted.

The shared response signal line 161 (share)
d) is used to notify a transaction issued by another CPU / cache that the cache line data targeted by the transaction is held, that is, shared.

The modified response signal line 162 (mod
Effied) is used to notify a transaction issued by another CPU / cache that the cache line data targeted by the transaction is held in an updated state. When this signal is asserted, the transaction is aborted. Thereafter, the slave that has aborted the transaction acquires the bus and then writes the updated cache line data to the memory. On the other hand, the master that issued the first transaction acquires the bus again,
Issue the same transaction.

Note that these two signal lines 161 and 1
Similarly, when 62 is asserted simultaneously, the transaction is aborted. Bus command signal line 16
3 (command) indicates the type of the bus transaction described above, and is used for sending various information related to the transaction.

Address / data signal line 164 (addr
ess / date) is a signal line for transmitting the address and data of the cache line data targeted by the bus transaction. In FIG. 1, they are collectively shown, but there are a method of using a common signal line in a time-division manner and a method of providing an independent signal line for each address / data.

Next, the operation of the multiprocessor system shown in FIG. 1, that is, how the data consistency maintaining protocol between caches is realized using the above-described bus transaction will be described.

Here, a CPU and a cache (master processor) on the side that issues a transaction and activates access, another CPU and a cache (slave processor) operating on a transaction issued by a certain CPU / cache, and a memory Control unit 2
0 and the operations of the before image buffer control unit 21 will be described. (1) Master Processor First, the operation of the master processor that issues a transaction to start access and the state transition of the cache corresponding to the issued transaction will be described.
The master processor is the CPU 14 (cache 1
7).

Read access (cache hit):
If a cache hit occurs in the cache 17 as a result of the read access request from the CPU 14, the cache 1
7, the corresponding data is read. The CPU 14 (cache 17) does not issue a transaction to the bus 16. At this time, the state of the cache line does not change.

Read access (cache miss): C
As a result of the PU 14 requesting a read access, the cache 1
If a cache miss occurs in 7, the CPU 14 (cache 17) issues a “Read-Line” transaction to the bus 16.

On the other hand, if the modify response signal is asserted via the modify response signal line 162, one of the other caches holds the update data of that line. Cache 17
Reads the cache line data written to the main memory 12 from the cache in which the modified response signal is asserted, and stores it in the data memory of the cache 17. The state of the cache line is “clean shared”.

On the other hand, if the modified response signal is not asserted and the shared response signal is asserted via the shared response signal line 161, another cache is holding the line in a clean state. The cache 17 sets the state of the cache line to “clean shared”, takes in the data read from the main memory 12, and stores the data in the data memory.

If neither the modified response signal nor the shared response signal is asserted, it means that no cache line holds the target cache line. The cache 17 sets the state of the cache line to “clean exclusive”.
Also in this case, the cache 17 takes in the data read from the main memory 12 and stores it in the data memory.
However, as will be described later, this method is controlled so as to avoid the clean exclusive state, so that this condition does not actually exist.

In any case, the cache 17 stores the bus 1
The required data among the cache line data fetched from 6 is returned to the CPU 14. -Write (cache hit / modify): CP
As a result of the write access request from U14, the cache 17
In the case where a cache hit has occurred and the corresponding cache line data is in a modified state, the data is written to the corresponding cache line. The CPU 14 (cache 17) does not issue a transaction to the bus 16. At this time, the state of the cache line does not change.

Write (cache hit / clean exclusive): As a result of a write access request from the CPU 14, a cache hit occurs in the cache 17,
If the corresponding cache line data is in a clean exclusive state, the data is written to the corresponding cache line. The CPU 14 (cache 17)
No transaction is issued to the bus 16. The cache 17 changes the state of the corresponding cache line to “Modified”. However, as will be described later, this method is controlled so as to avoid the clean exclusive state, so that this condition does not actually exist.

Write (cache hit / clean shared): As a result of a write access request by the CPU 14, a cache hit occurs in the cache 17, and when the corresponding cache line data is in a clean shared state, the CPU 14 (cache 17)
Issue an “Invalidate” transaction. Thereafter, the cache 17 changes the state of the corresponding cache line to “modify” and writes data.

Write (cache miss): CPU 14
As a result of a write access request, if a cache miss occurs in the cache 17, a "Read-L"
issue an "ine-with-Invalidate" transaction.

On the other hand, if the modified response signal is asserted, one of the other caches holds the update data of the line. Thereafter, the cache 17 reads the cache line data written to the main memory 12 from the cache that has asserted the modified response signal, and stores it in the data memory.

On the other hand, if the modified response signal is not asserted, the cache 17 takes in the data read from the main memory 12 and stores it in the data memory. In either case, the state of the corresponding cache line is set to “Modified” and data is written. (2) Slave Processor The operation and state transition of another processor and the corresponding cache (slave processor) for a transaction issued by a certain processor / cache will now be described. The master processor is the CPU 14
(Cache 17), the slave processor is the CPU 15
(Cache 18), and will be described for each transaction issued from the master processor.

Response to "Read-Line" transaction: The cache 18 stores the "Read-Line"
When the cache line data targeted by the “ne” transaction is held in a “modified” state, a modified response signal is asserted via the modified response signal line 162 to notify that the updated data is held. Thereafter, the cache 18 stores “W
write-line "transaction to write the updated data to the main memory 12. The cache 18
The state of the corresponding cache line is set to “clean shared”.

The cache 18 stores "Read-L"
When the cache line data targeted by the “ine” transaction is held in the “clean exclusive” or “clean shared” state, the shared response signal is asserted via the shared response signal line 161 to generate the clean data. In any case, the cache 18 sets the state of the corresponding cache line to “clean shared”.

When the cache 18 does not hold the corresponding valid cache line data, it does nothing.・ "Read-Line-with-Invalida"
Response to "te" transaction: cache 18
Is "Read-Line-with-Invalid
When the cache line data targeted by the “ate” transaction is held in a “modified” state, a modified response signal is asserted via the modified response signal line 162 to notify that the updated data is held. Thereafter, the cache 18 stores “W
write-line "transaction to write the updated data to the main memory 12. The cache 18
The state of the corresponding cache line is set to “invalid”.

The cache 18 stores "Read-L"
When the cache line data targeted by the “ine-with-Invalidate” transaction is held in a “clean exclusive” or “clean shared” state, the state of the corresponding cache line is set to “invalid”.

When the cache 18 does not hold the corresponding valid cache line data, it does nothing. Response to “Invalidate” transaction: When the cache 18 holds the cache line data targeted by the “Invalidate” transaction in the “clean exclusive” or “clean shared” state, the cache 18 changes the state of the corresponding cache line to “clean exclusive” or “clean shared”. Invalid.

If the cache 18 does not hold the corresponding valid cache line data, it does nothing. In this case, the corresponding line cannot be held in the “modified” state.

Response to "Write-Line" transaction: Cache 18 does nothing. -Response to "Read-Line-one-Snoop" transaction: Cache 18 does nothing. (3) Memory Control Unit The memory control unit 20 performs the following operation for each bus transaction.

Response to “Write-Line” transaction: “Write-Line” issued on bus 16
When the “Line” transaction is snooped, the memory control unit 20 fetches the cache line data written out from the cache and writes the data to the corresponding address of the main memory 12.

Response to "Invalidate" transaction: do nothing. "Read-Line", "Read-Line-w"
Response to "is-Invalidate" transaction: The memory control unit 20 performs the same operation for these two transactions.

If the modified response signal is asserted for these transactions, nothing is done. This indicates that the cache of the asserted slave processor already holds the updated data. In this case, following these transactions,
A “Write-Line” transaction is issued from this cache, and the updated data is written out.

On the other hand, when the modified response signal is not asserted, the cache line data is read from the memory location indicated by the address of the cache line to be accessed, and is output to the bus 16.

"Read-Line-none-Sn"
Response to "oop" transaction: read cache line data from the memory location indicated by the address of the cache line to be accessed, and output it to bus 16. (4) Before image buffer controller Next, before image processing for each bus transaction The operation of the image buffer control unit 21 will be described below.
6 will be described.

Response to “Read-Line” transaction: When the bus interface controller 211 snoops the “Read-Line” transaction issued to the bus 16, the state storage controller 212 activates the bus transaction response controller 215. I do. The bus transaction response control unit 215 asserts a shared response signal via the bus interface control unit 211. As a result, the state of the cache line currently targeted for the cache of the master processor can be changed to “clean shared” instead of “clean exclusive”. As a result, when a write access occurs to the cache line thereafter, an "Invalidate" transaction can be issued, and the data before update can be stored.

If there is a method of avoiding the “clean exclusive” state as a function of the processor and the cache, the before image buffer control unit 2
1 does not need to assert the shared response signal.

Response to “Invalidate” transaction: When the bus interface control unit 211 snoops the “Invalidate” transaction issued to the bus 16, the state saving control unit 212
Activates the bus transaction response control unit 215. The bus transaction response control unit 215 asserts the shared response signal and the modified response signal via the bus interface control unit 211. As a result, the "Invalidate" transaction is aborted, after which the master processor
After acquiring the bus again, reissue the same transaction.

Bus transaction response control unit 215
Will be reissued until the following process is completed.
Assert the shared response signal and the modified response signal for the "alidate" transaction and continue to abort.

The state storage control unit 212 activates the bus transaction issuance control unit 215. The bus transaction issuance control unit 215 obtains “Read” for the memory location indicated by the address of the cache line to be invalidated obtained via the bus interface control unit 211 in order to obtain the cache line data before update.
Issue a "Line-non-Snoop" transaction.

Further, the state saving control unit 212 activates the buffer access control unit 214, and transfers the cache line data read from the main memory 12 by the memory control unit 20 and output to the bus 16 to the bus interface control unit 211.
Is transferred to the buffer access control unit 214 and written into the before image buffer 13 together with the address value.

When this process is completed, the bus transaction response control unit 215 sends the reissued “Invali
Further, the abort for the “date” transaction is stopped.The state saving control unit 212 stores the address of the cache block on which the above processing has been performed, and thereafter, when the “Invalidate” transaction for the same address is issued again, ignore.

FIG. 4 shows this “Invalidate”
The operation timing of response processing to a transaction is shown. Bus transaction issuance control unit 215
When the “Invalidate” transaction is confirmed, the pre-update data (D1 to D4) of the address (A) is read from the main memory 12 using the address (A) at that time.
"Read-Line-non-Sn" for reading
In this case, each cache memory does not perform a snoop operation on the transaction.

The memory control unit 20 reads “Read-Lin
In response to the “e-non-Snoop” transaction, a memory address line (MM address) and a data line (M
M data), read / write control line (MM RA)
S #, CAS #, WE #) from the address (A) of the main memory 12 to the cache line data (D1 to D
4) and read it out to the data bus (dat
a bus).

On the other hand, before image buffer control unit 2
In (1), the address (A) is also passed to the buffer access control unit 214. Buffer access control unit 214
Controls an address line (BIB address), a data line (BIB data), and a read / write control line (BIB RAS #, CAS #, WE #) provided between the image buffer 13 and the before image buffer 13.
The address (A) and a data bus (data
bus) is stacked on a corresponding entry of the before image buffer 13.

"Read-Line-with-In"
response to the "validate" transaction:
“Read-Line-with-Invalidat
If the modified response signal is asserted following the issuance of the e "transaction, it indicates that the asserted cache already holds the updated data, and the processor executes write access after the latest checkpoint. You can see that
At that point, the previous data is stored in the before image buffer 1
3, so that it is not necessary to store the data at this address in the before image buffer again. Therefore, the state saving control unit 112 does nothing.

On the other hand, “Read-Line-with-
If the modified response signal is not asserted following the issue of the “Invalidate” transaction, the buffer access control unit 214 is activated, and the cache line data output from the main memory 12 to the read bus 16 by the memory control unit 20 is transferred to the bus interface control unit. The data is transferred from the unit 211 to the buffer access control unit 214 and written into the before image buffer 13 together with the address value.

In this case, "Read-Line-non"
It is not necessary to issue a “Snoop” transaction.Response to a “Write-Line” transaction: do nothing. (5) Checkpoint Next, checkpoint processing in a multiprocessor system that operates as described above will be described. .

The checkpoint processing is a system recovery method in which information necessary for recovery from a failure is periodically collected for each checkpoint, and when a failure occurs, the processing is restarted by rolling back to the checkpoint immediately before the failure. .

At the time of a checkpoint, the processor 14
Write the internal state of ~ 15 into the main memory 12,
The data of all the cache lines in the “modified” state of each of the caches 17 to 18 is written back to the main memory 12. Actually, the writing of the internal state of the processor to the main memory 12 is also performed via the cache, so that no special consideration is required in the bus transaction. The caches 17 and 18 change the state of the cache line written back to the main memory 12 to “clean shared” or “invalid”. Since the write-back of the line data to the main memory 12 is performed using the “Write-Line” transaction, the data is not stored in the before image buffer 13 at this time.

The contents of the before image buffer 13 are cleared when the checkpoint is normally taken, and when the normal processing is restarted, the writing of the update history information to the before image buffer 13 is started. You. At the time of rollback, not only the internal state of each CPU but also the state of the main memory 12 is restored to the state at the time of the immediately preceding checkpoint. The recovery of the state of the main memory 12 is realized by sequentially reading the pre-update data stored in the before image buffer 13 and writing it back to the corresponding address of the main memory 12.

According to this method, at the time of a checkpoint, it is only necessary to write the update data held in the copy-back cache to the main memory 16, and it is not necessary to store the pre-update data in the before image buffer 13 at this point. Thus, the overhead of the checkpoint can be reduced.

As described above, in this embodiment,
A before image buffer control unit 21 is provided separately from a memory control unit 20 including a normal memory controller, and is connected to the bus 16. The before image buffer control unit 21 does not operate when a write access request to the main memory 16 is sent to the memory control unit 20, but when the CPU issues a write access request to the corresponding cache, Automatically activated in response to a transaction issued on the bus 16 from the cache,
Issue a transaction to read the pre-update data from. As described above, by providing the before image buffer control unit 21 which can operate independently of the memory controller, the existing computer system can be easily used as it is without modifying the memory controller of the existing computer system. It is possible to realize a state recovery function.

The operation of the before image buffer control unit 21 for the “Invalidate” transaction and the “Write-Line” transaction can be changed as follows.

Response to “Invalidate” transaction: When the bus interface control unit 211 snoops the “Invalidate” transaction issued to the bus 16, the state saving control unit 212
Activates the bus transaction response control unit 215. The bus transaction response control unit 215 sets “Writ” for the same address until the following processing is completed.
Assert the shared response signal for the “e-Line” transaction and continue aborting.

The state saving control unit 212 activates the bus transaction issuance control unit 215. The bus transaction issuance control unit 215 obtains “Read” for the memory location indicated by the address of the cache line to be invalidated obtained via the bus interface control unit 211 in order to obtain the cache line data before update.
Issue a "Line-non-Snoop" transaction.

Further, the state saving control unit 212 activates the buffer access control unit 214, and the cache line data read from the main memory 12 by the memory control unit 20 and output to the bus 16 is transferred to the bus interface control unit 211.
Is transferred to the buffer access control unit 214 and written into the before image buffer 13 together with the address value.

When this process is completed, the bus transaction response control unit 215 sets “Wr” for the same address.
Abort the "item-Line" transaction.

Response to “Write-Line” transaction: As described above, “Invalidat”
During the process of reading the pre-update cache line data for the e "transaction, the bus interface control unit 2
11 is a “Write-Line” issued to the bus 16
When the transaction is snooped, if it is for the same address, the bus transaction response control unit 215 asserts the shared response signal and the modified response signal and aborts.

Nothing is performed except during this processing, and even when the processing is being executed, for a different address. In the above-described embodiment, the before image buffer is configured by an independent memory, and is connected to the before image buffer control unit 21. However, the embodiment can be implemented by using a part of the main memory 12.

FIG. 5 shows this implementation example. In the system configuration of FIG. 5, the before image buffer 13 is realized by using a partial storage area of the main memory 12.
The buffer access control unit 214 is also connected to the bus transaction issuance control unit 215, and has a function of issuing a transaction to the bus 16 for accessing the before image buffer 13.

When the pre-update data and the address are transferred, the buffer access control unit 214 activates the bus transaction issuance control unit 215 to store them in the before image buffer 13 in the main memory 12. The transaction issuance control unit 215 transmits the two “Write-
Issue a "Line" transaction.

One is for storing data before update, and the other is for storing the address. Thus, there is no need to provide an independent memory, and the configuration can be made at low cost.

In the above description, a copy-back type cache has been described. However, data before updating can be stored in a write-through cache as follows.

Here, a case where the caches 17 and 18 in FIG. 1 have a function of operating in the write-through mode will be described as an example. However, a cache dedicated to write-through can be similarly realized.

In the case of a write-through cache, there are two types of cache states: invalid, valid.

In the following, for the sake of simplicity, the state management table of FIG. 3 is used, and management is performed in two states: invalid, clean shared.

The following types of transactions are issued from the caches 17 to 18 to the bus 16. "Read-Line" transaction: reading of cache line data. This is the same as in the above-described embodiment, and is issued when a valid cache line data does not exist in the cache and a cache miss occurs in response to a read access from the CPU to a cache line at a certain address.

"Write-Word" transaction: data write. It is issued regardless of the presence or absence of the data in the cache in response to a write access from the CPU.

The bus 16 has the same configuration as the above embodiment. However, in this example, the shared response signal line 161 and the modified response signal line 162 only use the function of aborting the transaction when asserted at the same time. (1) Master Processor First, the operation of the master processor that issues a transaction to start access and the state transition of the cache corresponding to the issued transaction will be described.
The master processor is the CPU 14 (cache 1
7).

Read access (cache hit):
If a cache hit occurs in the cache 17 as a result of the read access request from the CPU 14, the cache 1
7, the corresponding data is read. The CPU 14 (cache 17) does not issue a transaction to the bus 16. At this time, the state of the cache line does not change.

Read access (cache miss): C
As a result of the PU 14 requesting a read access, the cache 1
7, when a cache miss occurs, the CPU 14 (cache 17) sends the “Read-Line”
Issue a transaction.

The cache 17 sets the state of the cache line to “clean shared”, and takes in the data read from the main memory 12 and stores it in the data memory.

The cache 17 returns necessary data to the CPU 14 from the cache line data fetched from the bus 16. Write (cache hit): When a cache hit occurs in the cache 17 as a result of the CPU 14 requesting a write access, the corresponding cache line data is written and “Write-Wor” is written to the bus 16.
A d ″ transaction is issued to rewrite the data in the main memory 12. At this time, the state of the cache line does not change.

Write (cache miss): CPU 14
Makes a cache miss in the cache 17 as a result of the write access request, the “Write-
A "word" transaction is issued to rewrite the data in the main memory 12. At this time, the state of the cache line does not change. (2) Slave processor The other processor and the corresponding cache for the transaction issued by the next processor / cache The operation and state transition of the (slave processor) will be described.
(Cache 17), the slave processor is the CPU 15
(Cache 18).

Response to “Read-Line” transaction: Do nothing. Response to “Write-Word” transaction: If the cache 18 holds the cache line data targeted by the transaction in a “clean shared” state, the cache 18 sets the state of the corresponding cache line to “invalid”. (3) Memory control unit The memory control unit 20 responds to each bus transaction by
The operation is as follows.

Response to “Read-Line” transaction: Reads cache line data from the memory location indicated by the address of the cache line to be accessed, and outputs it to bus 16.

Response to “Write-Word” transaction: fetches data written from cache and writes it to the corresponding address in memory 12. (4) Before Image Buffer Control Unit Next, the operation of the before image buffer control unit 21 for each bus transaction will be described.

Response to “Read-Line” transaction: Nothing is done. Response to “Write-Word” transaction: When the bus interface controller 211 snoops the “Write-Word” transaction issued to the bus 16, the state storage controller 212 activates the bus transaction response controller 215. The bus transaction response control unit 215 asserts the shared response signal and the modified response signal to the shared response signal line 161 and the modified response signal line 162 via the bus interface control unit 211. As a result, the “Write-Word” transaction has been aborted. After that, the master processor reacquires the bus and then reissues the same transaction.

Bus transaction response control unit 215
Indicates that the reissued “Wri
In response to the "te-Word" transaction, the shared response signal and the modified response signal are asserted and continue to be imported.

The state saving control unit 212 activates the bus transaction issuance control unit 215. The bus transaction issuance control unit 215 obtains “Read” for the memory location indicated by the address of the cache line to be invalidated obtained via the bus interface control unit 211 in order to obtain the cache line data before update.
Issue a "Line" transaction.

Further, the state saving control unit 212 activates the buffer access control unit 214, and the cache line data read from the main memory 12 by the memory control unit 20 and output to the bus 16 is transmitted from the bus interface control unit 211 to the buffer access control unit 211. The data is transferred to the section 214 and written into the before image buffer 13 together with the address value.

When this process is completed, the bus transaction response control unit 215 sends the re-issued “Write-
The abort for the “Word” transaction is stopped.The state storage control unit 212 stores the address of the cache block on which the above processing has been performed, and thereafter, when the “Write-Word” transaction for the same address is issued again. Ignores.

In this example, “Write-Wor
Although the data before update is stored in units of lines for the d ″ transaction, the data before update may be stored in units of words if reading of word data is supported. (5) Checkpoint check Point processing is realized by writing the internal state of the processor to the main memory, and there is no need to write the contents of the cache because it is a write-through cache.

Although the write-through cache has been described here, the memory state recovery function is realized by the same control in a computer system having no cache or a computer system having a non-cache access operation mode. can do.

In the above embodiment, the multiprocessor system having a plurality of processors 14 to 15 has been described. However, if the cache has a similar function,
The present invention can be applied to a computer system including a single processor. Further, the present invention can be similarly applied to a case where the cache is not a single cache but has a hierarchical structure. That is, the present invention can be applied to any system having a CPU and a cache compatible with a multiprocessor.

In this way, the before image buffer control unit 21 converts the cache line data including the pre-update data held in the main memory 12 into the before image according to the transaction issued from the certain cache or CPU to the bus 16. The data is stored in the buffer 13.

That is, the memory state recovery function is realized by adding the before image buffer control unit 21 to the bus without changing the bus, the processor, the cache, and the memory control unit of the existing computer system. Becomes possible.

The operation of the before image buffer control section 21 described above is performed by a computer-readable CD-ROM.
The present invention can be realized by a computer program provided by being stored in a recording medium such as a ROM. in this case,
The computer program becomes a target of the write access request by using the memory control unit 20 in response to a transaction issued from the cache to the bus when the CPU issues a write access request to the corresponding cache. A procedure for reading data from the main memory 12 and a method for storing the data read from the main memory 12 onto the bus via the memory control unit 20 and an address corresponding to the data in the before image buffer 13. May be included. These procedures are the same as the above-described hardware operation procedures. In addition, for the snoop of the transaction from the cache to the bus, for example, a status register in which the status of the transaction on the bus is set by hardware is prepared,
This can be realized by reading the status register or the like.

The before image buffer control unit 2
1, a microcomputer can be provided, and the operation procedure of the before image buffer control unit 21 can be controlled by an operation control program such as firmware stored in a ROM of the microcomputer. Further, the present invention is not limited to the above embodiment,
Various modifications can be made within the scope of the present invention.

[0119]

As described above, according to the present invention, a memory state recovery function can be realized only by additional hardware without modifying a memory control unit of an existing computer system. Can be used as it is. In addition, since data before updating is collected not when writing data to the main memory but when writing data to the cache, if the method is applied to a system using a system recovery method by checkpoint rollback, the checkpoint Sometimes
It is only necessary to write the update data held in the cache to the main memory. At this point, it is not necessary to save the pre-update data in the buffer, so that the overhead of the checkpoint processing can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor system using a memory update history storage device according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing a configuration example of a tag memory of a cache provided in the system according to the embodiment;

FIG. 3 is an exemplary view showing a state of cache line data held in a cache provided in the system according to the embodiment;

FIG. 4 is a timing chart showing an operation of collecting memory update history information in the system according to the embodiment.

FIG. 5 is an exemplary block diagram showing another configuration example of the system according to the embodiment;

FIG. 6 is a block diagram showing a configuration of a conventional multiprocessor system required to realize a memory recovery function.

[Explanation of symbols]

12: Main memory, 13: Before image buffer, 1
4 to 15 CPU, 16 bus, 17 to 18 cache, 20 memory control unit, 21 before image buffer control unit, 211 bus interface control unit, 2
12 state storage control unit, 213 bus transaction response control unit, 214 buffer access control unit, 215
... Bus transaction issuing control unit.

Continuation of the front page (56) References JP-A-5-128071 (JP, A) JP-A-3-68034 (JP, A) U.S. Pat. No. 5,418,916 (US, A) 1 NO. 2 1990 p231-240 Kun-Lung Wu, W.C. Kent Fuchs & Janak H. Patel, "Error Recovery in Shared Memory Multiprocessors Utilizing Private Certificates, 1990, 1990, International R & D Co., Ltd. Frazier & Peter N. Marinos, "Cache-Aided Rollback Error Recovery (CA LER)" Algorithms for Shared-Memory Multiprocessor System Systems, IEEE TRANSLATION SPACE DEVELOP SERIES CONNECTION SERVICE 5 NO. 10 1994 pp. 1033-1043 Bob Janssens & W. Kent Fuchs, "The Performance of Cache-Based Error Recovery in Multiprocessors, 1987 FAULT-TOG BUTTER GROUP. Hunt & Peter N. Marinos, "A General Purpose Cache-Aided Rollbach Error Recovery (CA RR) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 15/177 678 INSSPEC (DIALOG) JICSG file (JOISW) (JOISW)

Claims (11)

(57) [Claims] At least one CPU having a built-in or connected cache, a main memory, a memory controller connected to the main memory for read / write control, and a bus connected to the cache or CPU and the memory controller. A memory update history storage device for storing update history information necessary for restoring the storage contents of the main memory when a failure occurs in the computer system, comprising: A buffer for storing the update history information having a set of contents and its storage address; and a CPU connected to the buffer and the bus for monitoring a transaction output to the bus, and the CPU performs a write access to the cache. The cache or CP when requesting Before writing to a corresponding address in the main memory in response to a write transaction output from the memory to the bus, a read transaction for reading the storage content from the storage address is performed via the bus. A memory update history storage device, comprising: buffer access control means for outputting to a controller. 2. In response to the read transaction, the memory controller reads the stored contents from the corresponding storage address of the main memory and outputs the read contents as the update history information to the buffer access control means via the bus. 2. The memory update history storage device according to claim 1, wherein said buffer access control means writes said update history information into said buffer. 3. The memory controller writes the same content as the write information to the cache at the corresponding storage address of the main memory in response to a write transaction issued again from the cache or CPU. The memory update history storage device according to claim 2. 4. The cache according to claim 1, wherein said cache is a write-through cache.
2. The memory update according to claim 1, wherein
New history storage device. 5. At least a built-in or connected cache
Also one CPU, main memory and reading of this main memory
A memory controller for performing write control, and the key
Cache or CPU and memory controller are connected
A computer system comprising:
If a failure occurs in the computer system, the main
Update history information necessary to restore memory contents
In the memory update history storing method for storing, a storage content of the main memory and a storage address thereof are paired.
A buffer for storing the update history information, and a buffer connected to the buffer and the bus,
Buffer access control means for performing write control of
And the buffer access control means is provided with a buffer which is output from the cache or CPU to the bus.
Monitoring the transaction; and the monitoring step allows the CPU to execute the cache.
Cache in response to a write access request to the cache.
Or a write transaction output from the CPU
Is detected, the corresponding address in the main memory is
Before writing is performed
Read transaction to read stored contents from storage address
Output to the memory controller via the bus
A step of reading from the main memory by the memory controller
The updated storage contents and the storage addresses
Writing the history information to the buffer as a history information . 6. The buffer access control means further comprises:
Aborting the write transaction.
6. The memory update program according to claim 5, wherein the memory update program is provided.
History saving method. 7. A copy-back type cache for each.
A plurality of CPUs that incorporate or connect
Connected to this main memory to perform read / write control
A memory controller and the plurality of caches or CPs;
U and a bus connected to the memory controller
A computer system, wherein the computer system
In the event of a system failure, the contents of the main memory are
Memory update to save update history information necessary for restoration
In the new history storage device, the storage content of the main memory and its storage address are paired.
A buffer for storing the update history information, and a buffer connected to the buffer and the bus,
Buffer access control means for performing write control of
Comprising, the buffer access control means is outputted from said plurality of cache or CPU on the bus
Means for monitoring the transaction to be executed, and the monitoring means
In response to a write access request to the cache.
Cache or other cache via the bus from the CPU.
Of the corresponding cache line output to the
If an invalidation transaction indicating invalidation is detected
Read the stored contents from the corresponding address in the main memory.
Read access to the memory controller
Means for outputting a read request from the main memory by the memory controller.
The updated storage contents and the storage addresses
Writing means for writing to the buffer as history information, a memory update history storage device. 8. The invalidation transaction according to claim 1 , wherein:
Corresponding cacher in memory or other cache
Read data from the other cache
Invalidation to instruct the corresponding cache line to be invalidated
8. The transaction according to claim 7, wherein the transaction is a transaction.
Memory update history storage device. 9. The buffer access control means further comprises:
Means for aborting the invalidation transaction
8. The memory update history storage according to claim 7, wherein
Device. 10. A copy pack type cache for each.
Multiple CPUs with built-in or corresponding connections
Connected to this main memory to perform read / write control.
A memory controller and the plurality of caches or
It has a bus to which the CPU and the memory controller are connected.
A computer system, comprising:
In the event of a system failure, the main memory
Note that saves the update history information necessary to restore the contents
In the re-update history storing method, a storage content of the main memory and a storage address thereof are paired.
A buffer for storing the update history information, and a buffer connected to the buffer and the bus,
Buffer access control means for performing write control of
Comprising, the buffer access control means is outputted from said plurality of cache or CPU on the bus
Monitoring the transaction to be performed, and the monitoring step
In response to a write access request to the cache
From another cache or other CPU via the bus.
Cache or the corresponding cache license output to the CPU.
Detects invalidation transactions that indicate invalidation
The stored contents from the corresponding address in the main memory
To the memory controller to read
Outputting an access request, and reading from the main memory by the memory controller.
The updated storage contents and the storage addresses
Writing step of writing in the buffer as history information
And a memory update history storage method. 11. The buffer access control means according to claim 1, wherein
Aborting the invalidation transaction to
11. The memory update according to claim 10, comprising:
New history storage method.