JP3083133B2 - Packet communication network - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for packet communication. The present invention is suitable for use in ATM (Asynchronous Transfer Mode) communication. In particular, the invention relates to packet routing techniques.

[0002]

2. Description of the Related Art A conventional packet communication network and a packet switch used for packet communication will be described with reference to FIGS. FIG. 7 is a configuration diagram of a conventional packet communication network. FIG. 8 is a configuration diagram of a conventional packet switch.

In FIG. 7, reference numerals 11 and 12 denote input packet switches, reference numerals 21 to 24 denote internal packet switches, reference numerals 31 and 32 denote output packet switches, and reference numerals 11-1 to 11-4 denote input packet switches 11 to internal packet switches. Output path to switches 21 to 24, reference numeral 12
-1 to 12-4 are output paths from the input packet switch 12 to the internal packet switches 21 to 24, and reference numeral 21-1.
And 21-2, an output path from the internal packet switch 21 to the output packet switches 31 and 32;
-1 and 22-2 are output paths from the internal packet switch 22 to the output packet switches 31 and 32, reference numerals 23-1 and 23-2 are output paths from the internal packet switch 23 to the output packet switches 31 and 32,
Reference numerals 24-1 and 24-2 denote internal packet switches 2.
4 to output packet switches 31 and 32, reference numerals 61-1 to 62-4 denote input lines, and reference numeral 71-1.
Reference numeral 72-4 denotes an output line, and reference numeral RT denotes a routing tag field. Reference numerals 62-1 to 62-4 shown in FIG. 8 denote input lines, reference numerals 80-1 to 80-4 denote bus multiplexing circuits, reference numerals 81-1 to 81-4 denote output route determination circuits, and a reference numeral 82-.
1 to 82-4 are output buffers, and reference numerals 83-1 to 83-4.
Is a packet synchronization circuit, 84 is a common bus, and 12-
Reference numerals 1 to 12-4 denote output paths.

With reference to FIG. 7, a method of transmitting a packet input to a conventional packet communication network will be described. The packet input to the packet communication network is first input to the input packet switch 11 or 12. The input packet switches 11 and 12 refer to the value of the rightmost field of the routing tag included in the header information of the input packet.
In this information field, the input packet switch 11,
Twelve output ports are assigned values corresponding to one-to-one, and the corresponding input packet switch 11 or 12
The packet is switched to the corresponding output port.

Similarly, the internal packet switches 21 to 24
Performs switching with reference to the central information field of the routing tag of the input packet. The output packet switches 31 and 32 perform switching with reference to the leftmost information field of the routing tag of the input packet.

In FIG. 7, a packet β (routing tag information is 1-1-3) input from the input line 62-4 to the input packet switch 12 is based on the rightmost value “3” of the routing tag. , To the output port connected to the output path 12-3. At this time, the output paths 11-1 to 11- of the input packet switches 11 and 12 correspond to the rightmost field values "1" to "4" of the routing tag.
4, and output ports connected to 12-1 to 12-4.

The packet β transferred to the output port is input to the internal packet switch 23 via the output path 12-3. In the internal packet switch 23, the packet β
The value of the central field of the routing tag is referred to as “1”, and the packet β is transferred to the corresponding output port connected to the output path 23-1. Transferred packet β
Is the output packet switch 3 via the output path 23-1.
1 is input.

The output packet switch 31 refers to the value “1” in the leftmost field of the routing tag of the packet β, and transfers the packet β to the output port connected to the corresponding output line 71-1. The transferred packet β is output via the output line 71-1.

The packet switch 12 will be described with reference to FIG. The packet switch 12 controls the input lines 61-1 to 62-4 and the output line 71-1 of the packet communication network based on the routing tag information at the fixed position of the packet.
, And cell transmission with any of the output lines 71-1 to 72-4. The packet switch configuration is specifically realized as follows.

The packet β input to the packet switch 12 via the input line 62-4 is transmitted to the bus multiplexing circuit 80.
-4, and transmitted to the common bus 84. The packet β is output via the common bus 84 to the output route determination circuit 81-
1 to 81-4. Output route determination circuit 81-1
Each of the address filters included in the output filters 82 to 81-4 determines whether to pass or discard the transmitted packet according to the specific field information in the routing tag in the packet, and only when the packet passes the output buffer 82-i (i = 1 to 4). ).

The output route determination circuit 81-3 transfers the packet to the output buffer 82-3 at the subsequent stage if the value of the specific field in the routing tag is "3", and discards the packet if it is other than "3". I do. Similarly, the other output route determination circuits 81-1 to 81-4 determine passing or discarding by referring to a specific field. Output buffer 82-3
Stored in the packet synchronization circuit 83-3
From the buffer and output to the output path 12-3. Similarly, each packet switch can perform routing by presetting the position of a field of a routing tag to be referred to.

With such a configuration, in the packet communication network, a path between an arbitrary input line, an arbitrary internal line, and an arbitrary output line is uniquely determined, and packet transmission in the packet communication network is realized. I do.

Here, the example of the three-stage configuration of the input packet switch, the internal packet switch, and the output packet switch has been described. However, by increasing the information field of the routing tag, the number of internal packet switches to be passed is increased.
Input packet switch, internal packet switch (1),
It is also possible to construct a multi-stage packet communication network via a plurality of internal packet switches, such as internal packet switches (2),..., Output packet switches.

[0014]

In such a conventional packet communication network, before a packet is input to the packet communication network, a unique routing path is determined in advance for each packet, and information on the routing path is indicated. It is necessary to add a routing tag to each packet.

[0015] Therefore, even if the traffic is biased to a specific route in the packet communication network, it is impossible to change the predetermined routing route of the packet, and the packet is routed along the route with the biased traffic. For a packet that has been determined in advance, there is no way to avoid a route in which the traffic is biased, resulting in a situation such as packet delay or loss.

In a multi-stage packet communication network, the amount of information of the routing tag increases in proportion to the number of stages, and the packet length increases. The increase in the packet length not only increases the processing time when assembling or disassembling the packet, but also increases the possibility that an error occurs in a part of the routing tag during the routing or other processes. Therefore, it is desirable that the length of the routing tag be as short as possible.

The present invention has been made in view of such a background, and an object of the present invention is to provide a packet switch and a packet communication network capable of flexibly selecting a route. SUMMARY OF THE INVENTION An object of the present invention is to provide a packet switch and a packet communication network capable of setting a short routing tag even when the number of internal packet switch stages to be passed is large. SUMMARY OF THE INVENTION It is an object of the present invention to provide a packet switch and a packet communication network that can reduce a packet delay and a loss rate.

[0018]

SUMMARY OF THE INVENTION A first aspect of the present invention is an input packet switch, which is characterized by determining a destination (either a final destination or an intermediate destination) from header information of one incoming packet. Good)
Means are provided for creating a copy packet of at least the information portion of the packet, and for sending the copy packet (which may include the original) to a plurality of output paths that can reach the destination.

Thus, a plurality of routes from the input line to the output line can be selected, and the packet can be transferred using the plurality of routes. Therefore, when congestion occurs in a specific path, a copy packet that passes through another path in which congestion does not occur reaches the output line first, and it is possible to avoid packet delay or loss.

At this time, it is desirable that a table for associating the destination identified by the identifying means with a plurality of output routes that can reach the destination be provided, and a means for setting the output route with reference to the table. .

[0021] The information processing apparatus may include means for rewriting the header information of the copy packet according to the output path.
That is, in the present invention, a short routing tag that specifies a destination is used instead of uniquely determined routing path information, but a long routing path in which a conventionally used uniquely determined routing path is used from a transmission terminal used by a user or the like. A packet to which a routing tag is added may arrive. In such a case, the routing can be performed after the input packet switch rewrites the routing tag with the short destination designation used in the present invention.

A second aspect of the present invention is an output packet switch, preferably comprising means for selecting one of a plurality of copy packets when a plurality of copy packets arrive from a plurality of paths. That is, a plurality of identical copy packets reach the same output line by transmitting the copy packets to a plurality of paths toward the same output line by the input packet switch. The output packet switch outputs one of the same copy packets to the output line and discards the other. For example, the packet that arrives at the output packet switch earliest is output and the others are discarded.

Preferably, the plurality is "2".
That is, assuming that the packet loss rate when a packet is transferred to a uniquely determined routing path as in the related art is, for example, 1/10, the same copy cell is transferred to each of two paths, and the The loss rate is 1 /
It can be 100. This improvement rate can be regarded as a practically sufficient value. If practically sufficient, it is unnecessary to use a larger number of copy cells from the viewpoint of effective use of the line.

A third aspect of the present invention is a packet communication network including the input packet switch and the output packet switch.

The input packet switch has means for giving priority information to a plurality of copy packets.
The output packet switch may be provided with means for selecting a plurality of incoming copy packets according to their priority information. That is, when a plurality of copy packets copied from different original packets arrive at one output line at the same time, by selecting the packets in accordance with the priority given to the packets, the copy packets copied from the different original packets can be mutually exchanged. Contention control between them is performed in an optimal state, and packet loss can be avoided.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION

[0027]

【Example】

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a packet communication network according to a first embodiment of the present invention. FIG. 2 is a diagram showing the configuration of the packet switch according to the first embodiment of the present invention.

Reference numerals 110 and 120 shown in FIG. 1 are input packet switches, reference numerals 210 to 240 are internal packet switches, reference numerals 310 and 320 are output packet switches, and reference numerals 110-1 to 110-4 are input packet switches 110 to internal packet switches. Output paths to the switches 210 to 240, and reference numerals 120-1 to 120-4, are from the input packet switch 120 to the internal packet switches 210 to 2.
The output path to 40, reference numerals 210-1 and 210-2 are output paths from the internal packet switch 210 to the output packet switches 310 and 320, and the reference numerals 220-1 and 220-2 are the output packet switches 310 and The output path to 320, reference numerals 230-1 and 230-2 are internal packet switches 2
30, output paths from the internal packet switch 240 to the output packet switches 310 and 320, reference numerals 61-1 to 62-4 indicate input lines, Reference numerals 71-1 to 72-4 indicate output lines, and reference numeral 15
0, 250, 350, and 351 indicate destination address tables, respectively, and RT indicates a routing tag field.

Reference numerals 62-1 to 62-4 shown in FIG. 2 denote input lines, reference numerals 80-1 to 80-4 denote bus multiplexing circuits, and a reference numeral 9
1-1 to 91-4 are output route judgment circuits, and reference numeral 82-1
82-4 are output buffers, 83-1 to 83-4 are packet synchronization circuits, 84 is a common bus, and 120-
1 to 120-4 indicate output paths.

The present invention provides input packet switches 110 and 120, which are characterized by an output route determination circuit 91- as means for identifying a destination output line from header information of one incoming packet. 1-91
-4, a common bus 84 as a means for creating a copy packet of the packet, and output buffers 82-1 to 8-4 as means for sending the copy packet to output paths 120-1 to 120-4 which can reach this destination. 82-4 and the packet synchronization circuits 83-1 to 83-4.

The output route judging circuits 91-1 to 91-
Table 150 for associating the destination identified by No. 4 with output routes 120-1 to 120-4 that can reach the destination
And the output path 120 is referred to by referring to the table 150.
-1 to 120-4 are set. In the example of FIG. 2, the packet β is transferred to the output routes 120-1 and 120-2 since the output line a is the destination.

Output packet switches 310 and 320
Has a packet selection circuit 20 as means for selecting one of the plurality of copy packets when the plurality of copy packets arrive from a plurality of paths.

In the first embodiment of the present invention, the same output line 7 is used.
When there are two or more routes toward 1-i and 72-i (i = 1 to 4), the copy packet is transmitted to the two routes.

Next, the operation of the first embodiment of the present invention will be described. As shown in FIG. 2, the packet β input from the input line 62-4 is converted by the input packet switch 120 into the destination address table 1 based on the routing tag information.
After the output port capable of forwarding is determined from 50, it is output to the internal packet switches 210 to 240 via the output paths 120-1 to 120-4.

In FIG. 2, the packet β (routing tag “a”) corresponds to the routing tag “a” of this packet.
From the destination address table 150, it is determined that the data can be transferred to the output ports “1” and “2”. In the destination address table 150, a mark “○” can be transferred,
An “x” mark indicates that transfer is impossible, and whether transfer is possible is uniquely determined by a combination of a routing tag and an output port. When it is determined that transfer is possible, packet β is output from output ports “1” and “2” to output paths 120-1 and 120-1.
Output via 20-2.

Similarly, the internal packet switches 210-2
40, the packets input to the output packet switches 310 and 320 are transferred according to the information of the routing tag. 2 is input to the internal packet switch 210 via the output path 120-1 and then,
After it is determined from the destination address table 250 that the output port is “1”, it is input to the output packet switch 310 via the output path 210-1. Further, the output packet switch 310 determines that the output port is “1” from the destination address table 350 and forwards the packet. Similarly, the output path 120-
2, the packet β input to the internal packet switch 220 is output from the output line 71-1 via the output path 220-1 and the output packet switch 310.
At this time, if the copy packet that has passed through the output path 210-1 has been output from the output line 71-1 first, the copy packet that has passed through the output path 220-1 is discarded. The packet selection circuit 20 holds the information of the already output copy packet, and when a copy packet of the same content arrives, discards it.

In FIG. 2, the output route judgment circuits 91-1 to 9-1
1-4 are routing tags and destination address table 1
The transferable port is determined by retrieving 50 pieces of information. The output route determination circuit 91-1 searches the destination address table 150 for a combination of the routing tag “a” of the packet β and the same output port “1”. If the result is ““ ”, it is determined that transfer is possible. By performing similar processing in the output route determination circuits 91-2 to 92-4, the output route determination circuits 91-1 and 91-2 determine that this packet can be transferred, and the output buffer 82 -1 and 82-2. The packets once stored in the output buffers 82-1 and 82-2 are
The packets are synchronized by the packet synchronization circuits 83-1 and 83-2 and are sequentially transferred to the output paths 120-1 and 120-2.

According to the first embodiment of the present invention, a packet in which the information of the output lines 71-1 to 72-4 is added to the routing tag from the input lines 61-1 to 62-4 of the packet communication network is input. By transferring a plurality of copy packets to an output port capable of outputting at each packet switch (input, internal, output) in the packet communication network, packet transfer using a plurality of paths becomes possible.

In the first embodiment of the present invention, a 4 × 4 packet switch (input, internal, output) is used.
The same can be realized regardless of the number of lines of the basic switch. Further, the three-stage configuration including the input packet switches 110 and 120, the internal packet switches 210 to 240, and the output packet switches 310 and 320 has been described. However, the present invention does not require the input packet switches and the internal packet switches without increasing the information field of the routing tag. The number of stages of the internal packet switches passing through the switches (1), the internal packet switches (2),..., And the output packet switches can be increased to provide a multistage configuration exceeding three stages.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a diagram showing the concept of the packet communication network according to the second embodiment of the present invention. FIG. 4 is a diagram showing the configuration of the output packet switch according to the second embodiment of the present invention. In FIG. 3, reference numeral IN denotes an input line, reference numeral 500 denotes an input packet switch, reference numerals 510, 520, 530,
540, 550, 560, 570 are internal packet switches, 580 is an output packet switch, 501 is
511 and 521 are priority order addition constant holding circuits;
UT indicates an output line, and P indicates a copy priority information field. In FIG. 4, reference numeral 600 denotes a contention control circuit.

The second embodiment of the present invention is an embodiment for easily realizing control in the output packet switch in the case where copy packets having different original packets compete with each other. Selection and discard of a copy packet having the same original packet are processed in the same manner as in the first embodiment of the present invention.

In the second embodiment of the present invention, an input packet is provided with a routing tag field RT and a copy priority information field P. In FIG. 3, the packet β to which the copy priority “1” is assigned is input packet IN
Is input to the input packet switch 500. Here, a case where the input packet switch 500 branches to two routes is shown. At this time, the input packet switch 500 randomly selects any one of the branched routes, sets the priority of the packet transmitted to this route to “1”, and sets the other packet to hold the addition constant of the switch. A value obtained by adding a priority addition constant preset in the circuit 501 to the priority of the input packet is given. Here, a value obtained by adding “+10” to “1”, that is, “11” is assigned as a priority.

Similarly, the internal packet switch 510 branches to three routes, generates packets having priorities “1”, “3”, and “5” using the addition constant “+2”. 530, 540, and 550. In the internal packet switch 520, the priority “1”
Packets of "1" and "13" are generated and transferred to the internal packet switches 560 and 570. At this time, the number of copy priorities is regarded as the priority,
A priority can be given to the branch packet.

On the other hand, as shown in FIG. 4, two or more packets (here, packets β and packets δ: these packets have different original packets) are input to the output packet switch 580 at the same time, and Contention occurs when only one of the packets can be output to the path. In such a case, the contention control circuit 600 takes the copy priority into consideration by referring to the copy priority number given to the packet and outputting the packet with the smaller copy priority number preferentially. Contention control can be performed. In this way, by giving the copy priority and performing contention control in consideration of the copy priority, it becomes possible to discard the surplus copy when the internal load increases due to the copy in the packet communication network.

Third Embodiment A third embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a configuration diagram of a header conversion circuit according to the third embodiment of the present invention. FIG. 6 is a diagram showing a header conversion table according to the third embodiment of the present invention.

In the first and second embodiments of the present invention, the packet to which the routing tag used in the present invention is added is input to the input packet switch. However, the packet to which the routing tag described in the conventional example is added is input. And input packet switches 110 and 120
Within, the routing tag used in the present invention can be rewritten. This can be realized by providing the header conversion table 40 capable of specifying the output line by the routing tag described in the conventional example. Thus, for example, even when a user who uses the packet communication network of the present invention has a transmission terminal of the method of adding a routing tag described in the conventional example, the packet communication network of the present invention can be used.

As shown in FIG. 5, a header conversion circuit 30 is provided in the input packet switches 110 and 120. The header conversion circuit 30 is provided with a header conversion table 40. As shown in FIG. 6, the header conversion table 40 is a table in which information for converting the routing tag described in the conventional example to the routing tag of the present invention is recorded.

[0048]

As described above, according to the present invention,
The route selection can be performed flexibly, and the routing tag can be set short even when the number of internal packet switch stages to be passed is large. This allows
Packet delay and loss rate can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a packet communication network according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a packet switch according to the first embodiment of the present invention.

FIG. 3 is a diagram showing the concept of a packet communication network according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an output packet switch according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a header conversion circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a header conversion table.

FIG. 7 is a configuration diagram of a conventional packet communication network.

FIG. 8 is a configuration diagram of a conventional packet switch.

[Explanation of symbols]

11, 12, 110, 120, 500 input packet switches 21 to 24, 210 to 240, 510, 520, 530
570 Internal packet switch 30 Header conversion circuit 31, 32, 310, 320, 580 Output packet switch 40 Header conversion table 61-1 to 62-4, IN input line 71-1 to 72-4, OUT output line 11-1 ~ 12-4, 21-1 ~ 24-2, 110-1
To 120-4, 210-1 to 240-2 Output path 80-1 to 80-4 Bus multiplexing circuit 81-1 to 81-4, 91-1 to 91-4 Output route determination circuit 82-1 to 82- 4 Output Buffer 83-1 to 83-4 Packet Synchronization Circuit 84 Common Bus 150, 250, 350, 351 Destination Address Table 501, 511, 521 Addition Constant Holding Circuit 600 Competition Control Circuit P Copy Priority Information Field RT Routing Tag Field

Continuation of front page (56) References JP-A-6-14056 (JP, A) JP-A-7-95203 (JP, A) JP-A-8-251235 (JP, A) JP-A-8-256158 (JP, A) JP-A-7-193615 (JP, A) JP-A-7-46250 (JP, A) JP-A-6-343081 (JP, A) JP-A-6-303257 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (4)

(57) [Claims] (1)Input packet switch and output packet
A packet communication network including a switch and The input packet switch, One incoming packet
From the header information of the destination (whether final destination or intermediate destination)
Good) and at least that packet.
Means for creating a copy packet of the information portion of
Copy packets to multiple output routes that can be reached first
(Which may include the original)
e, The output packet switch transmits a plurality of packets from a plurality of paths.
When a packet arrives, its multiple copy packets
With means to select one of the The input packet switch converts a plurality of copy packets
Means for giving priority information about The output packet switch has a different copy source.
Priority information when multiple copy packets conflict
Equipped with means for selecting according to Characterized in that
KetCommunication network. 2. The input packet switch according to claim 1 , further comprising: a table for associating the destination identified by said identifying means with a plurality of output paths that can reach said destination; and means for setting said output path with reference to said table. The packet communication network according to claim 1, comprising: 3. The packet communication network according to claim 2 , wherein said input packet switch includes means for rewriting a header of a packet arriving according to said output path. 4. The packet communication network according to claim 1, wherein said plurality is “2”.