JP3083031B2 - Teletext broadcasting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a teletext display.
Dot claw by color subcarrier (3.58MHz) component
Le reduction on the.

[0002]

2. Description of the Related Art A conventional teletext device receives a normal television signal from an antenna, extracts character information data from the received television signal, writes it in a memory, stores it, and synchronizes it with a horizontal and vertical synchronizing signal. Then, the character information data is read from the memory and displayed as a teletext screen. Although the horizontal and vertical synchronizing signal for reading and displaying the character information data as is possible to generate within the teletext device, receiving
Depending on the device, the configuration of the circuit element (IC etc.)
Display with 262 scanning lines per field
There is. In this case, the first field and the next field
And the phase of the color subcarrier (3.58 MHz) match
This phase matching makes dot crawls stand out on the screen.
That is, there is a problem that it is difficult to view an image .

[0003]

SUMMARY OF THE INVENTION In view of the above problems, the present invention reduces dot crawl on a display screen, and
Generates a 3.58MHz clock signal for easy viewing
An object of the present invention is to provide a teletext broadcasting device.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method for detecting a horizontal synchronizing signal and a vertical synchronizing signal.
Input to the first inverter for phase inversion
Then , the output of the first inverter is input to an integrating circuit composed of a resistor and a capacitor, and the output of the integrating circuit is output to the integrating circuit.
Input to the second inverter Yumitto circuit function, the second
The output of the inverter is input to one input terminal of the first NAND gate, the composite synchronization signal is input to the other input terminal of the first NAND gate, and the output of the first NAND gate is fed back to the input terminal of the inverted output. enter the flip <br/> clock terminal of the flop comprising, enter the positive-phase output of the flip-flop to one input terminal of the second 2NAND gate, via a third inverter for phase inversion to the other input terminal A 3.58 MHz clock signal is input, the output of the second NAND gate is input to one input terminal of the third NAND gate, the output of the fourth NAND gate is input to the other input terminal, and the output of the fourth NAND gate is input. One input terminal receives the inverted output of the flip-flop, and the other input terminal receives the 3.58 MHz clock.
And a vertical synchronizing signal from the output terminal of the third NAND gate for each horizontal synchronizing signal.
Each time, a 3.58 MHz clock signal whose phase is inverted is taken out.

[0005]

According to the structure described above, the composite synchronizing signal is
Branch input to one inverter and the first NAND gate.
Predetermined time of the composite synchronization signal whose phase has been inverted by the first inverter
Integrates with the number of integrator circuits and outputs the same integrated output to the Schmidt circuit
Input to the second inverter. The second inverter is
For input levels below a certain reference value (threshold)
High (H) for input levels that exceed the reference value
Outputs a signal set to low (L). This output and the duplicate
With respect to the synchronizing signal, the first NAND gate
NAND (negation of logical product). This first NAND gate
Input to the clock terminal of the flip-flop.
You. As a result, the non-inverting output terminal of the flip-flop and the
From the output terminal, each horizontal sync signal or vertical sync signal
A signal in which H and L are interchanged is output, and the positive-phase output is the second N
Input to the AND gate, and the inverted output is the fourth NAND gate
To enter. The third NAND gate is connected to the second NAND gate.
Input 3.58MHz clock signal whose phase is inverted by data
And 3.58M without phase inversion is applied to the fourth NAND gate.
Hz clock signal is input. A second NAND gate;
The fourth NAND gate outputs the normal phase from the flip-flop.
When one is in the signal output state, the other
The other operates so that the output is stopped, and the second NAND gate
A 3.58 MHz clock signal whose phase has been inverted
Output, no phase inversion from the fourth NAND gate
A 3.58 MHz clock signal is output. These NA
Input the output of the ND gate to the third NAND gate,
NAND. As a result, the third NAND gate
Are set for each horizontal sync signal and each vertical sync signal.
A phase inverted 3.58 MHz clock signal is output
You.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A teletext apparatus according to the present invention has an internal 3.58 MHz clock generated by a conventional teletext apparatus.
Signals are phase-cropped so that dot crawl is reduced.
The signal is converted into a signal. As a result,
The converted 3.58 MHz clock signal is transmitted to the subsequent character signal.
Character signal display by using for signal processing circuit (not shown)
It is possible to reduce dot crawl on the screen.
This conversion circuit will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an embodiment of the conversion circuit. In the figure,
1 is a composite synchronization signal generated by a conventional teletext device
S1, which is an input terminal for inputting a. This composite synchronization signal S1 is
As shown in FIG. 2, the horizontal synchronization signal Sh and the vertical synchronization signal Sv
Which is synchronized with the synchronizing signal in the teletext signal.
There is . This composite synchronization signal S1 is input to the first inverter 2.
Then, the phase is inverted. The in-phase inverted signal is connected to the resistor R
And an integrating circuit 3 having a predetermined time constant and a capacitor C.
You. The integrated signal is input to the second inverter 4. This
The second inverter 4 is an inverter having a Schmitt circuit function.
Based on a set reference value (threshold).
High for input levels below the reference value (threshold)
(H), and input level exceeding the reference value
-(L) is output. This second inverter 4
Inputting the output of the one input terminal 6 of the 1NAND gate 5. The other input terminal 7 of the first NAND gate 5
Receives a composite synchronization signal S1 from the input terminal 1.
Flip-flop the output of the first NAND gate 5
(FF) to the clock terminal (CK) , and output the output terminal 8 (positive phase output terminal) of this flip-flop to the second NAN.
The signal is input to one input terminal 10 of the D gate 9. The second
The other input terminal 11 of the NAND gate 9 has a phase inversion
Black of 3.58MHz via a third inverter 12 in use
Input signal S3. Also, the third inverter 12
Is 3.58 MHz generated by a preceding circuit (not shown).
Is input via the input terminal 13.
The negation of the logical product of the output of the third inverter 12 and the output signal from the output terminal 8 of the flip-flop is the second.
Output from NAND gate 9. This output is
The signal is input to one input terminal 15 of the ND gate 14. 4th
The signal from the inverted output terminal 17 of the flip-flop is input to one input terminal of the N AND gate 18, the 3.58 MHz clock signal S2 is input to the other input terminal, and the output of the fourth NAND gate 18 is output. The third NA
Input to the input terminal 16 of the ND gate 14 . This 3N
3.58 MH which is the object of the present invention from the AND gate 14
The clock signal S4 of z is obtained.

Next, the operation of the circuit having the above configuration will be described with reference to FIG.
This will be described with reference to the waveform diagram of FIG. S1 in the figure is a composite synchronization signal
Reference numeral 21 denotes a horizontal synchronizing signal (S
h), 22 is the vertical retrace interval, and Sv is the vertical synchronization
Signal. This composite synchronizing signal S1 is converted by the first inverter 2
The phase is inverted, and the phase inversion signal Sa such as 23, 24, etc.
Get. The inversion signal Sa is integrated by the integration circuit 3. This product
As shown in the figure, the minute output Sb
Of the horizontal synchronizing signal Sh with a narrow
Etc.), and large amplitude for the wide vertical sync signal Sv
Output. The second inverter to which the integrated output Sb is input
The signal Sc shown in FIG . This second b
The inverter 4 is an inverter having a Schmitt circuit function as described above.
Data, the reference value (threshold value) Vs
High (H) is output for the following inputs (25 components).
(Reference 26), low for inputs above Vs
(L) is output (Sc). This output Sc and the composite synchronization signal S1
From the first NAND gate 5 to which a logical product is
A constant signal Sd is output. In the same signal Sd, the video period
Since Sc is H in the middle, its output depends on the presence or absence of the horizontal synchronization signal.
Changes to L (code 28) or H (code 29),
In the line period 22, since Sc is L, the polarity (L or H) of S1 is
Regardless, the output is always H. The first NAND gate
The output Sd of the gate 5 is the clock terminal of the flip-flop (FF)
(CK). This flip-flop (FF) is shown
To form an inverted output by feeding it back to the input terminal (D).
Therefore, L and H of the signal Sd input to the clock terminal (CK)
, The respective outputs of the positive phase output terminal 8 and the inverted output terminal 17
(Normal phase output / inverted output) is L / H → H / L → L / H →
H / L are alternately inverted as in H / L ...
You. Note that the flip-flop operates at the rising edge of the input signal Sd.
It is assumed that the operation is performed at a portion (arrow shown). These normal phases
The output and the inverted output are connected to the second NAND gate 9 and the fourth NAND gate 9.
Input to NAND gate 18 . In addition, these NAN
The D gates 9 and 18 are inverted in phase by the third inverter 12.
3.55 MHz clock signal S3 and phase inverted
No 3.58 MHz clock signal S2 is input as shown.
Power. Further, a second NAND gate 9 a fourth N AN
When one of the D gates 18 is in the signal output state, the other is in the signal output state.
The output is stopped, and this state is input by the input signal Sd.
Take the place. Thereby, the second NAND gate 9 and the fourth NAND gate 9
Inverted from the NAND gate 18 by L and H of Sd
Output of the inverted signal S3 and the non-inverted signal S2
Becomes This alternately output signal is the third NAND gate.
Output from the port 14 (S4 = S2 or S3). This final
Output signal S4 is output for each horizontal synchronization signal and for the vertical synchronization signal.
3.58 MHz clock signal with inverted phase for each signal
It is. This 3.58 MHz clock signal S4 is connected to a subsequent circuit.
Used for character signal processing .

[0008]

As described above, the number of scanning lines is set to one field.
In a text broadcasting device that displays characters as 262 lines per
Phase for each horizontal and vertical sync signal.
Can be obtained by inverting the 3.58 MHz clock signal.
You can do it . Conventionally, a 3.58 MHz clock signal
Phase is fixed independently of the horizontal or vertical sync signal.
It was fixed. Using this clock signal,
When the display of 262 characters has been processed,
Crawling appeared, making the image difficult to see
Uses a 3.58 MHz clock signal according to the present invention.
This reduces the dot crawl and reduces the visibility of the image.
This has the effect of being able to be improved .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a teletext device according to the present invention.

FIG. 2 is a timing waveform diagram of the teletext device according to the present invention.

[Explanation of symbols]

1 composite synchronizing signal input terminal 2 first inverter 3 integration circuit 4 second inverter 5 first NAND gate 6 input terminal 7 input terminal 8 output terminal 9 second NAND gate 10 input terminal 11 input terminal 12 third inverter 13 input terminal 14 third NAND Gate 15 Input terminal 16 Input terminal 17 Output terminal 18 Fourth NAND gate FF flip-flop

Claims (1)

(57) [Claims] 1. A system comprising a horizontal synchronizing signal and a vertical synchronizing signal.
Input to the first inverter for phase inversion
Then , the output of the first inverter is input to an integrating circuit composed of a resistor and a capacitor, and the output of the integrating circuit is output to the integrating circuit.
Input to the second inverter Yumitto circuit function, the second
The output of the inverter is input to one input terminal of the first NAND gate, the composite synchronization signal is input to the other input terminal of the first NAND gate, and the output of the first NAND gate is fed back to the input terminal of the inverted output. enter the flip <br/> clock terminal of the flop comprising, enter the positive-phase output of the flip-flop to one input terminal of the second 2NAND gate, via a third inverter for phase inversion to the other input terminal A 3.58 MHz clock signal is input, the output of the second NAND gate is input to one input terminal of the third NAND gate, the output of the fourth NAND gate is input to the other input terminal, and the output of the fourth NAND gate is input. One input terminal receives the inverted output of the flip-flop, and the other input terminal receives the 3.58 MHz clock.
And a vertical synchronizing signal from the output terminal of the third NAND gate for each horizontal synchronizing signal.
A teletext apparatus characterized in that a 3.58 MHz clock signal whose phase is inverted every time is taken out.