JP3080457B2 - Distributed address translation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In various fields such as aerodynamic simulation in aerospace technology, it is expected that the intended purpose will not be achieved in the near future unless the operation speed of a computer is increased to 100 times or more of the present speed. It is said,
There is a demand for a dramatic improvement in the calculation speed of computers.

In order to meet the above demands, a multiprocessor system in which a large number of processors are connected by a network to perform a parallel operation is indispensable, and development is proceeding.

In the above multiprocessor system, each processor is called a processor element PE. The multiprocessor system includes a shared memory type in which each PE shares a main memory and a distributed memory type in which each PE has a unique main memory (local memory).

[0004] The distributed memory type multiprocessor system has the advantages that a large number of operations can be executed in parallel, that the memory access time can be shortened, and that a high throughput can be obtained as a whole system. It is considered to be the most suitable as a calculation system for a simple simulation.

The present invention relates to an address conversion system for converting a virtual address in a system into a real address in a PE, which is necessary when one PE accesses another PE in a distributed memory type multiprocessor system.

[0006]

2. Description of the Related Art FIG. 4 shows an outline of a configuration of a distributed memory type multiprocessor system. In FIG. 4, N PEs
1-i (i = 1 to N) each have a CPU and a main memory (local memory) LM, and execute calculations independently by respective programs.

[0007] Each PE1-i is connected to the network 2 by a transmission line 5-i and a reception line 6-i.
The network 2 has a crossbar network 3 having N rows and N columns.
The crossbar network 3 includes N rows of bars, N columns of bars, and switches 4 arranged at respective intersections of the i-th row bar and the j-th column bar.
ij (shown by a circle).

Each switch 4ij is turned on / off by a control signal, and when turned on, connects the i-th row bar to the j-th column bar.
Disconnect them when off. PE1-i is in the i-th row bar
Are connected on a one-to-one basis, and the j-th column bar has P
E1-j receiving lines 6-j are connected one-to-one.

In PE1-i, PE1
When the command for accessing the main memory of -j is decoded, the network control is notified and the switch 4ij of the network 2 is turned on. as a result,
The i-th row bar and the j-th column bar are connected, so that PE1-
A packet transmission path from i to PE1-j is formed. For example, the originating switch 4 _1N is turned on PE1-
1 to a receiving PE1-N is formed.

[0010] The crossbar network 3 is composed of PE1-i to PE1
-J transmission of packets to j and PE1-k to PE1-
1 has a feature that transmission of a packet to 1 does not collide under the conditions of i ≠ k and j ≠ l.

FIG. 5 shows a format of a packet transferred through the network 2. In FIG. 5, packet 7
Consists of a packet header 7A and body data 7B.

The packet header 7A includes a packet transfer destination PE number, a body length indicating the length of body data, a transfer instruction code indicating whether data is read or written, and a transmission P
A transmission base address indicating the head address of the data storage area of E, a reception base address indicating the head address of the data storage area of the reception PE, and the like are included.

Now, in the distributed memory type multiprocessor system, the main memory is distributed to each PE as described above, and aims at realizing high throughput and shortening access time in the whole system. However, a part of the main memory distributed as described above is configured as a global memory so as to be accessible from all PEs.

That is, the global memory forms a virtual address space when viewed from a program, and all memory locations in the global memory can be specified by a virtual address in the system (referred to as a system address).

The system address included in the instruction of the program includes PE-id indicating the system number of the access destination PE (referred to as reception PE), and page number P in the reception PE.
X and the in-page byte number BX. The system address is converted to a real address for actually accessing the LM in each PE.

In a conventional system, a system address included in a program instruction is converted into a real address in a transmission PE, written in a reception base address column of the packet, and transferred to the reception PE.

[0017]

As described above, the virtual address in the PE is indicated by the page number and the byte number in the page. To convert the virtual address into the real address in the PE, it is necessary to convert the page number into the real head of the page. Address (Page
Frame Real Address: PFRA)
Is required.

In the originating PE, the virtual address in the PE is set to P
In order to convert to a real address in E, the originating PE must have a translation table (page table) for associating a page number (virtual) with PFRA for all PEs. When the system address space is further increased and address conversion is performed in two or more stages, the number of conversion tables further increases.

Therefore, P in a multiprocessor system
When the number of Es increases, the amount of hardware of the address translation table held by each PE becomes extremely large. As the amount of hardware increases, the processing time also increases, which hinders speeding up.

Further, since the contents of the address conversion table are frequently updated, the updated address conversion table must be broadcasted to all PEs each time, and the overhead for this is not negligible.

The present invention eliminates the above disadvantages of the prior art,
It is an object of the present invention to provide a distributed address conversion method capable of reducing the amount of hardware for the address conversion table, increasing the processing speed, and reducing the overhead when updating the address conversion table.

[0022]

According to the present invention, a plurality of processors each having a storage device are connected, and a logical address in the system common to the plurality of processors is assigned to a real address of each processor. A processor constituting a multiprocessor system in which the storage devices can be mutually accessed by converting the logical processor numbers into logical processor numbers. First conversion means for converting a real processor number into a real processor number, and second conversion means for converting a logical address in the processor relating only to its own processor into a real address in the processor for the logical address in the processor included in the logical address in the system. It is comprised including.

A plurality of processors, each having a storage device, are connected by a network, and a logical address in the system common to the plurality of processors is converted into a real address of each processor so that the storage devices can be mutually accessed. A processor system, wherein each of the processors is a first conversion unit that converts a logical processor number into a real processor number for all logical processor numbers for a logical processor number included in the in-system logical address; As for the logical address in the processor included in the logical address in the system, a second conversion means for converting the logical address in the processor relating only to the self processor to the real address in the processor is provided.

In a multiprocessor system in which a number of processors each having a main memory are connected by a network and mutual access between the processors is enabled, each processor stores a logical address in the system in a main memory of another processor.
Access with a dress . In this case, the logical
The address is converted into a real address in the receiving processor in two stages by both the processor on the transmitting side of the access request and the processor on the receiving side.

The intra-system logical address comprises a logical processor number and an intra-processor logical address . The logical processor number is converted to the real processor number by the first conversion means on the transmitting processor side, an access request is sent to the receiving processor of the real processor number, and at the same time , the logical
The dress is sent to the receiving processor.

The receiving processor receiving the request,
The second conversion means converts the in- processor logical address to its own in-processor real address. In this way, the logical address in the system is set to two for the transmitting side and the receiving side.
By converting to a real address in stages, each PE
There is no need to have a copy of the address translation table for E, thus reducing the amount of hardware and increasing the processing speed.

[0027]

Embodiments of the present invention will be described below. The multiprocessor system to which the present invention is applied is shown in FIG.
At the same time, a number of PEs 10-k (k = 1 to N) and each PE
And a network 20 that enables connection between the two. The network 20 has a crossbar network as shown in FIG. 4, and connects the transmitting PE 10-i and the receiving PE 10-j.

Each PE independently executes a program instruction. The instruction includes an operation code indicating the type of operation and an operand, and the operand includes an address and data. The address is described as a system address (virtual address in the system).

FIG. 1 shows an embodiment of the distributed address conversion system according to the present invention in the case where a PE 10-i accesses a PE 10-j by a system address. FIG. 1 shows only the part that operates when the PE 10-i functions as the transmitting side and the PE 10-j functions as the receiving side. However, each PE can function as the PE on any of the transmitting and receiving sides. Has become.

Each PE includes a system address register 11 for loading a system address included in a program read or write instruction, a real address register 12 for loading a real address of a self-main memory,
It has a PE conversion table 13 for converting logical PE numbers of all PEs to real PE numbers, and a page table 14 for converting page numbers of only the self-main storage into real page addresses.

[0031] The network 20 is connected from the originating PE to the real PE.
A request issuing circuit 21 for receiving a number and issuing a request signal to the PE of this number;
Register 2 for temporarily storing the address in virtual PE from E
2

The system address register 11 stores the reception P
A logical PE number PE-iD of E, a page number PX indicating the number of the page containing the memory location to be accessed, and an in-page byte number BX indicating the intra-page displacement of the memory location are stored.

PE-i of the system address register 11
D is an index input of the PE conversion table 13. The PE conversion table 13 outputs a real PE number corresponding to the PE-iD. The output of the PE conversion table 13 is
0 is supplied to the request issuing circuit 21. The request issuing circuit 21 sends a request signal indicating that there is an access request to the PE indicated by the real PE number.

The virtual addresses (PX and BX) in the PE in the system address register 11 are directly
0 is loaded into the register 22. The virtual page number PX stored in the register 22 of the network 20 serves as an index input of the page table 14. The page table 14 stores the actual head address (PFRA) of the page corresponding to PX.
Output to the PFRA section of the real address register 12 .

The in-page byte number BX stored in the register 22 is directly transferred to the BX portion of the real address register 12. The real address register 12 connects the PFRA unit and the BX unit to generate a real address of an access memory location and outputs the generated real address to the main memory LM.

The operation will be described below. PE10-
When the read or write command for PE 10-j is decoded at i, the switch 4ij of the crossbar network of the network 20 is turned on by the network control, and as a result, a packet transmission path is established between PE 10-i and PE 10-j. The system address formed and simultaneously included in the instruction is loaded into the system address register 11.

In this case, the system address PE-iD
The part is the logical number of PE10-j. The PE-iD part is supplied to the PE conversion table 13 as an index input,
The X and BX portions are transferred to the register 22 of the network 20 and are temporarily stored.

The PE conversion table 13 stores the PE-iD to P
The real PE number of E10-j is extracted and the network 20
To the request issuing circuit 21. The request issuing circuit 20 sends a request signal indicating an access request to the PE 10-j.

The PX portion of the register 22 of the network 20 is sent as an index input to the page table 14 of the PE 10-j, and the BX portion of the register 22 is sent to the lower bit position (BX portion) of the real address register 12 of the PE 10-j. And stored.

The head address PFRA of the page corresponding to the page number PX is extracted from the page table 14, and
Upper bit position (PF) of the real address register 12
RA unit) and stored.

The real address register 12 connects the page start address PFRA and the in-page byte number BX, and supplies the real address of the memory location to be accessed to the main memory LM.

In the case of writing, the body data included in the packet from the originating PE 10-i is
Is written to the memory location designated by the real address register 12 of the memory, and in the case of reading, the byte data is read out from the memory location and transmitted.
It will be sent to E10-i.

FIG. 2 is a diagram showing the details of the network 20. In FIG.
b is an address / data receiving unit, 20c is a data length recognition unit, 20d is a destination PE recognition unit, 20e is a data length control unit, 20f is a network switch connection / disconnection control unit,
20g represents a connection switch.

As shown in the figure, the signal from each transmission PE is input to the corresponding network. In the network, a request from a calling PE is received by a request receiving unit 20a, and its data length is recognized by a data length recognizing unit 20a.
c, and controls the data length of the data received by the address / data receiving unit 20b.

On the other hand, information on the destination PE is the destination P
The data is input to the E recognition unit, and the destination (receiving PE) is recognized. The information on the receiving PE recognized by the destination PE recognition unit 20d and the information from the data length control unit 20e are input to the network switch connection / disconnection control unit 20f, and based on the information, the network switch connection / disconnection control is performed. The unit 20f controls the connection switch 20g to transmit the P
Connect E to the receiving PE.

FIG. 3 is a diagram showing another embodiment of the present invention. The present embodiment is applied when the system address is configured by a two-stage access method. In the two-stage access method, the virtual address space is divided by a minimum unit page, and a larger unit segment is formed by a plurality of pages. Therefore, the virtual address is the PE number PE-iD, P
It is represented by the segment number SX in E, the page number PX in the segment, and the byte number BX in the page.

Each PE 30k (k = 1 to N) is a PE-i
A system address register 31 for loading a system address including D, SX, PX, and BX; a real address register 32 for generating a real address for accessing main storage;
It has a PE conversion table 33, a segment table 34, a page table 35, and addition circuits 36 and 37.

The PE conversion table 33 has a logical PE-iD
And outputs the corresponding real PE number and the start address (STO) of the segment table. The segment table 34 is provided corresponding to each PE, and stores the start address PTO of each page table 35.

The page table 35 stores the head address PFRA of each page. The network 40 stores a request issuing circuit 41 that issues a request signal to the PE having this number, a PTO register 42 that stores the PTO output from the segment table 34, and a PX according to the real PE number from the PE conversion table 33. It has a PX register 43 for storing and a BX register 44 for storing BX.

The operation will be described below. PE30-
i, when the access command to the PE 30-j is decrypted, the network
E30-j is connected, and at the same time, the system address is loaded into the system address register 31.

The conversion table 33 is indexed by the PE-iD of the system address register 31 and is stored in the PE 30-j.
Is output to the network 40 and the head address STO of the segment table 34 is output. The request issuing circuit of the network 40 issues a request signal to the PE 30-j having the received real PE number.

The STO from the segment table 34 and the SX of the system address register are added by the adding circuit 36, the segment table 34 is indexed by the addition result, and as a result, the corresponding start address PTO of the page table 35 is extracted, and 40 P
It is sent to the TO register 42.

The contents of the PX section and the BX section of the system address register 31 are sent to the PX register 43 and the BX register 44 of the network 40, respectively, and are temporarily stored therein.

Request issuing circuit 4 of network 40
Receiving the signal indicating the access request from No. 1, the receiving PE 30-j adds the output PTO of the PTO register 42 of the network 40 and the content PX of the PX register 43 by the adding circuit 37, and stores the page table 35 according to the result. Index.

The PFRA corresponding to the index input is output from the page table 35, and the PFRA of the real address register 32 is output.
It is stored in the RA unit. The content of the BX register 44 of the network 40 is the real address register 32 of the receiving PE.
Of the BX unit. The real address register 32 of the receiving PE 30-j obtains the real address of the target memory location by linking PFRA and BX, and stores it in the main memory LM.
Output to

In each of the above embodiments, the transmission P
E obtains the real PE number from the logical PE number, issues a request to the PE of this real PE number, and the receiving PE receiving the request obtains the real address in PE from the virtual address in PE. In this way, by performing the address conversion in two stages by the sending PE and the receiving PE, all the PEs
Does not need to have a copy of the translation table, so that the amount of hardware in the address translation table is reduced, and the address translation is accelerated with the reduction in the amount of hardware.

In the above system, for example, the contents of the page table 14 shown in FIG. 1 are frequently changed. In this case, conventionally, it was necessary to broadcast the updated contents of the table to all PEs, but this is not necessary in the above embodiment. In the above embodiment, the network has a crossbar network, but the network is not limited to this.

[0058]

According to the present invention, in a distributed memory type multiprocessor system, an increase in the amount of hardware for an address translation table accompanying an increase in the number of processors can be suppressed. The system can be realized.

Further, when updating the address conversion table,
Since it is not necessary to broadcast the updated address translation table to each PE, overhead at the time of updating the address translation table is reduced, and the processing speed of the system is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing details of a network.

FIG. 3 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a multiprocessor system.

FIG. 5 is a diagram showing a configuration of a packet.

[Explanation of symbols]

 1-1 to 1-N PE (processor element) 2 network 3 crossbar network 4 switch 5-1 to 5-N transmission line 6-1 to 6-N reception line 10-i transmission PE 10-j reception PE 11 system Address register 12 Real address register 13 PE conversion table 14 Page table 20 Network 20a Request reception unit 20b Address / data reception unit 20c Data length recognition unit 20d Destination PE recognition unit 20e Data length control unit 20f Network switch connection / disconnection control unit 20g Connection Switch 21 Request issuing circuit 22 Register 30i Sending PE 30j Receiving PE 31 System address register 32 Real address register 33 PE conversion table 34 Segment table 35 Page table 36,37 Adder circuit 40 Net Work 41 Request issuing circuit 42 STO register 43 PX register 44 BX register

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Nobuyuki Sugiura 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Teruo Utsumi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 72) Inventor Masami Dewa 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-2-1421863 (JP, A) JP-A-1-149159 (JP, A) JP-A Sho 62-100858 (JP, A) JP-A-63-85846 (JP, A) JP-A-2-228744 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/08 -12/12 G06F 15/16-15/177

Claims (11)

(57) [Claims] 1. A multi-processor wherein a plurality of processors each having a storage device are connected, and a storage device is mutually accessible by converting a logical address in the system common to the plurality of processors into a real address of each processor. A processor constituting a processor system, wherein the logical processor numbers included in the logical addresses in the system are:
First to convert logical processor numbers to real processor numbers
And a second conversion unit for converting a logical address in the processor relating only to its own processor into a real address in the processor for the logical address in the processor included in the logical address in the system. Processor. 2. The processor of the real processor number,
2. The processor according to claim 1, further comprising means for transmitting a logical address in the processor included in at least the logical address in the system. 3. The processor according to claim 1, wherein the in-processor logical address has at least a logical page number, and wherein the second converting means converts the logical page number into a real page number. The processor according to any one of the above. 4. A plurality of processors each having a storage device are connected by a network, and the storage devices can be mutually accessed by converting a logical address in the system common to the plurality of processors into a real address of each processor. A multiprocessor system, wherein each of the processors has a logical processor number included in the in-system logical address;
First to convert logical processor numbers to real processor numbers
And a second conversion unit for converting a logical address in the processor relating only to its own processor into a real address in the processor for the logical address in the processor included in the logical address in the system. Multiprocessor system. 5. The multiprocessor system according to claim 4, wherein each of the processors includes a unit for transmitting at least a logical address in the processor included in the logical address in the system to the processor of the real processor number. . 6. The multiprocessor system according to claim 5, wherein said network includes means for transferring the in-processor logical address to a processor corresponding to a real processor number sent from the processor. 7. The processor according to claim 4, wherein the in-processor logical address has at least a logical page number, and wherein the second converting means converts the logical page number into a real page number. The multiprocessor system according to any one of the above. 8. A multi-processor system in which a plurality of processors each having a storage device are connected, and a storage device can be mutually accessed by converting a logical address in the system common to the plurality of processors into a real address of each processor. A processor constituting a processor system, wherein the logical processor numbers included in the logical addresses in the system are:
First to convert logical processor numbers to real processor numbers
For the logical segment number included in the in-system logical address, for all the logical segment numbers,
Second conversion means for converting a logical segment number into a head address of a page table corresponding to the logical segment number; and, for a logical page number included in the in-system logical address, a logical page number relating only to its own processor to a real page. A third conversion means for converting the number into a number. 9. The processor of the real processor number,
9. The processor according to claim 8, further comprising means for transmitting at least a logical page number included in a logical address in the system and a head address of the converted page table. 10. The processor according to claim 9, wherein said third conversion means converts a logical page number into a real page number based on a head address of said page table. 11. A system in which a plurality of processors each having a storage device are connected by a network, and the storage devices can be mutually accessed by converting a logical address in the system common to the plurality of processors into a real address of each processor. A multiprocessor system, wherein each of the processors has a logical processor number included in the in-system logical address;
First to convert logical processor numbers to real processor numbers
For the logical segment number included in the in-system logical address, for all the logical segment numbers,
Second conversion means for converting a logical segment number into a head address of a page table corresponding to the logical segment number; and, for a logical page number included in the in-system logical address, a logical page number relating only to its own processor to a real page. A multiprocessor system, comprising: third conversion means for converting into a number.