JP3079387B2 - Main scanning reading device in image reading device using CCD - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main scanning reading device for reading a main scanning direction in an image reading device such as an image scanner using a CCD. The present invention relates to a main-scanning reading device for reading out.

[0002]

2. Description of the Related Art Conventionally, this kind of main scanning reading method has been performed in the following procedure.

FIG. 3 is a block diagram showing a configuration of an image reading apparatus to which a main scanning reading method using a CCD is applied. In the figure, reference numeral 10 denotes a C that outputs a control signal to the CCD 20.
A CD controller, 20 is a CCD, 30 is a CPU for controlling the entire image reading apparatus, 40 is an analog processing section for A / D converting a charge signal from the CCD 20 and adjusting the gain of an amplifier, and 45 is an A / D. An image memory for storing the converted data; 50, a digital image processing unit for processing the digital signal output from the image memory 45 as an image signal; 60, a digital image processing unit for communicating with the host computer 80; A host interface 70 for exchanging data; 70, an I / O unit for outputting a control signal to a light source, a motor, or the like;
80 is a host computer, and 90 is a clock generator.

The CCD controller 10 divides the clock CLK output from the clock generating section 90 by frequency division or the like to generate a reset pulse RS, transfer clocks φ ₁ , φ ₂ ,
A charge accumulation trigger SH is generated, and the RS, φ ₁ , φ _2, and SH are output to the CCD 20, and the RS, SH are output to the analog processing unit 40. In CCD 20 CCD control - an optical signal accumulated as charges in accordance with the charge accumulated trigger SH outputted from La 10, also the charge signal previously accumulated simultaneously, sequentially outputs to the analog processing unit 40 in accordance with the transfer clock phi _1, phi ₂ .

FIG. 4 is a timing chart for explaining the operation of the conventional main scanning reading method. An optical signal emitted from a light source (not shown) to a document (not shown) is accumulated in the CCD 20 for a time (tINT) corresponding to one cycle of the charge accumulation trigger SH. The charge signal stored in the CCD 20 is sent to the analog processing unit 40 according to the transfer clocks φ ₁ and φ ₂ from the fall of the charge storage trigger SH.
It is output as an output signal OS. As shown in the figure, as the CCD output signal OS, after a dummy signal such as idle feed is output, the effective pixel signal S is output by the number of effective pixels in the main scanning direction. Since the image reading apparatus of this embodiment has 5000 effective pixels per line in the main scanning direction,
5000 effective pixel signals S1 to S5000 are output.

The effective pixel signal S of the CCD output signal OS
Are A / D converted in the analog processing unit 40 and stored in the image memory 45. Further, after undergoing appropriate processing in the digital image processing section 50, the host computer 60 transmits the image data through the host interface 60.
Output to the data 80.

[0007]

However, in the above-described main scanning reading method in the conventional image reading apparatus,
Since the charge signal is read using the transfer clock and the reset pulse of the same frequency for the entire one line in the main scanning direction, the reading area is designated and the reading section in the main scanning direction is limited. However, there is also a problem that reading in the entire section of one line is required, and reading in the main scanning direction cannot be speeded up.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has been developed in an image reading apparatus using a CCD, which can read the main scanning direction at high speed when the reading section in the main scanning direction is limited. It is an object to provide a scanning reading device .

[0009]

In order to solve the above problems, the present invention provides a CCD, an analog processing section, an image memory, a CC,
Comprising a D controller and a CPU for controlling these,
Charges of pixels for one line in the main scanning direction stored in the CCD
Uses the transfer clock generated by the CCD controller
To the analog processing section, and the analog processing section
Is the A / D conversion of the effective pixel signal of the CCD output signal.
In the main scanning reading apparatus in an image reading apparatus using the configured CCD to store conversion to the image memory, C
The CD controller has a frequency divider, a reset pulse generator
Path, transfer clock generation circuit, charge accumulation trigger generation circuit,
Equipped with counter and comparator, frequency divider generates clock
Divide the clock from the circuit by a predetermined dividing ratio and reset
Pulse generation circuit, transfer clock generation circuit, charge storage
To the generator and counter, and the frequency division ratio is
The counter is configured to change with the output of
The same cycle as the reset pulse RS from the
The CPU is configured to be incremented by
From the scanning area specified by the
From what pixel to what pixel is read for the direction
Detect the desired section, and consider
Computes the start count value SC and end count value EC
From the charge accumulation trigger generation circuit.
When the charge accumulation trigger signal SH of the
The transfer clock is reset when the logical value becomes “0”.
CCD according to transfer clocks φ ₁ and φ ₂ from the clock generation circuit
From the analog processing unit
Comparison when the count value of is less than or equal to the start count value SC
Outputs the logical value “0” to the frequency divider and the image memory
Change the frequency division ratio of the frequency divider circuit to generate a reset pulse.
Reset pulse RS from circuit and transfer clock generation circuit
Reads the frequency of transfer clock φ ₁ and φ _{2 from}
Higher than in the case of
Do not write the charge signal from the CCD to the image memory
In this way, the count value of the counter is changed to the start count value SC.
≤ count value ≤ logical value if end count value EC
Outputs “1”, changes the frequency division ratio of the frequency divider, and resets
Reset pulse RS from the
Frequency of transfer clocks φ ₁ and φ ₂ from clock generation circuit
To Rutotomoni When the normal reading, processing in the analog processing unit
The charge signal OS from the processed CCD to the image memory
If the frequency of transfer clocks φ ₁ and φ ₂ is increased,
The combined CPU increases the amplifier gain of the analog processing unit .

[0010]

According to the present invention, a main scanning reading method in an image reading apparatus using a CCD is configured as described above, and in a section where an image is to be read, accumulated charges are transferred using a normal transfer clock, and an image is read. In the section other than the section where the reading is desired to be performed, the frequency of the transfer clock is increased within the range in which the charge is reliably transferred, and the charge is idlely fed. The main scanning direction can be read at high speed.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. The block diagram of the embodiment of the image reading apparatus to which the main scanning method according to the present invention is applied is the same as that shown in FIG.

FIG. 1 is a diagram showing a CCD controller 10 of an image reading apparatus to which the main scanning method according to the present invention is applied and its peripheral circuits. As shown in FIG.
The CD controller 10 includes a frequency divider 11, a reset pulse generator 12, a transfer clock generator 13, a charge accumulation trigger generator 14, a counter 15, and a comparator 16.

As shown in FIG. 1, a clock CLK generated by a clock generator 90 is frequency-divided by a frequency divider 11 a predetermined number of times, and a reset pulse (RS) generator 12 and transfer clocks (φ ₁ , φ ₂ ). The signals are output to the generation circuit 13, the charge accumulation trigger (SH) generation circuit 14, and the counter 15. Here, the frequency dividing circuit 11 outputs the output CO of the comparator 16.
The frequency division ratio can be changed by MP. When the output COMP of the comparator 16 is a logical value “0”, the frequency division is twice as large as that when the logical value is “1”. Have been. The counter 15 is configured to be incremented in the same cycle as the reset pulse RS, and the counter value is set to 0 by the charge accumulation trigger SH.
Is reset to The comparator 16 has a counter value of the counter 15 and a start count value SC output from the CPU 30.
And the end count value EC, and when SC ≦ (counter value of the counter 15) ≦ EC, the frequency dividing circuit 1
The configuration is such that a logical value “1” is output for “1”.
The output COMP of the comparator 16 is also connected to the write enable (WE) of the image memory 45,
5 indicates that when the WE is a logical value “1”, the analog processing unit 40
Can be written.

Next, the operation of this embodiment will be described with reference to FIGS. 1, 2 and 3. FIG. 2 is a timing chart for explaining the operation of the main scanning reading method according to the present invention. First, the host computer 8
At 0, the operator activates the application program on the host computer 80 and designates a range of the original document to be read as a reading area. The reading area is designated by designating a start point and an end point on the document.

The read area designated in the host computer 80 is transmitted through the host interface 60 to the CPU.
30 is input. The CPU 30 detects, from the reading area, the number of pixels and the number of pixels in the main scanning direction in which the section is to be read, calculates a start count value SC and an end count value EC, and compares SC and EC with each other. Give 16 Note that SC and FC are calculated in consideration of idle feeding and dummy pixels, respectively. Further, SC is determined so as to be several pixels before the pixel to start reading in order to increase the reliability of the transferred charge signal.

When the charge accumulation trigger SH has a logical value "1", the counter 15 is reset. Charge accumulation trigger S
When H changes from the logical value “1” to the logical value “0”, the transfer of charges is started according to the transfer clocks φ ₁ and φ ₂ , and the CCD output OS is output to the analog processing unit 40. The counter 15 is incremented in the same cycle as the reset pulse RS. At the start of charge transfer, a predetermined number of idle feed and dummy pixels are output. Here, when the counter value of the counter 15 is equal to or smaller than SC, COMP is a logical value "0", so that the frequency division of the frequency dividing circuit 11 is twice as large as that used for normal reading. Therefore, the reset pulse RS and the transfer clocks φ ₁ and φ ₂ also have twice the frequency of those used for normal reading.

When COMP is a logical value "0",
Since the WE of the image memory 45 also has the logical value “0”, data obtained by A / D converting the CCD output signal OS in the analog processing section 40 is not written in the image memory 45.

After the idle feed and dummy pixel are output from the CCD output OS, an effective pixel signal S is output. However, since the counter value of the counter 15 is set to the window outside the pixel in the following cases SC, 2 times the transfer clock phi ₁ frequency, the effective pixel signal at high speed using the phi ₂ S when used for normal reading Is performed. Here, the out-of-window pixel refers to a pixel that is not in a section to be read out of the effective pixels output as the effective pixel signal S, and the in-window pixel refers to a pixel in a section to be read out.

When the counter value of the counter 15 becomes SC, the output COMP of the comparator 16 becomes a logical value "1".
When the logical value "1" of COMP is input to the frequency divider 11,
The frequency division is halved to a frequency used for normal reading. Therefore, the reset pulse RS, the transfer clock φ ₁ ,
also becomes frequency when used for normal reading for phi _2, the effective pixel signal S of a window in the pixel is output A / D conversion to the analog processing unit 40 with a normal transfer speed.
Here, since COMP has the logical value "1", the WE of the image memory 45 also has the logical value "1", and the CCD output signal OS
Are A / D converted by the analog processing unit 40 and then written into the image memory 45.

When the counter value of the counter 15 becomes EC, the output COMP of the comparator 16 becomes a logical value "0".
When the logical value “0” of COMP is input, the frequency dividing circuit 11 doubles the frequency dividing. Therefore, since the pixels are outside the window thereafter, the effective pixel signal S is transferred at a high speed by using the transfer clocks φ ₁ and φ ₂ having twice the frequency used in normal reading. When COMP becomes a logical value "0", WE of the image memory 45 also becomes a logical value "0", so that data obtained by A / D conversion of the CCD output signal OS is not written in the image memory 45.

By accelerating the transfer clock and the like as described above, the charge accumulation time (tINT) for one line in the main scanning direction is shortened, and the output level of the CCD output OS is reduced. The CPU 30 controls the analog processing unit 40 to increase the amplifier gain so that the output of the analog processing unit 40 is adjusted to a constant level.

In this embodiment, the transfer of the pixel signal is performed for the out-of-window pixels using a transfer clock having a frequency twice as high as that of the normal pixel. However, the frequency of the transfer clock is not limited to this. It does not matter if the signal is within the range where the signal is reliably transferred.

[0023]

According to the present invention , the following excellent effects are obtained.
Fruit is obtained. In the reading in the main scanning direction, the accumulated charge is transferred using the normal transfer clock in the section where the image is to be read, and the charge is reliably transferred in the section other than the section where the image is to be read. Since the frequency of the transfer clock is increased within the range and the charge is idlely fed, the main scanning direction can be read at high speed. Also,
When the generation frequency of the transfer clocks φ ₁ and φ ₂ is increased, CP
U increases the amplifier gain of the analog processing section.
The output of the analog processor can be set to a certain level.
You.

[Brief description of the drawings]

FIG. 1 is a diagram showing a CCD controller 10 of an image reading apparatus to which a main scanning method according to the present invention is applied and peripheral circuits thereof.

FIG. 2 is a timing chart for explaining the operation of the main scanning reading method according to the present invention.

FIG. 3 is a block diagram illustrating a configuration of an image reading apparatus to which a main scanning reading method using a CCD is applied.

FIG. 4 is a timing chart for explaining the operation of the conventional main scanning reading method.

[Explanation of symbols]

 Reference Signs List 10 CCD controller 11 Divider circuit 12 Reset pulse generator circuit 13 Transfer clock generator circuit 14 Charge accumulation trigger generator circuit 15 Counter 16 Comparator 20 CCD 30 CPU 40 Analog processing unit 90 Clock generation unit

Claims (1)

(57) [Claims] A CCD, an analog processing unit, an image memory,
CD controller and CPU for controlling these
The image for one line in the main scanning direction stored in the CCD
Transfer of elementary charge signals from the CCD controller
It is sequentially transferred to the analog processing unit using a clock, and
The analog processing section has an output signal from the CCD.
A / D convert the effective pixel signal and store it in the image memory.
In the main scanning reading device in the image reading device using the CCD configured as described above, the CCD controller includes a frequency dividing circuit, a reset pulse,
Generation circuit, transfer clock generation circuit, charge accumulation trigger generation
A circuit, a counter, and a comparator, wherein the frequency divider circuit receives a clock from a clock generation circuit in a predetermined manner.
The reset pulse generating circuit,
A transfer clock generation circuit, the charge accumulation trigger generation circuit,
And the division ratio is output to the comparator.
And the counter is reset by the reset pulse generation circuit.
It is incremented in the same cycle as the reset pulse RS
And the CPU has a reading area designated by a host computer.
From what pixel to what pixel in the main scanning direction
Detects whether it is a section to be read,
Count value SC and end count value EC in consideration of the element
And a charge accumulation trigger signal from the charge accumulation trigger generation circuit.
When SH becomes a logical value "1", the counter is reset.
When the logic value becomes "0", the transfer clock generation circuit
Collection from the CCD according to et the transfer clock phi _1, phi ₂
A load signal is output to the analog processing unit, and the counter
When the count value is equal to or less than the start count value SC
The comparator outputs a logical value “0” to the frequency dividing circuit or the image memory.
Output to the memory, changing the frequency division ratio of the frequency dividing circuit,
Reset pulse RS from reset pulse generation circuit or before
Serial transfer transfer clock φ ₁ from the clock generation circuit, of φ ₂
While making the generated frequency higher than in normal reading,
Charge from the CCD processed by the analog processing unit
Signal is not written to the image memory,
The count value of the counter is the start count value SC ≦ counter
Logical value if the bets value ≦ the completion count value EC to "1"
Output, changing the frequency division ratio of the frequency divider circuit,
Reset pulse RS from the pulse generator and the transfer
Transfer clock phi ₁ from the clock generation circuit, phi ₂ of the generating circumference
In the case of normal reading of the wave number, the analog processing is performed.
The charge signal OS from the CCD processed by the
Writing in the image memory, the transfer clock phi _1, phi ₂ of the origination
When the raw frequency is increased, the CPU performs the analog processing.
A main scanning reading device in an image reading device using a CCD, wherein an amplifier gain of a section is increased .