JP3074910B2 - Division device - Google Patents

Division device

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Publication number
JP3074910B2
JP3074910B2 JP04050337A JP5033792A JP3074910B2 JP 3074910 B2 JP3074910 B2 JP 3074910B2 JP 04050337 A JP04050337 A JP 04050337A JP 5033792 A JP5033792 A JP 5033792A JP 3074910 B2 JP3074910 B2 JP 3074910B2
Authority
JP
Japan
Prior art keywords
quotient
equation
subtracting
division
dividing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP04050337A
Other languages
Japanese (ja)
Other versions
JPH05250145A (en
Inventor
光 森田
中皇 楊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP04050337A priority Critical patent/JP3074910B2/en
Publication of JPH05250145A publication Critical patent/JPH05250145A/en
Application granted granted Critical
Publication of JP3074910B2 publication Critical patent/JP3074910B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、除算装置に関し、特に
上位ブロック間の近似的な除算結果を用いて多数桁の商
および剰余を求める除算装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a division device, and more particularly to a division device for obtaining a quotient and a remainder of many digits by using an approximate division result between upper blocks.

【0002】[0002]

【従来の技術】汎用計算機を初め汎用マイクロプロセッ
サを用いるシステム等において、正整数A,Nが与えら
れ、A/Nなる割算を実行することで、剰余と商を求め
る場合について考えてみる。例えば、A,Nは対応する
メモリに書き込まれ、AとNはそれぞれに対応して、A
i,Nj(0≦i≦m−1,0≦j≦n−1,n≦m)で
示されるm個かn個のブロックに分けられ、
2. Description of the Related Art Consider a case where positive integers A and N are given in a general-purpose computer and a system using a general-purpose microprocessor, etc., and a remainder and a quotient are obtained by executing A / N division. For example, A and N are written to the corresponding memory, and A and N correspond to A and N respectively.
i, Nj (0≤i≤m-1, 0≤j≤n-1, n≤m) divided into m or n blocks,

【数6】 と表現され、rを基数とし各AiとNjは0よりr−1ま
での整数で表現されるとする。従来方法において、もし
2ブロックを1ブロックで除する演算手段しかない場
合、i=m−1、q=0に初期設定した後、
(Equation 6) Where Ai and Nj are each represented by an integer from 0 to r-1 using r as a radix. In the conventional method, if there is only an operation means for dividing two blocks by one block, after initializing i = m−1 and q = 0,

【数7】 なる商を求め、(Equation 7) Seeking a quotient

【数8】 なる演算をiを減じつつ繰返し処理する。但し、(Equation 8) Is repeated while reducing i. However,

【数9】 はxを超えない最大の整数を示し、x‖yはr×x+y
を表わす。なお、従来の除算装置に関するものとして
は、例えば、「萩原 宏著、電子計算機通論2、朝倉書
店、pp.135〜174」、「HWANG著、コンピ
ュータの高速演算方式、(株)近代科学社刊」等があ
る。
(Equation 9) Represents the largest integer not exceeding x, and x‖y is r × x + y
Represents Examples of the conventional division device include, for example, “Hiroshi Hagiwara, Computer Science, 2, Asakura Shoten, pp. 135-174”, “HWANG, High-speed Computer Computing System,” published by Modern Science Co., Ltd. And so on.

【0003】[0003]

【発明が解決しようとする課題】上記従来技術では、A
が負になるケースを判断する必要があり、除算の高速化
の妨げとなっていた。本発明の目的は、このような問題
点を改善し、演算処理を高速化するのに好適な除算装置
を提供することにある。
In the above prior art, A
It is necessary to judge the case where is negative, which hinders speeding up of division. An object of the present invention is to improve such a problem and to provide a division device suitable for speeding up arithmetic processing.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するた
め、本発明の除算装置は、従来と同じく、i=m−1よ
り初め、上記の式(3)および(4)で示した計算を行
ない、Aの桁数を減らすとともにiを減らしつつ、これ
を繰返し実行するが、特に、次式(5)で示す商Qを用
いることに特徴がある。
In order to achieve the above object, the dividing apparatus of the present invention performs the calculations shown in the above equations (3) and (4) starting from i = m-1 as in the prior art. This is repeatedly performed while reducing the number of digits of A and reducing i, and is characterized by using a quotient Q expressed by the following equation (5).

【数10】 すなわち、メモリとALUとを備えた除算装置におい
て、正整数A,Nが与えられ、A/Nを超えない最大の
整数である商と剰余を求め、A,Nおよび途中経過i,
qをメモリ領域に書き込み、A,Nは、Ai,Nj(0≦
i≦m−1,0≦j≦n−1,n≦m)で示されるm個
かn個の部分に分けられ、上記式(1)で表現され、r
を基数とし各Ai,Njは0よりr−1までの整数で表現
され、r/2≦Nn-1となるとき、iにm−1を、qに
0を蓄積して初期化する第1のステップと、Aの上位桁
AiがNn-1+1以上の場合に限り、
(Equation 10) That is, in a dividing device having a memory and an ALU, positive integers A and N are given, and a quotient and a remainder, which are the largest integers not exceeding A / N, are obtained.
q is written to the memory area, A and N are Ai, Nj (0 ≦
i ≦ m−1, 0 ≦ j ≦ n−1, n ≦ m) and is divided into m or n parts, expressed by the above equation (1), and r
Ai, Nj are represented by integers from 0 to r−1, and when r / 2 ≦ Nn−1, m−1 is stored in i and 0 is stored in q to initialize. And if the upper digit Ai of A is Nn-1 + 1 or more,

【数11】 をAから減じ、qに1を蓄積する第2のステップと、A
の上位桁r×Ai+Ai-1をNの上位桁Nn-1に1を加算
した除数で除した商Qを求め、
[Equation 11] A second step of subtracting A from A and accumulating 1 in q;
The quotient Q is obtained by dividing the high-order digit r × Ai + Ai-1 of N by a divisor obtained by adding 1 to the high-order digit Nn-1 of N,

【数12】 をAから減じ、r×q+Qでqを更新する第3のステッ
プと、再び、Aの上位桁r×Ai+Ai-1をNの上位桁N
n-1に1を加算した除数で除した商Qを求め、Q=0で
ない場合、式(6)の値をAから減じ、q+Qでqを更
新する第4のステップと、Aの上位桁Ai-1がNn-1+1
以上の場合に限り、
(Equation 12) Is subtracted from A, and q is updated by r × q + Q. Again, the upper digit r × Ai + Ai−1 of A is changed to the upper digit N of N.
A fourth step of obtaining a quotient Q obtained by dividing the divisor by adding 1 to n-1 and, if Q = 0, subtracting the value of equation (6) from A and updating q by q + Q, and the upper digit of A Ai-1 is Nn-1 + 1
Only in the above cases,

【数13】 をAから減じ、q+1でqを更新する第5のステップ
と、iから1を減じる第6のステップと、i>n−1の
場合、第3のステップへ戻る第7のステップと、i>n
−1ではなく、かつA<Nの場合、qを商、Aを剰余と
する第8のステップと、i>n−1ではなく、かつA<
Nではない場合、AからNを減ずるとともにqに1を加
え、第8のステップへ戻る第9のステップを有する処理
を行なうことに特徴がある。
(Equation 13) A fifth step of subtracting 1 from A and updating q by q + 1, a sixth step of subtracting 1 from i, a seventh step of returning to the third step if i> n−1, and i> n
If −1 and A <N, an eighth step in which q is a quotient and A is a remainder, and i is not i> n−1 and A <N
If it is not N, the process is characterized by performing a process having a ninth step of subtracting N from A, adding 1 to q, and returning to the eighth step.

【0005】[0005]

【作用】本発明においては、商Qを求めるため、上記
(5)式を実行する除数Qを用いれば、
In the present invention, in order to obtain the quotient Q, if the divisor Q for executing the above equation (5) is used,

【数14】 なる性質があるため、式(5)を用いて生成されたQを
用いる上記式(3)により生成されるAは、常に正であ
ることが保証される。なぜなら、式(3)、(5)、
(9)より、
[Equation 14] Therefore, A generated by the above equation (3) using Q generated by using the equation (5) is always guaranteed to be positive. Because, equations (3), (5),
From (9),

【数15】 であるため、負の値を扱うことに伴う条件判定等の処理
は不要であり、除算処理を高速化することができる。
(Equation 15) Therefore, processing such as condition determination accompanying the handling of a negative value is unnecessary, and the division processing can be sped up.

【0006】[0006]

【実施例】以下、本発明の一実施例を図面により説明す
る。図1は、本発明の一実施例における除算装置の処理
を示すフローチャート、図2は本発明の一実施例におけ
る除算装置の要部を示す構成図である。図2において、
21は商A,Nおよび途中経過i,qを蓄積するための
メモリ領域、22はブロック単位の加算、乗算、除算を
実現する算術論理ユニット(ALU)である。本実施例
の除算装置では、メモリ領域21、ALU22、および
除算に関する一連の処理を行なう制御手段(図2には示
さず)とによって、図1に示す手順で除算処理を行な
う。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing the processing of the division device according to one embodiment of the present invention, and FIG. 2 is a configuration diagram showing the main parts of the division device according to one embodiment of the present invention. In FIG.
Reference numeral 21 denotes a memory area for storing the quotients A and N and intermediate progresses i and q, and reference numeral 22 denotes an arithmetic logic unit (ALU) for realizing addition, multiplication, and division in block units. In the division device of the present embodiment, the division process is performed by the procedure shown in FIG. 1 by the memory area 21, the ALU 22, and the control means (not shown in FIG. 2) for performing a series of processes related to the division.

【0007】次に、図1を用い、除算処理の手順につい
て述べる。本実施例では、正整数A,Nが与えられ、A
/Nを超えない最大の整数である商と剰余を求め、A,
N,i,qをメモリ領域21に書き込み、A,Nは、A
i,Nj(0≦i≦m−1,0≦j≦n−1,n≦m)で
示されるm個かn個の部分に分けられ、前記(1)式で
表現されるものとする。また、rを基数とし、Ai,Nj
は0よりr−1までの整数で表現されるものとし、r/
2≦Nn-1とする(101)。また、整数Aを表わすの
に、mブロック必要な場合、iにm−1を、qに0を蓄
積して初期化し(102)、ステップ103において、
Ai≧Nn-1+1の場合、前記(6)式の値をAから減
じ、qに1を蓄積する(104)。そして、Aの上位桁
r×Ai+Ai-1をNの上位桁Nn-1に1を加算した除数
で除した商Qを求め、前記(7)式の値をAから減じ、
r×q+Qでqを更新する(105)。次に、再び、A
の上位桁r×Ai+Ai-1をNの上位桁Nn-1に1を加算
した除数で除した商Qを求め、Q=0でない場合、式
(7)の値をAから減じ、q+Qでqを更新し(10
6)、ステップ107において、Ai-1≧Nn-1+1の場
合、前記(8)式の値をAから減じ、q+1でqを更新
する(108)。そして、iから1を減じる(10
9)。その結果、iがn−1より大きければ(11
0)、ステップ105に戻り、iがn−1より大きくな
ければ、次のステップへ進む。次のステップ111にお
いて、A<Nである場合、qを商、Aを剰余として出力
する(113)。また、A<Nでない場合には、Aから
Nを減ずるとともにqに1を加え(112)、再び、A
<Nか否かをチェックする(111)。
Next, the procedure of the division process will be described with reference to FIG. In this embodiment, positive integers A and N are given.
The quotient and the remainder, which are the largest integers not exceeding / N, are obtained.
N, i, and q are written to the memory area 21, and A and N
i, Nj (0 ≦ i ≦ m−1, 0 ≦ j ≦ n−1, n ≦ m) divided into m or n parts and represented by the above formula (1) . Also, r is a radix, and Ai, Nj
Is represented by an integer from 0 to r-1, and r /
It is assumed that 2 ≦ Nn−1 (101). When m blocks are required to represent the integer A, m-1 is stored in i and 0 is stored in q to initialize (102).
When Ai ≧ Nn-1 + 1, the value of the above equation (6) is subtracted from A, and 1 is stored in q (104). Then, a quotient Q is obtained by dividing the upper digit r × Ai + Ai−1 of A by the divisor obtained by adding 1 to the upper digit Nn−1 of N, and subtracting the value of the above equation (7) from A,
q is updated by r × q + Q (105). Then again, A
Is obtained by dividing the high-order digit r × Ai + Ai-1 of N by a divisor obtained by adding 1 to the high-order digit Nn-1 of N. If Q = 0 is not obtained, the value of the equation (7) is subtracted from A, and q + Q gives q Is updated (10
6) In step 107, if Ai-1 ≧ Nn-1 + 1, the value of the above equation (8) is subtracted from A, and q is updated by q + 1 (108). Then, subtract 1 from i (10
9). As a result, if i is greater than n-1, (11
0), returning to step 105, if i is not greater than n-1, proceed to the next step. In the next step 111, if A <N, q is output as a quotient and A as a remainder (113). If A <N is not satisfied, N is subtracted from A and 1 is added to q (112).
It is checked whether or not <N (111).

【0008】ここで、具体的な例を挙げ、本実施例の演
算方法を示す。本実施例では、「965432÷562
1」を演算して「商171余り4241」を求める場合
について述べる。まず、基数r=10(10進法)と
し、データ構造は、 A=A5‖A4‖A3‖A2‖A1‖A0=9‖6‖5‖4‖3‖2 N= N3‖N2‖N1‖N0= 5‖6‖2‖1 とする。なお、10進法で誤解の心配はないため、以
下、区切り記号‖は省略する。これにより、次に示す
(1)〜(8)の順に除算処理を行なう。 (1)i=6−1=5,q=0 (2)A5=9>N3+1=6より、
Here, a specific example will be given to show the calculation method of this embodiment. In this embodiment, “965432 ÷ 562”
1 will be described to obtain “quotient 171 remainder 4241”. First, radix r = 10 (decimal system), and the data structure is A = A 5 ‖A 4 ‖A 3 ‖A 2 ‖A 1 ‖A 0 = 9‖6‖5‖4‖3‖2 N = It is assumed that N 3 ‖N 2 ‖N 1 ‖N 0 = 5‖6‖2‖1. Since there is no risk of misunderstanding in the decimal system, the separator ‖ is omitted below. As a result, division processing is performed in the following order (1) to (8). (1) i = 6-1 = 5, q = 0 (2) From A 5 = 9> N 3 + 1 = 6,

【数16】 q=1 (3)Q=40/6」=6,(Equation 16) q = 1 (3) Q = 40/6 "= 6

【数17】 q=10×1+6=16 (4)Q=06/6」=1,[Equation 17] q = 10 × 1 + 6 = 16 (4) Q = 0/6/6 ”= 1

【数18】 q=16+1=17 (5)A4=0<N3+1=6より、Aとqはそのまま。 (6)i=5−1=4 (7)4>3より、(3)へ戻る。 (3)Q=09/6」=1,(Equation 18) q = 16 + 1 = 17 (5) Since A 4 = 0 <N 3 + 1 = 6, A and q remain as they are. (6) i = 5-1 = 4 (7) Returning to (3) from 4> 3. (3) Q = 09/6 "= 1

【数19】 q=10×17+1=171 (4)Q=04/6」=0,Aとqはそのまま。 (5)A3=4<N3+1=6より、Aとqはそのまま。 (6)i=3−1=2 (7)i=3 (8)A=4241<N=5621より、商q=17
1、剰余A=4241を結果として出力する。 なお、本実施例のように基数10の場合、Nの最上位ブ
ロックが5以上でなければならないが、実利用ではrが
2のべき乗のため、Nをシフトして最上位ビットを1と
してから開始すればよい。
[Equation 19] q = 10 × 17 + 1 = 171 (4) Q = 04/6 ”= 0, A and q remain as they are. (5) Since A 3 = 4 <N 3 + 1 = 6, A and q remain as they are. (6) i = 3-1 = 2 (7) i = 3 (8) From A = 4241 <N = 5621, the quotient q = 17
1. The remainder A = 4241 is output as a result. In the case of radix 10 as in the present embodiment, the most significant block of N must be 5 or more. However, in actual use, since r is a power of 2, shifting N and setting the most significant bit to 1 Just start.

【0009】[0009]

【発明の効果】本発明によれば、負の値を扱うことに伴
う処理を不要にし、かつ上位ブロック間の近似的な除算
結果を用いて多数桁の商および剰余を求めることができ
る。これにより、除算処理を高速化することが可能であ
る。
According to the present invention, it is possible to eliminate the processing involved in handling negative values, and to obtain a quotient and remainder of many digits by using an approximate division result between upper blocks. This makes it possible to speed up the division process.

【0010】[0010]

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例における除算装置の処理を示
すフローチャートである。
FIG. 1 is a flowchart illustrating a process of a division device according to an embodiment of the present invention.

【図2】本発明の一実施例における除算装置の一部を示
す構成図である。
FIG. 2 is a configuration diagram illustrating a part of a division device according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

21 メモリ領域 22 ALU 21 Memory area 22 ALU

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 ALUと、除数、被除数、および途中経
過を蓄積するメモリ領域とを備えた除算装置において、
該ALUを制御し、正整数A,Nが与えられ、A/Nを
超えない最大の整数である商と剰余を求め、該A,Nお
よび途中経過i,qを該メモリ領域に書き込み、A,N
は、Ai,Nj(0≦i≦m−1,0≦j≦n−1,n≦
m)で示されるm個かn個の部分に分けられ、 【数1】 と表現され、rを基数とし各Ai,Njは0よりr−1ま
での整数で表現され、r/2≦Nn-1となるとき、iに
m−1を、qに0を蓄積して初期化する第1のステップ
と、Aの上位桁AiがNn-1+1以上の場合に限り、 【数2】 をAから減じ、qに1を蓄積する第2のステップと、A
の上位桁r×Ai+Ai-1をNの上位桁Nn-1に1を加算
した除数で除した商Qを求め、 【数3】 をAから減じ、r×q+Qでqを更新する第3のステッ
プと、再び、Aの上位桁r×Ai+Ai-1をNの上位桁N
n-1に1を加算した除数で除した商Qを求め、Q=0で
ない場合、 【数4】 をAから減じ、q+Qでqを更新する第4のステップ
と、Aの上位桁Ai-1がNn-1+1以上の場合に限り、 【数5】 をAから減じ、q+1でqを更新する第5のステップ
と、iから1を減じる第6のステップと、i>n−1の
場合、第3のステップへ戻る第7のステップと、i>n
−1ではなく、かつA<Nの場合、qを商、Aを剰余と
する第8のステップと、i>n−1ではなく、かつA<
Nではない場合、AからNを減ずるとともにqに1を加
え、第8のステップへ戻る第9のステップとから構成さ
れた処理を行なわせる制御手段とを備えたことを特徴と
する除算装置。
1. A dividing apparatus comprising an ALU, a divisor, a dividend, and a memory area for accumulating progress information.
The ALU is controlled, given positive integers A and N, obtaining a quotient and a remainder that are the largest integers not exceeding A / N, writing the A, N and intermediate progresses i and q to the memory area, , N
Are Ai, Nj (0≤i≤m-1, 0≤j≤n-1, n≤
m) divided into m or n parts shown by And each Ai, Nj is represented by an integer from 0 to r-1 using r as a radix. When r / 2≤Nn-1, m-1 is stored in i and 0 is stored in q. The first step of initialization and only if the upper digit Ai of A is greater than or equal to Nn-1 + 1, A second step of subtracting A from A and accumulating 1 in q;
The quotient Q is obtained by dividing the high-order digit r × Ai + Ai-1 of N by the divisor obtained by adding 1 to the high-order digit Nn-1 of N, and Is subtracted from A, and q is updated by r × q + Q. Again, the upper digit r × Ai + Ai−1 of A is changed to the upper digit N of N.
The quotient Q obtained by dividing by 1 to the divisor obtained by adding 1 to n-1 is obtained. Is subtracted from A, and q is updated by q + Q, and only when the upper digit Ai-1 of A is Nn-1 + 1 or more, A fifth step of subtracting 1 from A and updating q by q + 1, a sixth step of subtracting 1 from i, a seventh step of returning to the third step if i> n−1, and i> n
If −1 and A <N, an eighth step in which q is a quotient and A is a remainder, and i is not i> n−1 and A <N
A ninth step of subtracting N from A, adding 1 to q, and returning to the eighth step if the value is not N;
JP04050337A 1992-03-09 1992-03-09 Division device Expired - Lifetime JP3074910B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04050337A JP3074910B2 (en) 1992-03-09 1992-03-09 Division device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04050337A JP3074910B2 (en) 1992-03-09 1992-03-09 Division device

Publications (2)

Publication Number Publication Date
JPH05250145A JPH05250145A (en) 1993-09-28
JP3074910B2 true JP3074910B2 (en) 2000-08-07

Family

ID=12856110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04050337A Expired - Lifetime JP3074910B2 (en) 1992-03-09 1992-03-09 Division device

Country Status (1)

Country Link
JP (1) JP3074910B2 (en)

Also Published As

Publication number Publication date
JPH05250145A (en) 1993-09-28

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