JP3068504U - Semiconductor test equipment - Google Patents

Abstract

(57) [Summary] In a semiconductor test apparatus having a calibration function for correcting a characteristic variation of a level variable functional element provided in a tester pin, each time a device test condition for changing a setting condition for the level variable functional element is changed. Provided is a semiconductor test apparatus that performs point calibration under set conditions to eliminate a correction error to a variable function element. During execution of a device test program, each time a device test for changing the logic setting data for the variable level function element is performed, a point calibration is performed on the value of the logic setting data immediately before executing the device test. When the point setting data is obtained, or when the value of the logical setting data is the same as that at the time of performing the previous point calibration, the previous point setting data is reused without performing the point calibration, and the obtained point is obtained. A semiconductor test device that performs a device test immediately after applying setting data.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 This invention relates to a semiconductor test apparatus. In particular, a plurality of tester pins are provided with a plurality of channel variable level functional elements, and the level variable functional elements incorporate a DAC (DA converter) to change the analog level under various setting conditions by software. Can be. The present invention relates to a semiconductor test apparatus capable of preventing a decrease in device test accuracy (test condition setting accuracy and measurement accuracy) even when non-linearity characteristics are exhibited in all variable setting sections of the level variable functional element.

[0002]

[Prior art]

 The prior art will be described below with reference to FIGS. 4, 5, 6, and 7. FIG. It should be noted that since the semiconductor test apparatus is well-known and well-known in the art, detailed description of the entire system except for the main part is omitted. 2. Description of the Related Art A semiconductor test apparatus includes a large number of channels for testing a DUT (device under test), for example, hundreds to thousands of tester pins. A plurality of variable function elements that can be individually set and controlled for each tester pin are provided. The variable level function element is an element that includes a DAC (DA converter) and changes a test condition related to a voltage level of a device. For example, a level setting condition of signal application to the device and a response from the device are provided. The level setting conditions when measuring signals are variable. More specifically, VIH, VIL, and DUT, which are provided for each channel of the tester pin in the system configuration of FIG. 5 and vary the high / low voltage level applied to the DUT to the pin electronics driver DR, are provided. To the comparator CP that receives the output response signal, VOH and VOL that convert to a logic signal at a high / low voltage level of a predetermined threshold level, IL that applies a constant current load to the DUT, and the IC terminal of the DUT There is a VTT or the like that applies a termination voltage via a termination resistor. Each of these level variable function elements is provided with a DAC. The control CPU sets desired DA data in the DAC, and the level of each element is made variable using a variable voltage generated by the DAC.

As shown in FIG. 4, each level variable functional element is provided with a DAC correction arithmetic unit that corrects variations in characteristics due to variations in circuit configuration and components. The main configuration of the level variable functional element system including the DAC correction operation device shown in FIG. 4 is as follows. The DAC correction operation device includes a plurality of N-channel setting data registers 100, an offset correction register 200, and a gain correction register 300. , A plurality of M-channel arithmetic units 500, and a plurality of N-channel DACs 800 and a functional element 980 on the level variable function element side.

The setting data register 100 is a register provided for each channel and storing logic data when there is no variation in circuit response. Each time the test condition is changed from the device test program, it is written to the corresponding setting data register 100 via the tester bus TBUS. The output setting data 100 s is supplied to the arithmetic unit 500. The offset correction register 200 is provided for each channel and is a storage register for correcting an offset variation of each functional element 980. The offset correction register 200 is written to the corresponding offset correction register 200 via the tester bus TBUS in the same manner as described above. Normally, the correction value obtained after calibration is set once and held until the next calibration. The output, the offset correction data 200 s, is supplied to the arithmetic unit 500. The gain correction register 300 is provided for each channel and is a storage register for correcting a gain variation of each functional element 980, and is written to the corresponding gain correction register 300 via the tester bus TBUS. As described above, the correction value obtained after the execution of the calibration is set once and held until the next calibration. The output, that is, the gain correction data 300 s is supplied to the arithmetic unit 500.

The arithmetic unit 500 has a plurality of M channels for parallel processing in a short time, and receives predetermined setting data 100 s of the updated channel, offset correction data 200 s and gain correction data 300 s, and receives a predetermined number of channels. The DA data 500 s obtained as a result of the above correction operation is written and set in the DAC 800 R of the corresponding channel. Here, there are two types of correction operation modes. The first correction calculation mode is a mode in which the DA data 500 s calculated by the calculation formula of (setting data × gain correction data) + offset correction data is output. In the second correction operation mode, no operation is performed, and the offset correction data is output as it is as DA data 500s.

The DAC 800 is an N-channel DA converter. The DAC 800 includes a latch register 800 R inside, latches the DA data 500 s, and supplies an analog voltage corresponding to the code data to each functional element 980. I have. The functional element 980 is a variable level various functional element provided in the pin electronics, and is, for example, the above-described driver DR, comparator CP, termination voltage VTT, or constant current load IL.

Next, calibration will be described with reference to FIGS. 6 and 7. Calibration is a correction that corrects the variation in characteristics due to the variation in the circuit configuration and parts of the level variable functional elements of all channels so that the semiconductor test equipment can maintain the specified device test performance. The amount is determined by predetermined measurement, and correction data is set in the offset correction register 200 and the gain correction register 300 of each channel described above. For example, the calibration is performed by executing the initialization program (INIT) after the power is turned on. Further, calibration can be performed if necessary. FIG. 6A is an example of a typical linear characteristic variation of one channel. When the horizontal axis is the code value of the DA data 500s, the vertical axis is the output level finally output by the variable level function element of the channel. The ideal characteristic shown in FIG. 6A is an ideal straight line proportional to DA data in a ratio of 1: 1. For example, when the driver's VIH setting data 100s gives a code value of "300", the actual output level, that is, the voltage level value of the DUT IC input terminal becomes 3.00V, and the code The output level when the value “0” is given is 0.00 V, which indicates an ideal proportional relationship of 1: 1. On the other hand, the output characteristic of FIG. 6B1 is a case where there is characteristic variation, and is an example of a naked output characteristic before correction. In this case, both the offset level and the gain deviate from the ideal characteristics (see FIG. 6A). In this state, by setting the offset correction data 200 s and the gain correction data 300 s obtained by the above-described calibration, the output characteristic after correction by the DA data 500 s corrected by the arithmetic unit 500 (see FIG. 6B2) can be corrected to match the ideal characteristic (see FIG. 6A). Therefore, by interposing the above-described DAC correction arithmetic unit, from the viewpoint of the device test program, by writing only the logical setting data 100s without considering the variation in the characteristics of the hardware, the predetermined test accuracy can be obtained. Will always be maintained.

Next, a problem when the level variable functional element has non-linear characteristic variation will be described with reference to FIG. FIG. 7A shows the case where the output characteristics after offset and gain correction by calibration have characteristic variations in a curve, and FIG. 7B3 shows the case where the characteristic curve shows a cubic function. Normally, as shown in FIG. 7 (a), the calibration is performed such that the specified three points (see FIGS. 7C, 7D, and 7E) match the ideal characteristics or have a minimum error. And both correction data are generated. However, in FIG. 7B3, as can be seen from FIG. 3, a large calibration error occurs at a position other than the calibration point in the level variable functional element exhibiting non-linear characteristics. However, this correction error is a direct error factor in the measurement accuracy of semiconductor test equipment. FIG. 7B shows an example in which the comparator CP shown in FIG. 5 converts a response signal (see A in FIG. 7B) of the DUT into a logic signal using VOH. At this time, the horizontal axis represents time, the vertical axis represents the voltage of the response signal waveform output from the DUT, and the comparator converts the signal into a logic signal using VOH that gives a predetermined threshold level, and outputs the logic signal. FIG. 7B assumes the VOH output level at the time of the ideal characteristic, and FIG. 7C assumes the VOH output level when there is a correction error accompanying the setting data at a position outside the calibration point. From this figure, it can be seen that a timing error (see FIG. 7E) occurs from the ideal characteristic when converted into a logic signal. For example, when there is a correction error of 60 mV in VOH (see FIG. 7D), a timing error (for example, about 20 pS (picosecond)) (see FIG. 7ED) occurs depending on other conditions. This 20 pS timing error is a factor that directly deteriorates the measurement accuracy of the semiconductor test apparatus, and is extremely undesirable. In particular, in a semiconductor test apparatus for testing an ultra-high-speed device, the skew between comparators is required to be, for example, ± 150 picoseconds or less, and the timing error accompanying the VOH setting error cannot be ignored. Although the above is an example of VOH, the same applies to VOL, and similarly, VIH and VIL on the driver side also cause deterioration of skew between drivers.

[0009]

[Problems to be solved by the invention]

 As described above, when the level variable function element shows a non-linear characteristic, the correction data is obtained by calibration, and the correction point is out of the calibration point even when the correction operation is performed by the DAC correction operation device. It is not preferable because a correction error occurs in the setting data area. In this regard, there are practical difficulties in the prior art. Since a semiconductor test device is a measuring device, there is an urgent need to improve the measurement accuracy as much as possible. Therefore, the problem to be solved by the present invention is that a semiconductor test device having a calibration function for correcting a characteristic variation of a variable level functional element provided in a tester pin has a device test for changing a setting condition for the variable level functional element. It is an object of the present invention to provide a semiconductor test apparatus that eliminates a correction error to a variable function element by performing a point calibration under the set condition each time a condition is satisfied.

[0010]

Means for Solving the Problems First, in order to solve the above-mentioned problems, various types of tester pins provided in a semiconductor test apparatus having a variable number of channels (for example, several hundred channels to 1,000 channels or more) with variable device test conditions are used. Each of the level-variable functional elements is provided with a DA converter (referred to as a DAC) at an input portion of the level-variable functional element, and a device test condition for a device under test (referred to as a DUT) is changed. Is performed by changing the value of the DA data 500 s given to the DAC, receives the logical setting data actually applied when performing the test from the device test program, and outputs the ideal output to be output by the level variable function element. The level is referred to as an applied output level SL, and the points of the applied output level SL are subjected to point calibration. When the data to be set in the level variable function element obtained by the point calibration is referred to as point setting data PD, the point setting data PD is obtained from the designated logical setting data to obtain the characteristic of the level variable function element. In a semiconductor test apparatus having a point calibration function capable of correcting variations, during the execution of a device test program, each time a device test is performed, the logic setting data for the above-mentioned variable level functional element is changed immediately before execution of the device test. The point setting data PD is obtained by performing a point calibration on the value of the logical setting data in the above step, and the obtained data is stored and stored in a storage means that can be reused in the next and subsequent times, or The value of the logical setting data is the previous point carry. In the case of the same as the time of the execution of the brazing, the previous point setting data PD is read and reused without performing the point calibration, and the obtained device is used to perform the device test immediately after applying the obtained point setting data PD. This is a semiconductor test device characterized by the following. According to the above invention, in a semiconductor test apparatus having a calibration function for correcting a characteristic variation of a level variable functional element included in a tester pin, each time a device test condition for changing a setting condition for a level variable functional element is changed under the relevant setting condition. By performing the point calibration described above, it is possible to realize a semiconductor test apparatus having a correction method for eliminating a correction error accompanying correction to the variable function element.

Second, in order to solve the above problems, a setting data register 100 for giving logical setting data to a level variable function element, an offset correction register 200 for correcting offset variation of the level variable function element, and a level variable function DAC correction for linearly correcting and calculating the characteristic variation of the level variable function element, comprising a gain correction register 300 for correcting the variation in the gain of the elements, and an arithmetic unit 500 for receiving the three data and performing a predetermined correction operation. In a semiconductor test apparatus provided with an arithmetic unit, first, in the case of practical measurement accuracy where high measurement accuracy is not required, the above-mentioned three data are received and linearly corrected and calculated by the above-mentioned DAC correction arithmetic unit. Secondly, if high measurement accuracy is required, the above level can be used. Each time a device test for changing the logical setting data of the variable function element is performed, the point setting data PD is acquired immediately before the device test, and a means for substantially supplying the point setting data PD to the DAC is provided. The semiconductor test apparatus described above is characterized in that both of the above and a high measurement accuracy can be applied in a predetermined manner.

In addition, the above-described point calibration is performed on the level variable functional element exhibiting the non-linear characteristic in all variable setting sections of the level variable functional element, and the characteristic variation of the level variable functional element is corrected each time. There is the above-described semiconductor test apparatus characterized in that

Further, as one mode of the above-mentioned level variable function element provided with the DAC in the input unit, a function element for changing a high / low voltage level of a waveform applied to the DUT, or a response output from the DUT. A functional element that varies a threshold level voltage of a comparator CP that converts a signal into a logical signal, or a functional element that varies a load current level IL that applies a predetermined constant current load to an output signal from a DUT, or The semiconductor test apparatus described above is characterized in that the semiconductor test apparatus is a functional element that varies a termination voltage VTT applied to a signal output from a DUT via a predetermined termination resistor.

[0014]

[Embodiment of the invention]

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings together with examples. In addition, the description of the following embodiments does not limit the scope of utility model registration, and the elements and connection relationships described in the embodiments are not necessarily essential to the solution. .

In the present invention, focusing on the point that the correction error is zero at the calibration point, the correction error is always calculated by the point calibration method that associates the calibration point, which is the calibration condition, with the device test condition. (B) A semiconductor test apparatus capable of performing a device test is realized. The present invention will be described below with reference to FIG. 1, FIG. 2, and FIG. The components corresponding to the conventional configuration are denoted by the same reference numerals, and the description of the overlapping portions will be omitted.

First, an example of the device test program shown in FIG. 1 will be described. Here, it is assumed that the test is performed by changing the threshold level voltages VOH and VOL given to the comparator CP three times. “Setting of test conditions 1, 2, 3” is a condition setting for other elements except for the level variable function element. The “CALL CALB ()” statement is a utility newly provided in the present application, and is an execution instruction command for performing a level adjustment at a designated point and performing a point calibration. The "MEAS MPAT" statement is an instruction to actually execute a device test. In the present application, the name of the execution function of the point calibration is “CALL CALB ()”, the pin number is specified in the argument data in the statement (see FIGS. 1E and 1K), and the VOH voltage is specified. The following description focuses on three elements: designation (see FIGS. 1F, H, and L) and designation of a VOL voltage (see FIGS. 1G, J, and M).

In the “CALL CALB ()” statement (see FIG. 1A) immediately before the execution of the first device test, the pin numbers are designated from pin 1 to pin 8 (see FIG. 1E), and the VOH voltage Is 1.5 V (see FIG. 1F), and the VOL voltage is 0.5 V (see FIG. 1G). At this time, the point calibration has not been performed for all the VOHs and VOLs that are variable level functional elements, and as a result, there is no existing data in the table memory that is the storage means. Assume that In the first execution of the "CALL CALB ()" statement at the time described above, point calibration is executed for all VOHs and VOLs from pin 1 to pin 8, and each point setting data PD Is obtained. Each of the obtained point setting data PD is stored at a storage address corresponding to the designated voltage, and a storage flag is also set at the corresponding storage address. Then, each point setting data PD is set to the corresponding DAC. The first device test is executed by the “MEAS MPAT” statement immediately thereafter. According to the execution of the first "CALL CALB ()" statement, all VOHs from pins 1 to 8 are accurately set to 1.5V by point calibration, and VOL is accurately set to 0.5V. Is set to As a result, there is obtained an advantage that the difficulty of causing a correction error as in the related art is eliminated.

Here, the point calibration of the present application will be described with reference to FIG. FIG. 2A shows the case where the point calibration is performed on the VOH to 1.5 V, and FIG. 2B shows the case where the point calibration is performed on the VOL to 0.5 V. In this figure, the bare output characteristic without correction is assumed to be a case where both VOH and VOL show a non-linear characteristic curve like a cubic function, as shown in FIG. 2B. First, FIG. 2A will be described. The position where the VOH output level becomes 1.5 V is searched by changing the desired value before and after the set value of 1.50, and the intersection C1 between the naked output characteristic of FIG. 2B and the target horizontal line of the output level of 1.5 V is obtained. Ask for. Here, the setting value for the DAC is obtained as 1.43. The set value 1.43 is the point setting data PD to be given to the DAC corresponding to the VOH logic setting data 1.5V, that is, the DA data 500s. Next, FIG. 2B will be described. The position where the output level of the VOL becomes 0.5 V is searched by changing the desired value before and after the set value of 0.50, and the intersection D1 between the naked output characteristic of FIG. 2B and the horizontal line of the target output level of 0.5 V is searched. Ask for. Here, the set value for the DAC is obtained as 0.46. The set value 0.46 is the point setting data PD to be given to the DAC corresponding to the logical setting data 0.5V of VOL. In the case of the naked output characteristic shown in FIG. 2B, since there are intersections at the other intersections D2 and D3, any intersection may be applied.

Returning to FIG. 1, next, in the “CALL CALB ()” statement (see FIG. 1B) immediately before the execution of the second device test, the pin numbers are the same 1 to 8 pins, and the VOH The voltage is specified to be changed to 2.0 V (see FIG. 1H), and the VOL voltage is specified to be invariable to 0.5 V (see FIG. 1J). In the second execution of the “CALL CALB ()” statement at the time described above, the point calibration may be performed only on the elements that have been changed before. That is, the voltage on the VOH side from pin 1 to pin 8 is 1.5 V to 2. Since the voltage has been changed to 0 V, the point calibration is executed only for this, and each point setting data PD is obtained. Each of the obtained point setting data PD is stored at a storage address corresponding to the specified voltage of 2.0 V, and a storage flag is also set at the corresponding storage address. As for the other VOL-side point setting data PD, there is existing data stored in the table memory at the first time, so the corresponding point setting data PD is read out and reused. Then, each point setting data PD is set to the corresponding DAC. The second device test is executed by the “MEAS MPAT” statement immediately after that. According to the execution of the second "CALL CALB ()" statement, only the VOH side from pins 1 to 8 is actually subjected to the point calibration, resulting in an advantage that the first half of the time is required. Is obtained. Of course, VOH is set exactly to 2.0V and VOL is set exactly to 0.5V.

Next, in the “CALL CALB ()” statement (see FIG. 1C) immediately before the execution of the third device test, the pin number is changed from pin 5 to pin 8 (see FIG. 1K). , VOH voltage is 1.5V change designation (see FIG. 1L), and VOL voltage is 1.0V change designation (see FIG. 1M). In the third execution of the “CALL CALB ()” statement at the time described above, the point calibration may be performed only on the elements that have been changed before. That is, although the VOH side from pin 5 to pin 8 has been changed to 1.5 V, it has already been stored in the table memory at the first time, so there is no need to execute point calibration, and the table memory is simply stored. It is only necessary to read out the corresponding point setting data PD from and reuse it. Since the VOH side is a new voltage value, point calibration is similarly performed only for the new voltage value to obtain the point setting data PD, and store it in the corresponding table memory address. Then, similarly, each point setting data PD is set to the corresponding DAC. The third device test is executed by the “MEAS MPAT” statement immediately thereafter. According to the execution of the third “CALL CALB ()” statement, the point calibration previously executed at the same voltage value even once has been performed by simply reading the corresponding point setting data PD from the table memory. You only need to read them out. This means that in semiconductor test equipment that repeatedly tests a large number of devices of the same product type, point calibration is performed only on the first DUT, and the throughput is reduced accordingly. As a result of the point calibration being executed to zero for the subsequent DUT, there is substantially no decrease in throughput, and the correction error accompanying the correction to the variable function element is eliminated, thereby achieving high measurement accuracy. This provides a great advantage for device testing.

Next, the effect of the point calibration method of the present application will be described with reference to FIG. This figure is the same as the conventional FIG. 7B, and is an example of a case where the response signal (see FIG. 3A) of the DUT is converted into a logic signal by VOH in the comparator CP shown in FIG. As in the conventional case of FIG. 7 (b), the horizontal axis represents time, the vertical axis represents the voltage of the response signal waveform output from the DUT, and the comparator converts the voltage into a logic signal using VOH that gives a predetermined threshold level. 3B is assumed to be the output level of VOH at the time of ideal characteristics, and FIG. 3C is assumed to be the output level of VOH by point calibration according to the method of the present invention. The output level of VOH according to the method of the present invention is calibrated by a method that does not cause a correction error as described above. Therefore, the correction error (see FIG. 3D) is a measurement error of the measurement system used at the time of calibration, for example, a measurement error of 1 mV or less, and can be said to be practically zero error. As a result, as shown in FIG. 7E, the timing error that has been present, for example, about 20 picoseconds is resolved to almost zero. Therefore, especially in a semiconductor test apparatus for testing an ultra-high-speed device, the error of the skew between the comparators related to VOH and VOL is eliminated, and the VIH and VIL on the driver side are similarly set between the drivers related to VIH and VIL. Skew errors are eliminated. As a result, a great advantage that the performance of the semiconductor test apparatus can be further improved can be obtained.

The means for realizing the present invention is not limited to the above-described embodiment, and may be modified and applied. For example, the nonlinear characteristic is measured in advance in all variable setting sections of the level variable functional element, and the point calibration method described above is applied only to the level variable functional element exhibiting the nonlinear characteristic having a predetermined deviation or more. May be applied. For variable level functional elements that change device counts from hundreds to thousands and perform device tests, and that do not require high measurement accuracy, conventional correction calculation methods are used. May be applied.

[0023]

[Effects of the Invention] The present invention has the following effects from the above description. As described above, according to the present invention, an error between the logic setting data and the actual output level is reduced by performing a point calibration in which the value of the logic setting data is directly used as a calibration point. As a result, there is a great advantage that device testing can be performed with high measurement accuracy or timing accuracy. Therefore, the technical effect of the present invention is great.

[Brief description of the drawings]

FIG. 1 is an example of a test program according to the present invention in which a statement of a CALL CALB () function is additionally described.

FIGS. 2A and 2B are diagrams for explaining the operation of the CALL CALB function of FIG. 1 according to the present invention; FIG.
FIG. 9B is an explanatory diagram for obtaining a target set value when performing point adjustment at 5 V. FIG. 10B is an explanatory diagram for obtaining a target set value when performing point adjustment at a VOL setting of 0.5 V.

FIG. 3 is a diagram for explaining the elimination of a timing error in a comparator after level adjustment at a designated point according to the present invention;

FIG. 4 is an example of a configuration of a main part of a conventional DAC correction calculation device that performs linear correction using an offset correction value and a gain correction value.

FIG. 5 is a main system configuration diagram for explaining an example of types and arrangements of level variable functional elements in the semiconductor test apparatus.

FIG. 6 is a diagram for explaining a conventional correction operation, and FIG.
Is the response characteristic of the output level to the set value when there is a linear characteristic variation with respect to offset and gain,
(B) Response characteristics of the output level after correction by the DAC correction calculation device.

7A is a diagram showing a conventional response characteristic of an output level after correction by a DAC correction calculation device when there is a non-linear characteristic variation, and FIG. 7B is a timing error due to a deviation in VOH correction of a comparator CP; FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 setting data register 200 offset correction register 300 gain correction register 500 arithmetic unit 800 DA converter (DAC) 980 functional element CP comparator DR driver DUT device under test

Claims (4)

[Utility model registration claims] 1. A multi-channel tester pin provided in a semiconductor test apparatus is provided with various level variable function elements for varying device test conditions, and a DA converter (DAC) is provided at an input section of the level variable function element. ), And a change in device test conditions for a device under test (called a DUT)
The ideal output level to be output by the level variable functional element by receiving the logical setting data actually applied when performing the test by changing the data value and performing the test is set as the applied output level,
Points for the points of the applied output level
When the calibration is performed and the data to be set to the level variable functional element obtained by the point calibration is set as the point setting data, the characteristic setting data is obtained using the designated logical setting data to determine the characteristic variation of the level variable functional element. In a semiconductor test apparatus having a point calibration function for correcting the logic setting data, during execution of a device test program, each time a device test for changing logic setting data for the variable level functional element is performed, the logic setting data is The point setting data is obtained by performing a point calibration for the value of, or when the value of the logical setting data is the same as that at the time of the previous point calibration, the point calibration is not performed and the previous point calibration is not performed. Point setting data The reused, a semiconductor test apparatus which comprises carrying out the device testing immediately after applying said point setting data obtained. A setting data register for providing logic setting data to the variable level function element, an offset correction register for correcting offset variation of the variable level function element, a gain correction register for correcting gain variation of the variable level function element, A semiconductor test apparatus comprising: an arithmetic unit that receives the above three data to perform a predetermined correction operation; and a DAC correction operation unit that linearly corrects the characteristic variation of the level variable function element and performs a correction operation. If the request is not required, the three data are received by the DAC correction operation device to perform a linear correction operation to correct the characteristic variation of the level variable functional element. If the second high measurement accuracy is required, 2. The device according to claim 1, wherein each time a device test for changing the logic setting data of the level variable function element is performed, immediately before the device test is performed. Acquires Into setting data, the semiconductor test apparatus according to claim 1, characterized in that it comprises means for supplying substantially the DAC said point setting data. 3. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is applied to a level variable functional element exhibiting a non-linear characteristic in all variable setting sections of the level variable functional element. 4. The level variable function element having a DAC in an input section, the function element changing a voltage level of a waveform applied to the DUT, or a threshold value of a comparator CP converting a response signal output from the DUT into a logic signal. .Functional elements that make the level voltage variable or DU
A function element for varying a load current level IL for applying a predetermined constant current load to the output signal from T, or DU
2. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is a functional element that varies a termination voltage VTT applied to an output signal from T via a predetermined termination resistor.