JP3053009B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a fine MOS type semiconductor device for realizing a highly integrated semiconductor circuit.

[0002]

2. Description of the Related Art In order to improve the performance of a semiconductor circuit, it is necessary to increase the degree of integration of a semiconductor element. Therefore, the element area must be reduced. The element region of a transistor is determined by an element isolation region made of an oxide film. The isolation region is formed up to about 0.35 μm by a LOCOS (LOCal Oxidation of LOCOS) method using a thermal oxidation method.
Silicon) or an improved LOCOS method.

However, in the method using the thermal oxidation method, during oxidation, a portion below the silicon nitride film which defines the element region is oxidized, resulting in a bird's beak, which hinders miniaturization of the element isolation region. . Therefore, 0.35μ
Shallow trench isolation (Shallow Trench Isolation) technology has become mainstream for micro devices with m-rule and subsequent rules. The method of forming the shallow trench is shown in FIG.
This will be described with reference to (a) to (i).

FIG. 2A shows a state in which a pad silicon oxide film 2 is formed on a semiconductor substrate 1 by a thermal oxidation method, and a silicon nitride film 3 is further deposited by a plasma chemical vapor deposition (CVD) method. It is a model explanatory view. The thickness of the silicon oxide film 2 is 10 to
The thickness of the silicon nitride film 3 is set to about 15 to 200 nm.

The film thickness of the silicon nitride 3 is determined by chemical mechanical polishing (CMP) performed later.
The thickness is set to a thickness that can be used as a stopper film for polishing in the method g). Next, the resist 4 is patterned by photolithography, and the silicon nitride film and the silicon oxide film in a region to be an element isolation region are etched using the photoresist as a mask (see FIG. 2B).

Further, a trench groove 5 is formed by etching the silicon substrate in a region to be an element isolation region.
(See (c)). The depth of the trench 5 is 300 to
Etching is performed so as to have a thickness of 400 nm and an inclination angle of 75 to 80 °. Next, after the photoresist 4 is peeled off, oxidation of the inner wall of the trench 5 is performed to about 10 nm in order to round the corner of the trench 5. Then, CV
A silicon oxide film 6 having a thickness of 500 to 700 nm is deposited by the method D to bury the inside of the trench (see FIG. 2D, not shown in the figure because the oxide film on the inner wall is thin).

Next, the surface is flattened by the CMP method until the silicon nitride film 3 serving as a stopper appears (see FIG. 2E). Thereafter, the silicon nitride film 3 serving as a stopper is etched with a phosphoric acid-based etchant, and the pad oxide film 2 is removed with a hydrofluoric acid-based etchant to form an isolation region (see FIG. 2F).

Thereafter, impurities for the well and channel regions are introduced by an ion implantation method, and a gate oxide film 9 is formed by a thermal oxidation method (see FIG. 2 (h)).
The formation of the polysilicon film serving as the gate electrode by the CVD method is the same as the step of forming a normal MOS transistor.

[0009]

However, in such a process, pillars 53 (see FIG. 2F) are generated by an amount corresponding to the thickness of the silicon nitride film which is a stopper film during the CMP. Furthermore, the silicon oxide film 2 of the pad is a thermal oxide film, while the pillar is formed by CV.
Since the silicon oxide film is formed by the method D, the latter oxide film has a higher etching rate with respect to a hydrofluoric acid-based etchant. Therefore, the film is reduced at the edge of the trench isolation, and the depression 54 (see FIG. 2G) is generated.

The recess 54 is liable to cause an electric field concentration. If a gate structure is formed on the shoulder by the formation of a gate oxide film 9 and polysilicon 8 serving as a gate electrode in a later step, the shoulder 54 The portion becomes a region 91 (see FIG. 2H) in which a side channel is likely to occur, which causes a problem that the off-leak current of the transistor is increased.

Further, when performing gate lithography due to the absolute step of the pillar portion, a constriction of the resist occurs, and the processing accuracy of the gate is deteriorated, which may cause a serious problem.

On the other hand, complete flattening is necessary to eliminate the problem of dents during etching of the pad oxide film and the problem of steps due to pillars. For this purpose, dry planarization is performed by plasma etching. Although etching is effective, in this method, the channel region of the transistor is exposed to plasma, and the damaged region 9 is exposed.
3 (see FIG. 2 (i)), which results in a problem that the transistor characteristics are degraded.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can realize complete planarization without damaging a channel region of a transistor in a shallow trench process without the above problems. Things.

[0014]

The above objects and objects are solved and achieved by the present invention described below. That is, the present invention provides a method of manufacturing a MOS type semiconductor device, wherein a step of forming first and second insulating films on a surface of a semiconductor substrate, a step of forming a trench reaching the semiconductor substrate,
Embedding a third insulating film in the trench;
Flattening the surface of the third green film by a mechanical polishing method until the insulating film appears on the surface;
And a step of stripping the first insulating film, a step of nitriding the entire substrate, and a step of covering the substrate surface with the fourth insulating film to form a trench.
, A step of etching back and planarizing until a substrate nitrided by plasma etching appears, and a step of peeling off a nitrided region on the substrate surface.
A method for manufacturing a semiconductor device characterized by the above is disclosed.

In the method of manufacturing a semiconductor device according to the present invention, the material of the first, third and fourth insulating films is silicon oxide, and the material of the second insulating film is Wherein the first insulating film is peeled off by using a wet etching solution mainly composed of hydrofluoric acid. It is characterized in that it is carried out in a cord, ammonia, NO or N ₂ O atmosphere.

In order to prevent the channel region of the transistor from being damaged by plasma against etch back for flattening the oxide film, the surface is protected by nitriding. Therefore, the element isolation region can be flattened without damaging the transistor region, so that stable transistor characteristics without variation in threshold voltage can be obtained while increasing the degree of integration.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be specifically described below.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the drawings (FIGS. 1A to 1K). FIG.
1A is a schematic explanatory view showing a state in which a pad silicon oxide film 2 and a silicon nitride film 3 serving as a CMP stopper film are formed on a semiconductor substrate 1. FIG.

The pad silicon oxide film 2 is deposited to a thickness of 10 to 20 nm by a thermal oxidation method, and the silicon nitride film 3 is deposited to a thickness of 150 to 200 nm by a CVD method. Next, a resist is applied to the entire surface of the substrate, and is patterned by photolithography so as to leave the resist 4 in a region other than a region to be an element isolation region (see FIG. 1B).

Thereafter, the silicon nitride film 3 and the pad silicon oxide film 2 are etched by anisotropic etching using the resist 4 as a mask, and a trench 5 is formed in the silicon substrate by etching (FIG. 1).
(See (c)).

The trench 5 has an inclination angle of 70 to 8
Make it 5%. After that, the resist 4 is removed, the inner wall is oxidized by thermal oxidation, and then a silicon oxide film 6 is deposited to a thickness of 500 to 700 nm by a CVD method.
A silicon oxide film is buried inside the trench (FIG. 1
(See (d), the figure does not show the oxide film on the inner wall).

After the silicon oxide film 6 is embedded, the silicon oxide film is planarized by polishing until the silicon nitride film serving as a stopper appears by CMP (see FIG. 1E). Then, the silicon nitride film 3 serving as a stopper is peeled off with a phosphoric acid-based etchant (see FIG. 1F).

At this time, pillars 53 corresponding to the thickness of the silicon nitride are formed. Further, the silicon oxide film 2 of the pad is etched with a hydrofluoric acid-based etchant. The etching of the bad oxide film 2 simultaneously etches the upper portion of the CVD silicon oxide film 6 buried in the trench 5.
Since the etching rate for the CVD silicon oxide film is higher than that for the pad silicon oxide film which is a thermal oxide film, the shape of the isolation region is a shape as shown in FIG. become.

Next, the entire surface of the substrate is nitrided in this state. The conditions for the entire surface nitriding are as follows. For example, by performing a heat treatment at 900 ° C. for 30 seconds in a nitrogen atmosphere, a silicon nitride film 12 of 4 to 5 nm is formed only in a region where a transistor is to be formed (FIG. 1H). See). Note that the nitrided region 12 is not formed on the silicon oxide film. Next, a CVD silicon oxide film 62 is further deposited on the entire surface of the substrate to fill the depressions 54 generated by the hydrofluoric acid etching. The thickness of the CVD oxide film 62 may be about 20 to 40 nm because the recess 54 itself may be filled.
(See (i)).

Thereafter, the entire substrate is etched back to completely flatten the substrate surface (see FIG. 1 (j)). At this time, since an element region in which a transistor can be formed is covered with the silicon nitride film, no plasma damage occurs at this time. After that, the silicon nitride film is separated with a phosphoric acid-based etchant. Since the thickness of the nitrided region is 4 to 5 nm, it hardly affects the overall planarization. Therefore, complete planarization of the element isolation region is completed (FIG. 1 (k)).
refer.

The subsequent steps are the same as the steps after the formation of the element isolation region in the usual transistor manufacturing process. When the silicon nitride film for protecting the transistor region is peeled off, a gap is formed between the trench region corresponding to the depression and the transistor region.
There is no problem because it is buried by oxidation when a through oxide film is formed before ion implantation in a usual post-process.

The above is an n-type MOSFET (Field Effect T)
ransistor) manufacturing process,
The same effect can be obtained for p-type MOSFETs by changing the conductivity type of the above impurities.

[0028]

According to the present invention, there is provided an excellent method of manufacturing a semiconductor device which enables complete flattening of trench isolation without complicating the manufacturing process and without adversely affecting a transistor such as plasma damage.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory view showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic explanatory view showing a method for manufacturing a semiconductor device according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 pad silicon oxide film 3 silicon nitride film 4 resist 5 trench groove 6 CVD silicon oxide film 8 gate polysilicon 9 gate oxide film 12 nitrided region 53 pillar 54 trench depression 62 CVD silicon oxide region 91 side channel Probable area 93 Plasma damage area

Claims (5)

(57) [Claims] In a method of manufacturing a MOS type semiconductor device, a step of forming first and second insulating films on a surface of a semiconductor substrate, a step of forming a trench (trench) reaching the semiconductor substrate, and a step of forming a trench in the trench . A step of embedding the third insulating film, a step of flattening the surface of the third green insulating film by mechanical polishing until the second insulating film appears on the surface, and the second and first insulating films after the flattening. Stripping, nitriding the entire substrate, and covering the substrate surface with a fourth insulating film .
Fill depressions wrench step, a step of planarizing is etched back until the substrate is nitrided appears by plasma etching, the semiconductor device characterized by comprising the step, each step of peeling the nitrided region of the substrate surface Production method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the material of said first, third and fourth insulating films is silicon oxide. 3. The method according to claim 1, wherein a material of the second insulating film is silicon nitride. 4. The method for manufacturing a semiconductor device according to claim 1, wherein said first insulating film is peeled off using a wet etching solution mainly composed of hydrofluoric acid. 5. The method according to claim 1, wherein the nitriding of the substrate surface is performed in an atmosphere of nitriding, ammonia, NO or N ₂ O.