JP3052334B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing device, and more particularly, to a data processing device that performs data processing for suppressing a DC component.

[Prior Art] In recent years, a system for digitally recording an audio signal, a video signal, and the like on a recording medium has been proposed. However, it is difficult to record and reproduce a very low frequency and a DC component on a magnetic recording medium. A recording modulation method that derives a code string that does not include a DC component, such as -10 block coding, is used. In addition, as a recording modulation method for suppressing the DC component and the low frequency component of the code string, for a combination of a plurality of highly correlated digital data, the DC and DC of the same number of bits as the sum of the number of bits of the plurality of data are used. An encoding method has been proposed in which recording is performed with a small DC component without increasing redundancy by assigning a digital code having a small low frequency component. Hereinafter, a coding method that suppresses a DC component and a low-frequency component using a correlation between input data is referred to as a DC suppression coding method.

[Problems to be Solved by the Invention] When recording images (still images and moving images) on a recording medium, unique additional information (for example, ID information) is added to each image. Such additional information has no or low correlation between data, and is coded using the above-described DC suppression coding method. Therefore, there is a high possibility that a code having a high DC component is assigned, making recording and reproduction difficult. May occur.

Therefore, an object of the present invention is to provide a data processing device that solves such a problem.

[Means for Solving the Problems] A data processing apparatus according to the present invention further comprises an input means for inputting information data composed of a plurality of bits in parallel, and a conversion of the parallel information data input by the input means into serial data. Converting means, adding means for adding predetermined bit data to the serial data converted by the converting means in a predetermined bit unit, predetermined bit data added by the adding means and information data of the predetermined bit subsequent thereto And a conversion means for performing a conversion process so that the data sequence becomes a data sequence in which the DC component is suppressed.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an encoding apparatus to which the present invention is applied. 10 is an input terminal for m-bit uncorrelated data D, and 12 is a p-bit stuff
An input terminal 14 for data S is an input terminal for n-bit correlation data Q having a correlation between data. Reference numeral 16 denotes a block correlation generation circuit for converting m-bit uncorrelated data D into data having n-bit correlation, reference numeral 18 denotes a (n-p) -bit blocking circuit, and reference numeral 20 denotes a higher order output of the blocking circuit 18. Is a high-order bit adding circuit for adding the stuff data S of the input terminal 12 to the input terminal 12. Reference numerals 22 and 24 denote time delay circuits, reference numeral 26 denotes a switch as a multiplexing circuit, reference numeral 28 denotes a DC suppression coding circuit, reference numeral 30 denotes an output terminal, and reference numeral 32 denotes a timing control circuit for controlling the switch 26.

The operation of FIG. 1 will be described. The blocking circuit 18 blocks the uncorrelated data D at the input terminal 10 for every (n-p) bits, and the high-order bit adding circuit 20 inputs the upper bits of the (n-p) -bit data from the blocking circuit 18. The p-bit stuff data S at the terminal 12 is added. The output of the upper bit addition circuit 20, that is, the output of the block correlation generation circuit 16, is n-bit block data D ^(m) having a correlation between data.

The output of the block correlation generating circuit 16 and the input data Q of the input terminal 14 are time-adjusted by delay circuits 22 and 24, respectively, and applied to the a and b contacts of the switch 26. The switch 24 is switched by a timing signal from the timing control circuit 32, and for example, the data is transmitted in the order shown in FIG.
D ^(m) and Q are input to the DC suppression coding circuit 28.

The n-bit data input to the DC suppression coding circuit 28 has a correlation between the data, and the DC suppression coding circuit 28
Is 8-bit for a combination of multiple n-bit data.
The N-bit data D ^(m) and Q multiplexed by the switch 26 are coded by a coding method such as 8-word invert coding in which the DC and low frequency components are suppressed, and the DC and low frequency components are coded. Output terminal 30
Output to As the DC suppression coding circuit 28, for example, a coding circuit described in JP-A-63-33086, that is, a 2n bit composed of a combination of two n-bit data is converted into a signal having a low DC component and a low frequency component. It is possible to use a moping encoder that converts the data into 2n-bit data.

Next, a method for determining the staff data S will be described with reference to FIG. FIG. 2 shows an example of the processing flow and processing contents of the block correlation generation circuit 16. In this example, m = 1
2, n = 4 and p = 1. Also, staff data S
= 0. The blocking circuit 18 calculates the uncorrelated data D
Is divided into four blocks of 3 (= n−p) bits, and the upper bit addition circuit 20 adds stuff data S (= 0) to the upper bits of each block of 3 bits to form a 4-bit block. Output data D ^(m) . Data D ^(m) the upper bits are common to S, compared with the case of blocking the uncorrelated data D of 12 bits as a 4-bit, resin of possible data becomes 1/2 ^p. That is, 4-bit random data is limited to a 3-bit range, and there is a correlation between data.

FIG. 4 shows a specific circuit configuration example of the block correlation generating circuit 16. 40 is an input terminal for uncorrelated data D, 42 is an input terminal for stuff data S, 44 and 46 are parallel / serial (P / S) converters, 48 and 50 are buffer memories, and 52 is a buffer memory 48 and Reference numeral 50 denotes a switch for multiplexing output data, 54 denotes a serial / parallel (S / P) converter, 56 denotes an output terminal, and 58 denotes a timing control circuit for controlling the switch 52.

The uncorrelated data D input to the input terminal 40 is converted to a P / S converter 44.
, The data is converted into a serial bit string in order from the MSB (most significant bit), and the buffer memory 48 buffers the data so that p bits become available every (np) bits from the head of the bit string. This is equivalent to performing a blocking process on the serial data string. The P / S converter 46 converts the stuff data S input to the input terminal 42 into a serial data string, and the buffer memory 50 performs buffering for multiplexing at the switch 52.

Under the control of the timing control circuit 58, the switch 52 controls the buffer memory 50 during the vacant period of the first p bits of the bit string from the buffer memory 48 and the vacant period of p bits every other (n-p) bits thereafter. Insert p bits from. The S / P converter 54 converts the bit string multiplexed by the switch 52 into a parallel signal, and outputs a D signal via an output terminal 56.
Output as ^(m) .

In FIG. 4, when p = 1, the P / S converter 46 and the buffer memory 50 can be omitted.

FIG. 5 shows another circuit configuration example of the block correlation generation circuit 16. Here, it is assumed that n−p = m / 2. 60 is m
The input terminal of the bit uncorrelated data D, the input terminal of the p-bit stuff data S, and the lower (np) bit of the m-bit uncorrelated data D input to the input terminal 60 This is a latch circuit that is input to the lower side and the staff data S of the input terminal 62 is input to the upper side. Reference numeral 66 denotes a selection switch, and n-bit data in which the upper (n-p) bit of the uncorrelated data D is arranged on the lower side and the stuff data S is arranged on the upper side is input to the contact a. The n-bit data output from the latch circuit 64 is input to the contact. 68 is a timing control circuit that controls the switch 66,
70 is an output terminal.

This circuit is suitable when m is small and constant.
For example, in the case where m = 6, p = 1, and n = 4, for example, the one-bit stuff data S of the input terminal 62 is added to the upper three bits of the uncorrelated data D input to the input terminal 60. Are supplied to the contact a of the switch 66. Also, 1-bit stuff data S of the input terminal 62 is added to the lower 3 bits of the uncorrelated data D.
The bit is supplied to the latch circuit 64. The switch 66 is alternately connected to the contacts a and b at a cycle twice as long as the input cycle of the uncorrelated data D, and the latch circuit 64 holds the input until the switch 66 is connected to the contact b. As described above, 4-bit data D ^(m) having correlation is obtained from the output terminal 70.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, DC and low-frequency components with little DC and low-frequency components are obtained by DC and low-frequency suppression coding using data correlation even for data including uncorrelated data. The sign can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the processing contents in a block correlation generating circuit 16, FIG. 3 is a multiplexing format by a switch 52, and FIG. FIG. 5 is another circuit example of the block correlation generation circuit 16. 10, 12, 14, 40, 42, 60, 62: input terminal, 16: block correlation generation circuit, 18: blocking circuit, 20: upper bit addition circuit, 2
8: DC suppression coding circuit, 30, 56, 70: output terminal, 44, 46: parallel / serial converter, 48, 50: buffer memory, 5
4: Serial / parallel converter, 64: Latch circuit

Continuation of the front page (56) References JP-A-63-302627 (JP, A) JP-A-60-199257 (JP, A) JP-A-60-199258 (JP, A) JP-A-63-33086 (JP) JP-A-1-228333 (JP, A) JP-A-57-48848 (JP, A) JP-A-59-57549 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB (Name) H03M 7/14

Claims (1)

(57) [Claims] An input means for inputting information data consisting of a plurality of bits in parallel; a conversion means for converting parallel information data input by the input means into serial data; a conversion by the conversion means in predetermined bit units. Adding means for adding predetermined bit data to the serial data thus obtained, and converting the predetermined bit data added by the adding means and the information data of the predetermined bits subsequent thereto into a data string in which a DC component is suppressed. A data processing device, comprising: a processing unit that performs a conversion process on the data.