JP3048608B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a content addressable memory (Content Addr) having a bit collating function.
essable memory) (hereinafter, referred to as a CAM cell).

[Conventional technology]

Figure 3 shows the IEE Journal of
Solid State Circuit sc-7 page 366 (IEEE
Journal of Solid-State Cjrcit, vol.sc-7 pp.366)
1 is a circuit diagram of a conventional CAM cell disclosed in US Pat. No. 3,701,980.

As shown in FIG. 3, the CAM cell includes five n-channel MOS transistors 1 to 5. Transistor 1
Is connected between the bit line 6 and the storage node 20, the transistor 2 is connected between the inverted bit line 7 and the inverted storage node 21, and the respective gates of these transistors 1 and 2 are both connected to the word line 8. It is connected. The transistor 3 is connected between the bit line 6 and the control terminal 9, and the transistor 4 is connected between the inverted bit line 7 and the control terminal 9. The gate of transistor 3 is connected to storage node 20, and the gate of transistor 4 is connected to inverted storage node 21. The transistor 5 is connected between the match line 10 and the control terminal 9, and the gate of the transistor 5 is also connected to the match line 10.

Next, the write operation, match search operation, read operation and refresh operation of the CAM cell of FIG. 3 will be described in order. In the following description, “H” indicates the power supply potential Vcc or a potential in the vicinity thereof, and “L” indicates the ground potential Vs
Indicates the potential at or near s. However, Vcc> Vss. Also, that the data of the bit line pair 6, 7 is "0",
When the potential of the bit line 6 is “L” and the potential of the inverted bit line 7 is “H”, and the data of the bit line bodies 6 and 7 are “1”, the potential of the bit line 6 is This is equivalent to “H” and the potential of the inversion bit line 7 being “L”.

(Write Operation) In the write operation, the potential of the word line 8 is set to “H”,
Data to be written is supplied to the bit line pair 6, 7, and after a certain time, the potential of the word line 8 is set to "L".

For example, the data to be written is "1", that is, "H" is applied to bit line 6 and "L" is applied to inverted bit line 7. In this case, the potential “H” of the bit line 6 is supplied to the gate capacitance of the transistor 3 via the transistor 1 which is turned on in response to the gate input of “H” from the word line 8. Similarly, the potential “L” of the inversion bit line 7 is applied to the gate capacitance of the transistor 4 via the transistor 2 which is turned on in response to the “H” gate input from the word line 8. After a certain period of time, transistors 1 and 2 are turned off in response to a gate input of "L" from word line 8.

As a result of the above operation, the gate potential of the transistor 3, that is, the potential of the storage node 20 is kept at Vcc-Vth, and the gate potential of the transistor 4, that is, the potential of the inversion storage node 21, becomes
Kept at Vss. Note that Vth is a threshold voltage of the transistors 1 to 5.

(Match Search Operation) In the match search operation, after the match line 10 is precharged to “H” to be in a floating state, search data is supplied to the bit line pair 6 and 7. If the stored data and the search data do not match, the match line 10 is discharged to "L". On the other hand, when the stored data matches the search data, the match line 10 is maintained at "H" without being discharged.

For example, it is assumed that the storage data is “1”, that is, “H” is stored in the gate capacitance of transistor 3 and “L” is stored in the gate capacitance of transistor 4. In this case, the transistor 3 is turned on and the transistor 4 is turned off. When "1" is given as the search data and the potential of the bit line 6 becomes "H" and the potential of the inverted bit line 7 becomes "L", the potential of the control terminal 9 becomes "H". Therefore, the match line 10 is maintained at "H" without being discharged (match).

On the other hand, when the stored data is similarly “1”, it is assumed that “0” is given as the search data, the potential of the bit line 6 becomes “L”, and the potential of the inverted bit line 7 becomes “H”. In this case, since the transistor 3 is on and the transistor 4 is off, the potential of the control terminal 9 is “L”.
Becomes Therefore, the discharge is performed via a discharge path including the transistors 5 and 3 of the match line 10 and the bit line 6 (mismatch).

Similarly, when the stored data is “0”, if the search data is “1”, the potential of the control terminal 9 becomes “L”. Therefore, the match line 10 is connected to the transistors 5 and 4 and the inverted bit line 7.
(Disagreement) through a discharge path consisting of If the search data is “0”, the potential of the control terminal 9 becomes “H”. Therefore, the match line 10 is maintained at "H" without being discharged (match).

When "H" is applied to both the bit line 6 and the inverted bit line 7, the potential of the control terminal 9 becomes "H" regardless of the value of the stored data. This state means that no match search operation is performed on the bit line, that is, a masked state.

As described above, in the match search operation, the match line 10 is discharged when the storage data and the search data do not match, while the match line is not discharged when they match or when the match data is masked. Is kept.

(Read Operation) In the read operation, the match line 10, the bit line 6 and the inverted bit line 7 are discharged to "L", and after the bit line 6 and the inverted bit line 7 are brought into a floating state, the potential of the match line 10 is set. Is set to “H”.

For example, it is assumed that the stored data is “1”. In this case, the transistor 3 is turned on.
Is set to "H", the potential of the bit line 6 rises through the transistors 5 and 3, whereby the stored data "1" is read.

Conversely, it is assumed that the stored data is “0”. In this case, since the transistor 4 is in the ON state, the potential of the inverted bit line 7 rises through the transistors 5 and 4 in which the potential of the match line 10 is set to "H", whereby the stored data "0" is read. .

(Refresh Operation) The above CAM cell is of a dynamic type, and stored data is stored as charges in the gate capacitances of the transistors 3 and 4. Therefore, the stored data may be destroyed due to the leakage of the charge. Therefore, it is necessary to perform the refresh operation every predetermined time.

In the refresh operation, after the above-described read operation, the data read to the bit line 6 and the inverted bit line 7 are amplified, and subsequently the above-described write operation is performed.

That is, after the match line 10, the bit line 6 and the inverted bit line 7 are discharged to "L" and the bit line 6 and the inverted bit line 7 are set to the "L" floating state, the potential of the match line 10 becomes "H". Is made. Thereby, stored data is read out to bit line 6 and inverted bit line 7. Subsequently, the read data is amplified. By setting the potential of the word line 8 to "H", the transistor 3,
The amplified data is written to the gate capacitance of No. 4, and after a certain time, the potential of the word line 8 is set to "L".

By the plurality of CAM cells performing the above operations, the fourth
Words are configured as shown in the figure. Here, the word means a block including a plurality of CAM cells connected to a common word line and a common match line.

FIG. 4 shows a word consisting of four CAM cells. 4th
In the figure, four bit lines 6a to 6d, four inverted bit lines 7a to 7d, a word line 8, a match line 10, and four CAM cells 11a to
11d, a word line driver 12, a match line driver 13, and a match line sense amplifier 14 are provided.

The above-described write operation, read operation and refresh operation are all performed in word units. In addition, the above-described match search operation is performed in units of a plurality of words or in an array described later, but determination of match or mismatch is performed in units of words. That is, in each of the above operations, the word line driver
12 drives the word line 8 to “H” and “L”.
Is controlled and the match line driver 13
The drive to "H" and the drive to "L" and the floating state of 10 are controlled. The match line sense amplifier 14 detects a match search operation, particularly the voltage output to the match line 10, and performs a match / mismatch determination operation.

Next, the features of the match search operation, the refresh operation, and the partial write operation in units of word lines will be described. Each CA
The operation inside the M cell is the same as each operation of the corresponding CAM cell already described.

(Match Search Operation) The above-described match search operation is performed simultaneously in the four CAM cells 11a to 11d in the word. As a result of the match search operation, the CAM cell indicating "match" or the masked CAM cell does not discharge the match line 10, but
The CAM cell indicating "mismatch" discharges the match line 10.

Therefore, if even one of the four CAM cells in a word indicates "mismatch", the match line 10 corresponding to that word
Is discharged. Therefore, when the potential of the match line 10 is detected by the match line sense amplifier 14, "mismatch" in that word is detected.

Conversely, when all the unmasked CAM cells among the four CAM cells indicate "match", the potential of the match line 10 corresponding to the word remains "H". When the potential of the match line 10 is detected by the match line sense amplifier 14, "match" in the word line is detected.

(Refresh Operation) In the four CAM cells 11a to 11d in a word, the above-described refresh operation is performed simultaneously. That is, the match line 10 and the bit lines 6a to 6d common to the four CAM cells 11a to 11d
After the inversion bit lines 7a to 7d are discharged to "L" and the bit lines 6a to 6d and the inversion bit lines 7a to 7d are set to the floating state, the potential of the match line 10 is set to "H". Thereby, the bit lines 6a to 6d and the inverted bit line
The stored data in the CAM cells 11a to 11d are read out to 7a to 7d, respectively. Subsequently, the read data is amplified. The potential of the word line 8 common to the four CAM cells is "H"
, The amplified data is written to the four CAM cells 11a to 11d. After a certain time, the potential of the word line 8 is set to “L”, whereby the refresh operation in word line units is completed.

(Partial Write Operation) A partial write operation is a process in which new data is written to arbitrarily designated CAM cells of all CAM cells in a word, and the remaining CAM cells hold previous storage data. This is a continuous operation.

Here, CAM cells 11a and 11c of the four CAM cells
Only new data shall be written. First, 4
Match line 10, bit lines 6a-6 common to the CAM cells 11a-11d
d and the inverted lines 7a to 7d are discharged to "L", and the bit lines 6a to 6d and the inverted bit lines 7a to 7d are set to the "L" floating state. Is made. Thereby, each CAM cell 1
The stored data of 1a to 11d is read to bit lines 6a to 6d and inverted bit lines 7a to 7d, and subsequently, the read data is amplified.

Next, data to be written is applied to bit lines 6a and 6c and inverted bit lines 7a and 7c. In this state, the bit lines 6a, 6
c and inverted bit lines 7a and 7c are given new data to be written to the CAM cells 11a and 11c, and the bit lines 6b and 6d and the inverted bit lines 7b and 7d are stored by the CAM cells 11b and 11d. That data is amplified and given. next,
When the potential of the word line 8 common to the four CAM cells is set to “H”, data applied to the corresponding bit line and the inverted bit line is written to each of the four CAM cells. After a certain time, when the potential of word line 8 is set to "L", the partial write operation is completed.

By the above operation, the CAM cell 11 is
New data is written to a and 11c, and the stored data is refreshed in the CAM cells 11b and 11d.

[Problems to be solved by the invention]

In an actual CAM, as shown in FIG. 5, a plurality of words are arranged side by side to form an array. In FIG.
Four words 15A to 15D constitute one array.
Word 15A is composed of four CAM cells 11a to 11d, word line 8, match line 10, word line driver 12, match line driver 13, and match line sense amplifier 14, and word 15B, word 1
5C and word 15D are similarly configured.

The above-described match search operation is performed simultaneously in the entire array, and the above-described write operation, read operation, refresh operation, and partial write operation are usually performed sequentially word by word. However, depending on the application of the system, It is often more efficient to perform a write operation and a partial write operation on a plurality of words simultaneously.

In the array of FIG. 5, simultaneous writing to a plurality of words can be performed by setting all desired word lines to "H" in the above-described writing operation, but simultaneous partial writing to a plurality of words can be performed by simultaneously writing CAM cell data. In the read stage, it cannot be executed because the data of a plurality of words collide on the bit line and the inverted bit line.

Fig. 6 shows the IEE journal
Of Solid State Circuit sc24, p.107 (IEEE Journal of Solid-State Circuit, vol.sc-24,
This is a conventional CAM cell capable of simultaneous partial writing to a plurality of words disclosed in p. 1017).

As shown in FIG. 6, this CAM cell has nine n-channel MOS transistors 1-4, 32-36, and two resistors 30,
Consists of 31. The transistors 32 and 33 and the resistors 30 and 31 form a flip-flop. The storage node 20 and the inverted storage node 21 of the flip-flop are connected to the bit line 6 and the inverted bit line 7 via transistors 1, 35 and 2, 36 connected in series, respectively. 8, the gates of the transistors 35 and 36 are respectively connected to a partial write control line 37 paired with a bit line and an inverted bit line. Transistor 3
Is connected between the inverted search data line 41 and the control terminal 9, the transistor 4 is connected between the search data line 40 and the control terminal 9, the gate of the transistor 3 is connected to the storage node 20, and the gate of the transistor 4 is connected to the inverted storage. Each is connected to the node 21. Transistor 34 is connected between match line 10 and ground, and its gate is connected to control terminal 9.

Next, when the CAM cells of FIG. 6 constitute an array as shown in FIG.
The match search operation and the read operation will be described in order. The sixth
Since the CAM cell in the figure is constituted by a static flip-flop, a refresh operation is not required.

(Write and Partial Write Operation) In the write operation, write data is supplied to the bit line 6 and the inverted bit line 7, and the word line 8, the partial write control line 37
Is set to “H” to set the storage node to a state that matches the write data, and then the word line is set to “L”. The partial write is executed by setting the partial write control line 37 corresponding to the bit whose write is to be inhibited at the time of performing the above-described write operation to “L”. In the CAM cell of FIG.
Since it is not necessary to read data once at the time of partial writing, simultaneous writing and simultaneous partial writing to a plurality of words are performed by setting all desired word lines to “H” in the above operation.
Is possible.

(Match Search Operation) In the match search operation, the search data is given to the search data line 40 and the inverted search data line 41 after the match line 10 is pre-sharded to “H” to be in the floating state. If the stored data and the search data do not match, the control terminal 9 goes "H", the transistor 34 is turned on, and the match line 10 is discharged. On the other hand, when the stored data and the search data match, the control terminal 9 is set to "L", the transistor 34 is turned off, and the match line 10 maintains "H". When both the search data line 40 and the inverted search data line 41 are set to "L", the control terminal 9 is set to "L" and the match line 10 is maintained at "H" regardless of the stored data. It is possible.

(Read Operation) The read operation is performed by the word line 8 and the partial write control line 37.
Is set to "H", and the stored data is output to the bit line 6 and the inverted bit line 7, and is amplified.

As described above, the CAM cell of FIG. 6 allows simultaneous partial writing to a plurality of words, but the CAM cell of FIG. 6 has a larger number of constituent elements than the CAM cell of FIG. There is a problem that it is difficult.

On the other hand, FIG. 7 shows the CAM cell of FIG.
Similar to the AM cell, this is a CAM cell in which a transistor controlled by a partial write control line is connected in series with a transistor controlled by a word line.

In FIG. 7, transistors 35 and 36 are controlled by a partial write line 37 and are connected in series with transistors 1 and 2, respectively, controlled by a word line. The other parts are the same as the CAM cell of FIG. With this configuration, simultaneous partial writing to a plurality of words is possible as in the case of the CAM cell in FIG. 6, but data is destroyed by the timing of the word line and the partial writing control line as described below. The problem arises.

FIG. 8 is an equivalent circuit focusing on a part of the CAM cell of FIG. 7, in which 24 is the storage capacitance of the storage node 20, and 25 is the node 22.
Stray capacitance. Hereinafter, the problem of data destruction will be described with reference to the equivalent circuit of FIG. 8 and the timing chart of FIG.

In FIG. 9, the word line 8, the partial write control line 37,
After the bit line 6 is set to "H" to turn on the transistors 1 and 35, the word line 8 is set to "L" at time t0 to turn off the transistor 1. At this time, "H" is written to the storage node 20, and the potential is set to VH0. Next, when the bit line 6 becomes "L" at time t1, the node 22 is discharged via the transistor 35, and the potential becomes zero. At time t2, the partial write control line
After the transistor 37 is turned off and the transistor 35 is turned off, when the word line 8 is turned on at time t3, the transistor 1 is turned on and a part of the charge stored in the storage node 20 is turned on. Is transferred to the node 22 and the storage node 20
And the potential of the node 22 becomes VH1. Now, storage node 2
If the storage capacitance 2 of 0 is Cs and the stray capacitance 25 of the node 22 is Cf, Becomes

Thereafter, at times t4, t5,..., The partial write control line 37 and the word line 8 alternately change to “H”, and the potential of the storage node 20 decreases due to the charge pumping action of the stray capacitance 25 as described above. , Eventually destroying the data.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described various problems, and an object of the present invention is to provide a semiconductor memory device capable of simultaneously performing partial writing on a plurality of words and having a small number of constituent elements. .

[Means for solving the problem]

A semiconductor memory device according to the present invention includes a memory cell connected to first and second control signal lines which are paired with a bit line, a word line and a bit line and which are complementary to each other. The memory cell includes a storage node for storing information, and first and second switch means. The first switch means is connected between the bit line and the storage node, and the second switch means Connected between the control terminal of the first switch means and the word line;
These are controlled by first and second control signal lines,
When the first control signal line is in an active state and the second control signal line is in an inactive state, the second switch is turned on, the first switch is controlled by the word line, and the first switch is controlled by the word line. When the second control signal line is inactive and the second control signal line is active, both the first and second switch means are controlled to be non-conductive.

[Action]

In the semiconductor memory device according to the present invention, at the time of writing information, if the first control signal line is active and the second control signal line is inactive, the second switch means becomes conductive. . Therefore, the first switch is controlled by the word line, and when the word line is activated, the first switch is turned on and the information of the bit line is written to the storage node. On the other hand, when writing information,
If the first control signal line is in an inactive state and the second control signal line is in an active state, both the first and second switch means become non-conductive, regardless of the state of the word line and the bit line. Writing to the storage node is prohibited.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention. The first CAM cell contains seven n
It comprises channel MOS transistors 1 to 5, 50 and 51. Transistor 1 is connected between bit line 6 and storage node 20, and transistor 2 is inverted bit line 7 and inverted storage node.
Connected between 21 and. Transistor 50 is connected between word line 8 and the gates of transistors 1 and 2, the conduction of which is controlled by partial write control line 37. Transistor 51 is connected between partial write control line (first control signal line) 37 and the gates of transistors 1 and 2, and its conduction state is inverted partial write control line (second control signal line).
Control signal line) 38. The other parts are the same as the CAM cell of FIG.

 Next, the operation of the CAM cell of FIG. 1 will be described.

Partial write control line 37 is "H", inverted partial write control line
When 38 is "L", transistor 50 is on and transistor 51 is off, and the gates of transistors 1 and 2 are connected to word line 8 via transistor 50.
The operation is equivalent to that of the CAM cell in FIG.

On the other hand, when the partial write control line 37 is "L" and the inversion partial write control line 38 is "H", the transistor 50 is off and the transistor 51 is on, and the gates of the transistors 1 and 2 are partially connected via the transistor 51. Since it is connected to the write control line 37, it becomes "L", and the transistors 1 and 2 are turned off regardless of the state of the word line 8.

Therefore, during the partial write operation, the partial write control line 37 corresponding to the bit whose writing is to be inhibited is set to “L”, the inverted partial write control line 38 is set to “H”, and in other cases, the partial write control line 37 is set to “H”. If the "H" and the inverted partial write control line 38 are set to "L", simultaneous writing to a plurality of words can be performed with a small number of elements in addition to the function equivalent to the CAM cell of FIG.

FIG. 2 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention. In the present embodiment, the gate of the transistor 50 is connected to the partial write control line 37 via the transistors 52 and 53 connected in parallel, the gate of the transistor 52 is connected to the partial write control line 37, and the gate of the transistor 53 is inverted partial write. Connected to control line 38.

In the CAM cell of FIG. 1, when writing "H" to the storage node 20, assuming that the "H" levels of the partial write control line 37, the word line 8 and the bit line 6 are equal to the power supply voltage Vcc, the transistor 1 , 2 becomes Vcc−Vth (Vth is the threshold voltage of the transistor).
Only the voltage of Vcc-2Vth is written. In the CAM cell of FIG. 2, when the partial write control line 37 is set to Vcc, the gate (node 60) of the transistor 50 is charged to Vcc-Vth via the diode-connected transistor 52. Thereafter, when the word line 8 is boosted to Vcc, the node 60 is boosted to Vcc or more by a self-boost effect due to the gate capacitance of the transistor 50, and the gate voltages of the transistors 1 and 2 become equal to the voltage of the word line 8. Therefore, the voltage of Vcc-Vth is written to the storage node 20 as in the CAM cell of FIG.
The partial write control line 37 is set to “L”, and the inverted partial write control line 38
To “H”, the transistors 51 and 53 are turned on,
The gates of the transistors 1, 2, 50 are discharged to "L".

Therefore, in this embodiment, simultaneous writing to a plurality of words can be performed with a small number of elements in the same manner as in the first embodiment, and in addition, Vcc-V
th voltage can be written.

Although the switch elements in the first and second embodiments are all constituted by n-channel MOS transistors, other switch elements may be used. In this case, a CAM cell having the same function is used. Can be configured.

〔The invention's effect〕

As described above, according to the present invention, the storage node for storing information, and the first node connected between the storage node and the bit line.
Switch means, second switch means connected between the control terminal of the first switch means and the word line, and first and second control signal lines which form a pair with the bit line and are complementary to each other. When the first control signal line is in an active state and the second control signal line is in an inactive state, the second switch means is turned on and the first switch means is connected to the word line. The first and second switch means are turned off when the first control signal line is inactive and the second control signal line is in active state. In a write operation, the first control signal line corresponding to the bit whose writing is to be inhibited is inactivated, the second control signal line is activated, and otherwise, the first control signal line is activated. , Deactivate the second control signal line It leads to an effect that can be configured with a small number of elements the CAM cell with simultaneous partial write function for a plurality of words.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a conventional CAM cell, FIG. 4 is a diagram showing a word composed of four CAM cells, FIG. 5 is a diagram showing an array composed of four words, and FIGS. FIG. 9 is a circuit diagram showing a CAM cell according to the prior art that can simultaneously and partially write to a plurality of words. FIG. 9 is a timing chart for explaining the operation of the conventional CAM cell. In the figure, 1 to 5, 32 to 36, and 50 to 53 are n-channel MOS transistors, 6 is a bit line, 7 is an inverted bit line, 8 is a word line, 10 is a match line, 20 is a storage node, and 21 is inverted storage. A node 37 is a partial write control signal line (first control signal line);
Reference numeral 38 denotes an inverted partial write control signal line (second control signal line). In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A storage node for storing information, a first switch connected between the storage node and a bit line, and a connection between a control terminal of the first switch and a word line. A second switch means, and first and second control signal lines paired with the bit line and complementary to each other, wherein the first control signal line is in an active state and the second When the control signal line is in an inactive state, the second switch means is conductive, the first switch means is controlled by the state of the word line, and the first control signal line is in an inactive state A semiconductor memory device including a memory cell configured such that when the second control signal line is in an active state, both the first and second switch means are in a non-conductive state.