JP3045139B2 - ATM communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an ATM switching system used for wideband ISDN, and more particularly to an ATM switching system suitable for burst data communication services.

[0002]

2. Description of the Related Art As a communication service mode in a broadband ISDN, a switched virtual connection (SVC) is used.
Mode and a PVC (Permanent virtual connection) mode.

[0003] In the SVC mode, when a call is set (call connection), A
VPI / VCI to the call in the TM switching system
(Virtual path identifier / Virtual channel identif
ier) to secure a band for the call at the same time as the establishment of the routing path. For this reason,
In the SVC mode, the amount of incoming cells for each output line of the ATM switch is within a predetermined band, and the storage capacity of the output cell buffer provided for each output line can be relatively small. In the case where calls are concentrated,
A situation may occur in which the storage capacity of the buffer for storing and exchanging cells is exceeded, and some three cells must be discarded.

[0004] On the other hand, in the PVC mode, VPI / VCI is fixedly assigned in advance between specific communication terminals, so that the terminal device can communicate with a dedicated line at any time. ATM for communication in PVC mode
In the switching system, since the band securing for VPI / VCI performed in the SVC mode is omitted, when a plurality of burst data in the PVC mode destined for the same output line are simultaneously input to the AT switch, the above output is output. Excessive ATM cells exceeding the bandwidth of the output line flow into the buffer memory paired with the line, and the excess cells exceeding the buffer capacity must be discarded.

In order to avoid such cell discard,
For example, a method in which a buffer capacity sufficient to cope with the occurrence of a plurality of burst data on the same output route is prepared in advance,
Alternatively, prior to transmission of burst data from the 5-PVC mode terminal, a method is conceivable in which each system on the data path secures a necessary band.

[0006]

However, the terminal device R
Since the burst data output from the AM or the hard disk may reach an amount of 1 Mbit to 1 Gbit, a method of preparing a buffer capacity capable of coping with a plurality of burst data in the ATM switch in advance is not enough. Is enormous, which is not practical in terms of memory utilization efficiency.

[0007] Further, in the method of securing a band every time burst data is transmitted in the 6 PVC mode, the time required for securing the band cannot be ignored, and there is a problem that the efficiency of communication in the terminal device is reduced. For example, an ATM switching system in which control information such as call control and band control is collected in a processor and various kinds of control are performed by commands from the processor is employed. For example, data of about 10 Mbit is transferred by 150 Mb / s transfer. When a wideband ISDN capable of transferring data in 100 ms or less is configured, the time required for securing the band may exceed the time required for data transfer, and the overhead time for securing the band may be a bottleneck in burst data communication. The overhead time can be reduced to some extent by increasing the processing power of the processor, but there is a limit to the improvement due to such processor power.

It is an object of the present invention to provide an improved ATM switching system suitable for communicating burst data and an ATM switching system.
It is to provide a TM cell control method.

Another object of the present invention is to provide an AT which can use a relatively small buffer memory capacity for each output line and efficiently communicate burst data in PVC mode.
An M switching system and an ATM cell control method are provided. More specifically, the present invention relates to 8,
ATM cell transfer method suitable for transmitting and receiving burst data 9
It is an object of the present invention to provide an ATM switching system and an ATM cell control system which can efficiently communicate 0 burst data while avoiding 6 and 9 congestion in an ATM switching system using the ATM. (1) To prevent a part of the cells constituting the burst data from being discarded (2)
Invalid cells accumulate in the M switching system or 3
It is an object of the present invention to provide an ATM switching system and an ATM cell control system which are excellent in buffer memory use efficiency. It is another object of the present invention to provide an ATM switching system and an ATM cell control system which can easily perform congestion control by reducing a cell retransmission request to a burst data transmission source due to four cell discards by five.

[0010]

In order to achieve the above object, an ATM switching system and an ATM switching system according to the present invention are provided.
In the cell control method, when a plurality of burst data directed to the same output line overlap with each other and flow into the switching system, they belong to one or a plurality of burst data specified when the first cell of each burst data arrives. It is characterized in that only cells are passed and cells belonging to other burst data are discarded.

Here, the selection of cell passing / discarding is performed, for example, with respect to burst data in which the head cell arrives when there is room in the band of the output line, all cells belonging to the head cell are passed, and there is no room in the band. With respect to the burst data at which the first cell arrives at that time, all the cells belonging to the burst data are discarded.

More specifically, for example, for each output line, status information indicating the use status of the output band or the use of other burst data is stored, and when the head cell of each burst data arrives, Based on the state information, if the burst data is in a state where transmission is permitted, a part of the header information of the head cell is registered as identification information of a burst permitted to pass, and
The head cell is temporarily stored in the buffer memory. At the time of arrival of the head cell, if the band of the output line is in a state in which transmission of the burst data is not allowed, the head cell is discarded. When a cell other than the head of the burst arrives, it is determined whether the cell is a passing cell or a discarded cell depending on whether or not the header of the cell includes the registered burst identification information. The registration of the identification information of the pass-permissible burst is deleted when the last cell of the burst is processed.

As the identification information of the pass-permitted burst, 7 PVC identification information of 7 cells included in the header portion of the head cell of the burst data, for example, VCI (Virtual channe
l identifier), VPI (Virtual path identifier),
A value obtained by combining VPI and VCI, a part of VPI, a part of VCI, or a part of a value obtained by combining VPI and VCI can be used.

According to the present invention, even when a plurality of burst data destined for the same route arrive at a time overlap,
At the time of arrival of the first cell of the burst data, it is determined whether or not the burst data is allowed to pass, and for the burst data that has refused passage, all cells arriving after that are discarded. Since all the arriving cells can be passed, it is possible to prevent cell discard due to congestion from spreading to all bursts, and reduce the number of burst data to be retransmitted due to cell discard.

Further, according to the present invention, for the burst data rejected to pass, all cells arriving after that are discarded, so that output cells are temporarily stored for each output line. Buffer memory capacity required for the operation can be reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an ATM to which the present invention is applied.
1 shows an example of the overall configuration of a switching system or an ATM switch.

In the figure, L1-i (i = 1 to N) is an input line, L6-i (i = 1 to N) is an output line, and these lines have a fixed length in the form of an optical signal or an electric signal. Transfers a packet (ATM cell). Line L1-i
And L1-i form a pair, for example, forming a subscriber circuit connected to a terminal device (or a relay circuit connected to another switching system). 1 is a switch,
2-i (i = 1 to N) is a line processing circuit provided for each subscriber circuit, and 3 is a switch 1 via lines L3 and L4.
And a control circuit connected to each line processing unit and the switch 1 via the control bus L0.

The cells input from the input lines L1-1 to L1-N are processed by line processing circuits 2-1 to 2-N for optical / electrical conversion, transmission frame termination, cell synchronization, etc. according to the system configuration. Processing, header conversion and addition of routing information required by the switch 1 are performed.

Cells input from the line processing circuit 2-i to the switch 1 via the line L2-i are transferred to the lines L5-1 to L5 according to the routing information added to the header.
-N and L4. Line L5
-1 to L5-N are output to the line processing circuit 2-
After processing such as cell synchronization, transmission frame termination, and electrical / optical conversion at 1-2-N, the output lines L6-1 through L6-1, respectively.
Output to L6-N.

The switch 1 distributes cells for call processing control or network management (hereinafter, referred to as control cells) to the line L4 and transfers them to the control circuit 3. The control circuit 3 controls the switch 1 and the line processing circuit 2-1 via the control bus L0.
... 2-N and collects information on these elements via the control bus L0. The control circuit 3 generates a cell including control information to be transmitted to a terminal device connected to the subscriber's circuit or another ATM switching system, and outputs the cell to the line L3. This cell is switch 1
And is transferred to any of the lines L5-1 to L5-N through the line processing circuit and transferred to the destination terminal device or another ATM switching system.

FIG. 2 shows an embodiment of the control circuit 3.

The control circuit 3 includes a control signal processing circuit 30 and
It comprises a control processor 31 and a main memory 32. The control cell input from the line L4 is assembled into a message by the control signal processing circuit 30, and then supplied to the control processor 31 via the control bus L0. The control processor 31 decodes the contents of the message received from the control signal processing circuit 30, stores necessary information in the main memory 32, and switches the switch 1 and the line processing circuit 2 as necessary.
A command for controlling -1 to 2-N is output to the control bus L0. Also, other ATMs generated by the control processor 31
The message including the control information addressed to the switching system or the terminal device is divided into cells by the control signal processing circuit 30 and output to the line L3.

FIG. 3 is a diagram for explaining the basic configuration and operation of the ATM switch according to the present invention.

The ATM switch 1 includes a multiplexing circuit 11, a plurality of queue filters 12-i (i = 1 to N) provided for output lines (lines L5-1 to L5-N), and a PVC.
It is composed of an assignment circuit 13-i (i = 1 to N) and a FIFO buffer 14-i (i = 1 to N).

The cells input in parallel from the lines L2-1 to L2-N are converted into a serial cell string by the multiplexing circuit 11, and then converted into the plurality of queue filters 12-1 to 12-12.
-N in parallel. Each queue filter 12-i
Determines whether the input cell is a cell to be output to the output line L5-i corresponding to the queue filter based on the routing information of the input cell, and selectively assigns only the cells to be output to the PVC. It is given to the circuit 13-i. PVC
The allocating circuit 13-i performs a burst cell control operation according to the vacant band of the output line described later, and selectively supplies the input cell to the FIFO buffer 14-i. The cells stored in the FIFO buffer 14-i are read out to the output line L5-i in accordance with the output line speed.

In the switch 1, the SVC (Switched Visible)
rtual Connection) mode and PVC (Permanent Virtua)
l Connection) mode.

In the SVC mode, a band on the output line L5-i of the switch 1 is secured when a call is connected, and a call setting operation is performed so as not to exceed the band of the output line. In this case, even if cells are input from a plurality of input lines L2-1 to L2-N concentrated on the same output path, this is a temporary phenomenon, and the band is It does not exceed the line speed of the output lines L5-1 to L5-N. Accordingly, if the capacity of the FIFO buffers 14-1 to 14-N is sufficient, the probability of cells overflowing the buffer can be extremely reduced, and the PVC allocation circuits 13-1 to 13-1 can be reduced.
The function of adjusting the cell flow rate by 3-N is not required.

On the other hand, the PVC mode is a communication service that transmits data more frequently than circuit switching and is suitable for transferring burst data that occurs sporadically after a relatively long idle period. In order to avoid wasting time and increasing the frequency of call control processing, a call is always fixedly allocated between transmitting and receiving terminals, so that the control circuit 3 does not need to perform call control at the time of burst data transmission. It is a service form. The PVC mode is based on the premise that the transmission of each burst data is instantaneous and the probability that a plurality of burst data transmissions compete on the same line is low, and the bandwidth allocation of the output line corresponding to the call is omitted. ing.

The problem of the PVC service is that, for example, as shown in FIG. 3, burst data input from a plurality of input lines L2-1 and L2-N overlapped in time, that is, a plurality of columns of continuous cells are identical. When going to an output line, for example, l5-1, the FIFO buffer 141 of the output line is used.
That is, the amount of cells input to -1 exceeds the output band.

In general, FIFO buffers 14-1 to 14-14
Since the capacity of −N is designed on the assumption that the amount of cells input thereto is within the range of the band of the output line, it exceeds the band like the simultaneous occurrence of a plurality of burst data shown here. It is not always possible to cope with the case where the inflow of cells continues for a certain period of time. When cells flow in beyond the output bandwidth, the FIFO buffer becomes full and subsequently arriving cells overflow the buffer and are discarded. In this case, since a part of the succeeding cell is discarded in all the burst data, all of the plurality of conflicting burst data become incomplete and retransmission is forced.

In order to cope with the above-mentioned phenomenon, in the present invention, at least one of a plurality of conflicting burst data is prevented from being discarded and a cell input to a FIFO buffer is performed so that data can be completely transferred. Is provided with a PVC allocating circuit 13-i (i = 1 to N) for selectively controlling.

In the present invention, the PVC assignment circuit 13
When the head cell of the burst data in the PVC mode arrives, if there is room in the bandwidth of the output buffer, the burst data identifier (PVC) is registered as the identification information of the burst allowed, and the head cell, and The burst data cell having the registered identification information that arrives after that is subjected to storage processing (pass processing) in the output buffer. If there is no band margin at the time of arrival of the head cell, the head cell is discarded without registering the PVC (not stored in the buffer), and the burst data cell arriving after that having an unregistered identifier is also discarded. Perform processing.

In the simplest embodiment of the present invention, when a plurality of burst data conflict on the same output line, each VC
The allocating circuit passes only the earliest burst data, and until the burst data is completely passed, discards all cells of other burst data that arrive later.
In this case, the PVC registered as the pass-permitted burst identification information when the first cell of the earliest burst data arrives is deregistered when the last cell of the burst data arrives, and the PVC is deregistered. Until the above, PVC registration of other burst data is not performed, so that all cells of the later-arriving burst data having no permissible burst identification information are discarded, and the burst data in which the first cell arrives after the PVC is deleted is replaced with a new burst data. It becomes a permissible burst.

In the example of FIG. 3, the input lines L2-1 and L2
-N Of the two burst data arriving at the same time,
The burst data of the line L2-1 to which the first cell arrives first acquires the pass right, and the PVC allocating circuit 13-1 passes the burst data cell of the line L2-1 to the line L2-
A control operation is performed to discard all N burst data cells. According to this embodiment, since the burst data of the first line L2-1 can pass through the FIFO buffer at the time of contention, the burst data is completely transferred, and the burst data that needs to be retransmitted is sent later. Wearing line L
2-N data can be localized.

FIG. 4 shows an example of a cell format input to the switch of FIG.

The input cell includes a header section 400 and an information section 41.
The header section 400 includes an empty / closed field 401 indicating whether or not the cell is empty, and a start display field 4 indicating that the cell is the first cell of the data (burst data).
02, an end display field 403 indicating the end cell of the data (burst data), and a field 40 indicating the output line (output queue) which is the routing information.
4 and a VPI / VCI (PVC) field 405 which is call identification information.

The switch determines to which queue filter 12-1 to 12-N the cell should be supplied by the output queue number 404 in the header information of the input cell. When information indicating the start display (head cell) is set in the field 402, the PVC allocation circuits 13-1 to 13-1
3-N indicates the PV included in the field 405 of the cell if no other burst data is using the buffer.
The value of C is stored (registered) as identification information of the permissible burst data. Note that the PVC value includes the VCI value, the VPI value, and the VPI set in the field 405.
A value obtained by integrating PI and VCI, or a part of these values is used.

When cells other than the head cell among the cells constituting the burst data are input, the PVC allocating circuits 13-1 to 13-N store the data in the field 405 in the field registered at the time of arrival of the head cell. It is determined whether or not the same identification information as the identification information of the allowable burst data is included, and only cells that match the registered identification information are to be passed,
Others are discarded. When a cell including the end indication (last cell indication) arrives in the field 403, if the cell is the last cell of the cell-permissible burst, the PVC allocation circuit 1
3-1 to 13-N delete the registration of the identification information of the permissible burst data, and thereafter, 4 indicates that the first cell has arrived. Makes it possible to pass through the output buffer.

FIG. 5 is a block diagram showing the PVC allocating circuit 13 shown in FIG.
It is a figure which shows one Example of -i.

The header analysis circuit 131 determines whether the input cell is empty or empty.
Closed field 401, start display field 402, end display field 403, and PVC field 405
Is output separately.

If the empty / closed display field contains a value "0" indicating an empty cell, the AND circuit 13d outputs a signal "0" and causes the selector 13e to select and output an empty cell pattern. The unused / used register 138 stores information indicating whether or not the output line is being used for transmitting burst data (information indicating whether or not the output line has sufficient bandwidth). The register 139 is for storing the PVC (identification information of the permissible burst data) of the burst data currently using the output line.

The PVC / SVC register 13a stores the P
Indicates whether the queue allocated by the VC allocation circuit is for the SVC mode or the PVC mode. If the above register is set for SVC mode, PVC / SV
The C register 13a outputs a signal "1", and outputs the signal
When the empty / closed display field is "1" indicating a valid cell, the AND circuit 13d outputs the signal "1", and the selector 13e passes the input cell as it is. In this case, the PVC allocation circuit does not manage the burst data, but passes through the cells. PVC / S
If the VC register 13a is set for the PVC mode, the OR circuit 13c outputs the AND circuit 133 or 135
Is not "1", the signal "1" is not output. Therefore, in this state, the cell output is controlled by the output of the AND circuit 133 or 135.

The setting of the mode in the PVC / SVC register 13a is performed by the control circuit 3 via the control bus L0 and the microcomputer interface circuit 13b. For example, the SVC mode is set as an initial state in the PVC / SVC register 13a of each output line, and when a service operation in the PVC mode is applied for a specific output line,
The corresponding PVC / SVC register 13a is changed to the PVC mode.

Next, the PVC / SVC register 13a stores the PV
The operation in the case of indicating C will be described in detail. If the input cell indicates the first cell, the unused / used register 138
Outputs a signal “0” indicating that it is not in use,
When the closed display field indicates “1” indicating a valid cell, the AND circuit 133 outputs a signal “1”. At this time, the AND circuit 136 outputs “1” under the condition that the AND circuit 134 outputs “0” (when it is not the last cell), and
The circuit 137 sets the load input LD of the register 138 to “1”.
Thus, the unused / used register 138 is set to the in-use state “1”. At this time, the PVC value output from the header analysis circuit 131 is set in the PVC register 139. Further, the “1” output of the AND circuit 133 causes the selector 13 e to selectively output the input cell through the OR circuit 13 c and the AND circuit 13 d. By this operation, when the head cell of the burst data arrives, P
You can register a VC.

When the input cell indicates the start display,
When the unused / used register 138 indicates that the burst data is being used, the output of the unused / used register 138 is “1”.
Since the AND circuit 133 outputs “0”, the value is not set in the unused / used register 138.
In this case, the input cell selection output control operation through the OR circuit 13c is not performed. This operation indicates that when the first cell of the burst data arrives, if the other first-arrived burst data is using the buffer, the burst data that has arrived this time cannot be registered in the PVC.

When the input cell is the last cell (field 4
03 indicates that the end display is present)), the empty / closed display field 401 indicates “1” indicating that a valid cell is present, and the unused / used register 138 indicates “1” indicating that the cell is in use.
Is output, and if there is an “1” output from the match detection circuit 132 indicating that the PVC registered in the PVC register 139 matches the PVC output from the header analysis circuit 131,
The D circuit 134 outputs “1”. At this time, since the AND circuit 136 outputs “0” and the OR circuit 137 outputs “1”, the unused / used register 138 is set to “0” in the unused state. Thus, when another new burst data arrives, the buffer can be used by the burst data.

The input cell is a valid cell, the unused / used register 138 indicates the use state, and the PVC register 13
9 is equal to the PVC value of the input cell,
The D circuit 135 outputs "1", and the OR circuit 13c, AN
The selector 13e is caused to select and output an input cell through the D circuit 13d. With this control, when a cell of the PVC in use arrives, the cell can pass.

FIG. 3 shows a case where only one burst data is passed through one output circuit at a time. For example, if the maximum bandwidth of the burst data is 10 Mb / s and the bandwidth of the output line is 150 Mb / s. For example, 15 burst data can be simultaneously passed through one output line.

FIG. 6 shows an example of the configuration of an ATM switch capable of passing a plurality of burst data through one output line.

In this example, a plurality of queue filters 1 are provided for one output line, for example, output line L15-1.
2-11 to 12-1m and a plurality of PVC allocating circuits 13-
11 to 13-1m and a plurality of FIFO buffers 14-1
1 to 14-1m, one selector 15-1 and a band control table 16-1 connected to the selector.

Each PVC allocating circuit passes only one burst data at a time, but since a plurality of sets of PVC allocating circuits are mounted on one output line, up to m burst data can be simultaneously transmitted on each output line. You can pass. The bandwidth control table 16-1 includes the output timing counter 1
7 outputs a queue number (FIFO buffer number) corresponding to the timing signal output from the selector 15-1.
Then, the user selects a FIFO buffer corresponding to the queue number from the FIFO buffers 14-11 to 14-1m.

In this configuration, for example, only the specific PVC allocation circuit 13-11 is set to the SVC mode, and the other
When the C allocation circuits 13-12 to 13-1m are set to the PVC mode, cells dedicated to the SVC mode are supplied to the FIFO buffer 14-11 connected to the specific PVC allocation circuit 13-11, and the bandwidth control table 16 The cell is output in the band allocated by −1, and the remaining band is m−
It can be assigned to one burst data band. Therefore, it is possible to pass a cell of a call of a different service through one output line.

In the example of FIG. 6, a configuration is shown in which a plurality of queues are provided in each output line in a physically separated form.
The configuration in which a large number of queues are provided independently and individually has a large division loss of the buffer memory, which is disadvantageous in hardware implementation.

FIGS. 7 to 9 show an example of a switch configuration employing a common buffer, which is functionally equivalent to FIG.

In FIG. 7, the ATM switch comprises a multiplexing circuit 11, a common buffer 18, a separating circuit 19, and a buffer control circuit 10.

The cells input in parallel from each of the input lines L2-1 to L2-N are time-division multiplexed by the multiplexing circuit 11, and input to the common buffer 18 as a serial cell row. The buffer control circuit 10 analyzes the header part of the cell output from the multiplexing circuit 11 to the signal line L14, obtains an address of a list structure to which the cell is to be linked, and gives this to the common buffer as a write address. Further, the buffer control circuit 10 includes output lines L5-1 to L5-
At a predetermined timing synchronized with the cell output to the N, a read address is given to the common buffer 18 and the common buffer 1
8 is read out. The separation circuit 19 outputs the cells read from the common buffer 18 to the output lines L5-1 to L5.
-N periodically.

FIG. 8 shows the buffer control circuit 1 in FIG.
It is a figure which shows 1 Example of 0.

The header of the input cell is input to the PVC allocating circuit 107 via the line L14. The PVC allocating circuit 107 performs a control operation for registering an identifier of burst data permitted to pass (PVC allocation) and discarding a cell of burst data not permitted to pass. Also,
The PVC allocating circuit 107 outputs the output queue number to the line L100 and outputs the write enable signal to the line L100.
152. As a result, the write address corresponding to the queue number is read from the write address memory (WARAM) 101 and output to the line L150.

Reference numeral 103 denotes a pointer address (write address or read address) indicating a record (cell data) to be accessed next in each of a plurality of queues formed in the common buffer 18 (FIG. 7). This is a next address memory for storing.

In the write cycle of the input cell,
FIF, an address queue that stores empty addresses
An unused address is output from the top of O104 and is supplied as data (next address) to the write address memory WARAM 101 and the next address memory 103, respectively. The write address memory WARAM 101 is
It has a plurality of record storage locations corresponding to queue numbers. Now, the write address memory WARAM101
Is addressed by the queue number extracted from the header part of the input cell by the PVC allocating circuit, and the next address stored last time is read from the memory location corresponding to the queue number, and instead, The empty address extracted from the FIFO 104 is stored as a new next address in the storage location.

The next address memory 103 for storing the empty address (next address) stores the write address memory WARAM as the write address WA.
The next address output from 101 and stored last time is given. The write address WA is also used as a write address of an input cell to the common buffer 18 shown in FIG. 7, and as a result, the input cell and the next address are paired with the common buffer memory 18 to form a pair. These are stored in the next address memory 103, respectively.

Therefore, when a cell having the same queue number as the cell stored this time arrives later, the cell is addressed by the queue number and the write address memory WARAM10 is written.
When an input cell is written into the common buffer 18 with the next address output from 1 as the write address WA, the memory location of this input cell in the common buffer is stored in the next address memory 103 in pairs with the previous input cell. Cell records having the same queue number and the same queue number have a list structure linked one after another by the next address stored in the next address memory.

In the cycle of reading cells from the common buffer 18, the queue number to be accessed (read) is output from the bandwidth control table 105 in response to the timing given from the output timing counter 106.

The cell presence / absence detection circuit 108 comprises, for example, a plurality of counter areas corresponding to queue numbers, and when writing cell data to the common buffer, increments the count value of the counter area corresponding to the queue number of the input cell. When reading the cell data from the common buffer, the count value of the count area corresponding to the queue number given from the band control table is checked, and it is determined whether or not the cell exists in the corresponding queue in the common buffer. Circuit. Cell presence / absence detection circuit 108
Inputs a queue number to be read from the line L103, outputs a read enable signal if a cell exists in the queue, and decrements the count value.

Reference numeral 102 has a plurality of storage areas for storing a next read address corresponding to a queue number.
When the read enable signal is “1”, the line L10
3 is a read address memory (RARAM) for outputting the next read address from the storage area corresponding to the queue number designated from No. 3. The read address output from the memory 102 is supplied to the next address memory 103 and the common buffer 18 as a read address RA via the line L151. As a result, one cell data is read from the queue corresponding to the queue number in the common buffer 18, and the next address is read from the next address memory 103 in synchronization with this. The next read address is stored in a storage area of the read address memory 102 corresponding to the queue number, and serves as a read address when accessing a queue having the same queue number next time. Since the address RA read from the read address memory 102 to the line L151 is used, the empty address FIFO1 is used as an unused address.
04.

The bandwidth control table 105 is, for example, as shown in FIG.
As shown in the figure, the number of record areas equal to the number N of output lines (output ports) of the switch 1 is provided, and read permission / prohibition information and queue number information (corresponding to the RARAM address) are stored in each record area. It has become. When the output port number generated by the output timing counter 106 shown in FIG. 8 is given as an address to the bandwidth control table 105, read permission / inhibition information and queue number information are read from the record area corresponding to the output port number. . When the read permission / prohibition information indicates “prohibited”, the operation of reading cells from the common buffer described above is not performed. The content of each record of the bandwidth control table is controlled by the control device 3.
It is set via the control bus L0.

In the bandwidth control table shown in FIG. 13, if the same queue number is set in two or more record areas designated by different output port numbers, cells are transferred from the same queue to a plurality of output ports of the switch. Can be output, and cells can be output from the queue at twice or more the speed of the normal queue. Conversely, the number of records in the bandwidth control table is set to, for example, 4
When the output timing counter 106 generates port numbers from 1 to 4N and writes the queue number “1” only to the first address of the bandwidth control table, the output port 1 The cell with the queue number "1" is read out only once, and the cell can be output in a quarter band. In this way, the bandwidth control table can control the cell reading speed from each queue depending on the setting of its contents, and can control the bandwidth for each queue.

FIG. 9 shows the PVC allocating circuit 10 in FIG.
FIG. 7 is a diagram showing an example of No. 7;

The header analysis circuit 131 'extracts the contents of the empty / closed field, start display field, end display field, PVC field, and queue number field from the header of the input cell. When the signal of the empty / closed display field outputs “0” indicating an empty cell, AND
The circuit 13d outputs "0" and inhibits writing to the common buffer 18.

The unused / used RAM 138 'is a RAM for storing the used / unused information of the burst data for each queue number. The PVC RAM 139 'is a RAM for storing a PVC of burst data in use for each queue number. Also, PVC / SVC RAM1
3a 'is for designating for each queue number whether it is for the SVC mode or the PVC mode.

If specified for SVC mode,
The PVC / SVC RAM 13a 'outputs "1"
The R circuit 13c outputs "1", the AND circuit 13d outputs "1" indicating that the empty / closed display indicates a valid cell, and the input cell is written into the common buffer 18. Therefore, P
The VC allocating circuit 107 performs a cell write operation without managing burst data. If specified for the PVC mode, the output of the AND circuit 133 or 135 is "1"
Otherwise, the OR circuit 13c does not output “1”. Therefore, in this case, the output of the AND circuit 133 or 135 controls the cell writing. The above PVC / SVC R
The mode setting for the AM 13a 'is performed from the control circuit 3 via the control bus L0 and the microcomputer interface circuit 13b'.

Next, the PVC / SVC RAM 13a '
Describes the operation when the PVC mode is designated for the queue number of the input cell.

If the input cell is the first cell of the burst data (indicating the start display), the unused / used RA
When M138 'outputs "0" indicating that it is not in use, and when the empty / closed display indicates "1" indicating that there is a valid cell, the AND circuit 133 outputs "1". At this time, the AND circuit 1
The AND circuit 136 outputs “1” under the condition of “0” output (value when the end display is not set), and the OR circuit 137 sets the data load LD to “1”. As a result, on the unused / used RAM 138 ', the display "1" indicating that the cell is in use is set in the record area corresponding to the queue number of the input cell. At this time, the PVC RAM
The record area corresponding to the queue number of the input cell in 139 'is provided with the P output from the header analysis circuit 131'.
The VC value is set. Further, the “1” output of the AND circuit 133 is passed through the OR circuit 13c to the AND circuit 1
3d outputs a cell write enable. With this operation, the PVC can be registered when the head cell of the burst data arrives.

If the input cell is the first cell and the unused / used RAM 138 'indicates that burst data is being used, the output of the unused / used RAM 138' is "1",
The AND circuit 133 outputs “0”. Therefore, no value is set in the unused / used RAM 138 '.
The operation of writing the input cell to the common buffer 18 through the OR circuit 13c is not performed. That is, if another burst data is already using the output line when the first cell of the burst data arrives, the PV of the newly arrived burst data is used.
C is not registered as a pass permission identifier.

When the input cell is the last cell of the burst (when the end display is shown), the empty / closed display indicates "1" indicating that a valid cell is present, and the unused / used RAM 138 'indicates that it is in use. "1" is output and the match detection circuit 13
2 is the PV registered in the PVC RAM 139 '.
When "1" indicating that C and the PVC output from the header analysis circuit 131 'match is output, the AND circuit 134
Outputs “1”. At this time, since the AND circuit 136 outputs “0” and the OR circuit 137 outputs “1”, the record corresponding to the queue number of the input cell in the unused / used RAM 138 ′ indicates the unused state. "0" indicating
Is set. As a result, another burst data becomes available upon arrival.

The input cell is a valid cell, the unused / used RAM 138 ′ indicates the use state, and the PVC RAM 1
If the value of 39 'matches the PVC value of the input cell,
The AND circuit 135 outputs “1”, and outputs a write enable signal from the AND circuit 13d through the OR circuit 13c. With this control, when a cell of the PVC in use arrives, the cell can pass.

Although the PVC assignment circuit shown in FIGS. 5 and 9 has shown an example in which only one burst data is passed through one queue, the following describes an embodiment in which a plurality of burst data is passed through one queue. State.

FIG. 10 shows an embodiment in which a plurality of burst data can be set in each queue instead of the PVC allocating circuit of FIG. 3 or FIG.

In the input cell, the header analysis circuit 131 separates and extracts the fields of empty / closed, start, end and PVC, and outputs an empty / closed display field signal of "0" indicating an empty cell. Causes the AND circuit 13d to output "0" and cause the selector 13e to output an empty cell pattern. C
An AM (Content-addressable memory) 13f is a memory for registering a PVC of burst data, and an unused address FIFO 13g is for storing addresses not used in the CAM 13f. up/
The down counter 13h is a counter that counts the number of registered burst data, and is a comparator 13i.
Is used to determine whether the number of registered burst data exceeds a predetermined threshold, and performs an operation of suppressing the number of burst data passing through one queue to be equal to or smaller than the threshold.

The PVC / SVC register 13a stores this P
Is the queue processed by the VC allocation circuit for SVC mode?
This is for specifying whether it is for VC mode or not.
When the mode is designated, the PVC / SVC register 13a outputs "1" and the OR circuit 13c 'outputs "1", and the empty / closed display indicates "1" indicating that there is a valid cell. The AND circuit 13d outputs “1”, and the selector 1
The input cell is passed through 3e as it is. Therefore, PVC
The allocation circuit does not manage the burst data but passes through the cells. When the PVC / SVC register 13a specifies the PVC mode, the OR circuit 13c '
If the output of the circuit 133 'or 134' is not "1", the output does not become "1". Therefore, in this case, AND
The cell output is controlled according to the output of the circuit 133 'or 134'. The mode of the PVC / SVC register 13a is set from the control circuit 3 via the control bus L0 and the microcomputer interface circuit 13b.

Next, the PVC / SVC register 13a sets P
The control operation when the VC mode is designated will be described. When the cell arrives, the PVC extracted by the header analysis circuit 131 is input to the CAM 13f as an address,
The determination result of the presence or absence of registration of the passage permission corresponding to the input PVC is output from the AM 13f. OR if registered
The selector 1 is passed through the circuit 13c 'and the AND circuit 13d.
An input cell selection command is given to 3e.

If the input cell is the first cell of the burst data (indicating the start display), the CAM 13f outputs "0" indicating that it is not in use, and the empty / closed display indicates "1" indicating that there is a valid cell. And the comparison circuit 13i indicates that “the value of the up / down counter 13h does not exceed the threshold value”, the AND circuit 133 ′ outputs “1”.
At this time, an address is generated from the unused address FIFO 13g, and on the CAM 13f,
C is registered, and the value of the up / down counter 13h is counted up. Also, “1” of the AND circuit 133 ′
The output causes the selector 13e to select and output the input cell through the OR circuit 13c 'and the AND circuit 13d. By this operation, when the head cell of the burst data arrives, the PV
C can be registered.

If the input cell is the first cell and the value of the up / down counter 13h exceeds the threshold,
The AND circuit 133 'outputs "0". in this case,
No PVC is registered in the CAM 13f.
No input cell selection command is issued by the output of the circuit 13c '. In this operation, when the head cell of the burst data arrives, if a predetermined number of other burst data are already in use of the output circuit, the passage of the currently arrived burst data is not permitted, and the registration of the PVC is not performed. This indicates that operation cannot be performed.

If the input cell is the last cell (when the end display is shown), the empty / closed display is "1" indicating that a valid cell is present, and the CAM 13f outputs "1" indicating that a PVC has been registered. ", The AND circuit 134 '
Outputs “1”. At this time, the corresponding PVC on the CAM 13f is deleted, the address of the record in which the PVC is registered is stored in the unused address FIFO 13g as a free address, and the value of the up / down counter 13h is counted down. As a result, the registered PVC of the passed burst data is deleted, and new burst data arriving after that can be registered.

The up / down counter performs an addition operation with an addition width corresponding to the band of the burst data when registering the identification information of the pass-permitted burst data, and performs a subtraction operation with a subtraction width corresponding to the band when the registration of the identification information is deleted. Is performed, appropriate pass permission control can be performed on a plurality of burst data having different bands so as not to exceed the band of the output queue. In this case, it is necessary to obtain band information for each burst data. For example, a method of preparing a table indicating a band value for each PVC, a terminal device for generating cells, a line processing circuit 2- It can be realized by a method of adding information indicating the band to the first cell of the burst data to 1 to 2-N, or the like.

FIG. 11 is a diagram showing one embodiment of the line processing circuits 2-1 to 2-N in the ATM switching system of FIG.

For example, a cell input from a line L 1 made of an optical fiber is converted into an electric signal by an O / E converter 21, and a transmission frame termination processing is performed by a reception-side SDH termination circuit 22. Cells transmitted by the transmitting clock are:
In the receiving side cell synchronizing circuit 23, it is synchronized with the clock on the switch side distributed in the ATM switching system. The header conversion circuit 24 converts the header of the cell, adds necessary information to the header portion, and outputs the cell to the line L2 serving as a switch input. The cell on the line L5 output from the switch is connected to the transmission-side cell synchronization circuit 27.
Synchronizes from the clock on the switch side to the clock on the transmission side. Transmission side SDH termination circuit 26
Then, the cell is placed on the transmission frame and the E / O converter 25
Then, an electric signal is converted into an optical signal.

FIG. 12 is a diagram showing one embodiment of the header conversion circuit 24 in FIG.

The cells input to the header conversion circuit 24 are
The data is separated into a data part and a header part by a separation circuit 241, and further separated by a header analysis circuit 242 into VPI / VCI, end display, and other parts.

Generally, AAL5 (ATM Adaptation Layer)
In Type 5: connection-oriented data service), an end indicator indicating that it is the last cell of the burst data is added, and this is used. When the VPI / VCI output from the header analysis circuit 242 is input, a new VPI / V
Output CI, empty / close indication, output queue number,
The type of PVC / SVC and the value of PVC are output.
The contents of the header conversion table 243 are rewritten by the control circuit 3 via the control bus L0.

The used / unused table 245 is a table for holding, for each queue, information indicating whether or not the output line is being used by burst data in accordance with PVC.
The empty / close indication signal is “1” indicating a valid cell, and the PVC
When the / SVC type signal is “0” indicating the PVC mode and the information output from the used / unused table 245 outputs “1” indicating unused, this output is displayed on the selector 24a. And at the same time, OR
Through circuit 246 and AND circuit 247, the P
Used / unused table 24 corresponding to VC and queue number
5, the output value of the OR circuit 248 is written to the record area. In this case, the output value of the OR circuit 248 is “0” meaning “in use” unless the end indication is “1”. Is set. It should be noted that a bit pattern indicating start indication is added to the header of the head cell of the burst data.

The empty / closed display is "1" indicating a valid cell, and the PVC / SVC type is "0" indicating a PVC mode.
In this case, when the end display indicating the last cell is output from the header analysis circuit 242, the OR circuit 246 and the AND circuit 24
7, the OR circuit 24 stores a record corresponding to the PVC and queue number of the arrival cell in the used / unused table 245.
8 is written. At this time, the output value of the OR circuit 248 is “1”, which means “not in use”, whereby the registration information in the used / unused table 245 is deleted.

When any of the burst data occupies the queue for more than a predetermined time and unduly interrupts the passage of another burst data, the timer 244 forcibly inhibits the burst data from passing through the cell. Give end indication, PVC
It is provided to cancel the registration of. When the head cell of the burst data arrives, a start indication (unused indication) is output from the used / unused table, and its VPI / V
The values of the timer 244 for the CI and the queue number are reset. The timer 244 updates the timer value as time passes, and when the timer value exceeds a predetermined value, the OR circuit 2
49 is output as “1”, and the OR circuit 249 outputs a control signal “1” indicating end display.

The selector 24a configures and outputs a cell format for a switch by selecting an empty / closed display, a start display, an end display, a queue number, a VPI / VCI, other parts of a header, and data as needed. .

As is apparent from the above-described operation, the header conversion circuit 24 shown here adds a start indication to the first cell of the burst data and forcibly applies burst data occupying the queue for a long time. The feature is in the function of ending the cell transfer operation.

[0096]

As is clear from the above embodiment, according to the present invention, when the head cell of the burst data arrives,
It checks whether there is enough bandwidth for the output queue of the ATM switch through which the burst data should pass, and if the bandwidth can be secured, the burst data is allowed to pass. If the bandwidth cannot be secured, the cell of the burst data is allowed. Are all discarded. By this, ATM
Even if a plurality of burst data exceeding the band arrives at a specific output line of the switch in time overlapping, all the cells of the burst data that are not permitted to pass are discarded,
Burst data cells for which a band has been secured up to that time can be reliably transferred without receiving cell discard due to buffer overflow.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an overall configuration of an ATM switching system to which the present invention is applied.

FIG. 2 is a diagram showing one embodiment of a control circuit of the ATM switching system shown in FIG. 1;

FIG. 3 is a diagram showing one embodiment of an ATM switch having a PVC assignment function.

FIG. 4 is a diagram showing an example of a format of an internal cell.

FIG. 5 is a diagram showing one embodiment of a PVC assignment circuit in FIG. 3;

FIG. 6 is a diagram showing another embodiment of an ATM switch having a PVC assignment function.

FIG. 7 is a diagram showing still another embodiment of an ATM switch having a PVC assignment function.

FIG. 8 is a diagram showing one embodiment of a buffer control circuit in FIG. 7;

FIG. 9 is a diagram showing one embodiment of a PVC allocation circuit in FIG. 8;

FIG. 10 is a diagram showing another embodiment of the PVC assignment circuit in FIG. 3 or FIG. 6;

FIG. 11 is a diagram showing one embodiment of a line processing circuit in FIG. 1;

FIG. 12 is a diagram showing one embodiment of a header conversion circuit in FIG. 11;

FIG. 13 is a diagram showing one embodiment of a band control table in FIG. 8;

[Explanation of symbols]

1. Switch, 2-1 to 2-N ...
Line processing circuit, 3 ... control circuit, 3
0: control signal processing circuit, 31: control processor,
32: Main memory, 11: Multiplex circuit, 12-1
... 12-N, 12-11 to 12-Nm ... queue filter, 13-1 to 13-N, 13-11 to 13-Nm ... P
VC allocation circuit, 14-1 to 14-N, 14-11 to 14
-Nm: FIFO buffer; 131, 131 ': header analysis circuit; 132: match detection circuit, 133, 134;
135, 136, 13d, 133 ', 134' ... AND
Circuit, 137, 13c, 13c '... OR circuit, 138.
Unused / used register, 139 ... PVC register, 13a ... PVC / SVC register, 13b, 13
b ': microcomputer interface, 13e, 15-1 to 1
5-N selector, 16-1 to 16-N, 105 bandwidth control table, 17, 106 output timing counter, 10 buffer control circuit, 18 common buffer, 19 separation circuit,
101: Write address RAM, 102: Read address RAM, 103: Next address memory, 10
4: Empty address FIFO buffer 107: PVC allocation circuit 108: Cell presence / absence detection circuit 13
8 ': unused / used RAM, 139': PVC RA
M, 13a '... PVC / SVC RAM,
13f CAM, 13g unused address FIFO, 13h up / down counter, 13i comparison circuit, 21 O / E converter,
22: SDH termination circuit on the receiving side, 23:
Reception-side cell synchronization circuit, 24: header conversion circuit, 25: E / O converter, 26: transmission-side SDH termination circuit, 27: transmission-side cell synchronization circuit,
241, a separation circuit, 242, a header analysis circuit,
243 ... header conversion table, 244 ...
Timer, 245: unused / used table, 246, 248, 249: OR circuit, 2
47 ... AND circuit, 24a ... selector.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-135248 (JP, A) JP-A-6-268633 (JP, A) IEEE Networks Mag. Vol. 6, No. 5 (1992-9), p. 50-58 (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 12/28 H04L 12/56

Claims (9)

(57) [Claims] An ATM communication apparatus for processing ATM cells including burst data composed of a plurality of ATM cells, comprising: a plurality of input lines, a plurality of output lines, and a buffer memory for storing and exchanging the ATM cells. And control means for writing and reading ATM cells received from any of the input lines to the buffer memory and transferring the ATM cells received from any of the input lines to any of the output lines based on header information of the ATM cells. When the last cell is detected and the first burst cell of the next burst data is identified, if another burst data passing through to the same output line as the next burst data competes with the next burst data, the input line is received. The writing of the plurality of cells to which the next burst data belongs to the buffer memory is stopped, and the first cell belonging to the next burst data is changed to ATM communication device characterized by being configured by the control means for executing a discard control of the continuously plurality of received cells. 2. An ATM communication device for processing an ATM cell including burst data composed of a plurality of ATM cells, comprising: a plurality of input lines, a plurality of output lines, and a buffer memory for storing and switching the ATM cells. And control means for writing and reading ATM cells received from any of the input lines to the buffer memory and transferring the ATM cells received from any of the input lines to any of the output lines based on header information of the ATM cells. When the last cell is detected and the first burst cell of the next burst data is identified, if another burst data passing through to the same output line as the next burst data competes with the next burst data, the next burst data is output. Is determined, and the buffer memory of a plurality of cells to which the next burst data received by the input line belongs is determined based on the determination. An ATM communication apparatus comprising: control means for controlling writing to memory or discarding of a plurality of received cells including a head cell belonging to the next burst data. 3. An ATM communication device for processing an ATM cell including burst data composed of a plurality of ATM cells, comprising: a plurality of input lines, a plurality of output lines, and a buffer memory for storing and switching the ATM cells. And control means for writing and reading ATM cells received from any of the input lines to the buffer memory and transferring the ATM cells received from any of the input lines to any of the output lines based on header information of the ATM cells. When the last cell is detected and the first burst cell of the next burst data is identified, if the next burst data conflicts with the ATM cell train passing through to the same output line as the next burst data, the input line receives the signal. The writing of a plurality of cells to which the next burst data belongs to the buffer memory is stopped, and the plurality of cells including the first cell belonging to the next burst data are stopped. ATM communication device characterized by being configured by the control means for executing a discard control number of received cells. 4. An ATM communication device for processing an ATM cell including burst data composed of a plurality of ATM cells, comprising: a plurality of input lines, a plurality of output lines, and a buffer memory for storing and switching the ATM cells. And control means for writing and reading ATM cells received from any of the input lines to the buffer memory and transferring the ATM cells received from any of the input lines to any of the output lines based on header information of the ATM cells. When the last cell is detected and the first burst cell of the next burst data is identified, if the next burst data conflicts with the ATM cell train passing through to the same output line as the next burst data, the next burst data is discarded. A decision is made to pass or discard, and based on the decision, to the buffer memory of a plurality of cells to which the next burst data received by the input line belongs. And a control means for controlling discard of a plurality of received cells including a head cell belonging to the next burst data. 5. An ATM communication device for processing an ATM cell including burst data composed of a plurality of ATM cells, wherein the ATM communication device receives data from one of a plurality of input lines, a plurality of output lines, and the input line. The ATM cell is
Switching means for switching and transferring to any one of the output lines based on the header information of the TM cell; detecting the last cell of the burst data and identifying the first cell of the next burst data; When another burst data passing through the line and the next burst data compete with each other, input of a plurality of cells to which the next burst data received by the input line belongs to the switching means is stopped, and the next burst data is stopped. An ATM communication apparatus, comprising: switching means for performing discard control of a plurality of received cells including a head cell belonging to burst data. 6. An ATM communication apparatus for processing an ATM cell including burst data composed of a plurality of ATM cells, the ATM communication apparatus comprising: a plurality of input lines; a plurality of output lines; The ATM cell is
Switching means for switching and transferring to any one of the output lines based on the header information of the TM cell; detecting the last cell of the burst data and identifying the first cell of the next burst data; When another burst data passing through the line and the next burst data compete with each other, it is determined whether the next burst data is passed or discarded, and based on the determination, the next burst data received by the input line belongs. An ATM communication apparatus, comprising: switching means for controlling writing of a plurality of cells to the buffer memory or discarding of a plurality of reception cells including a head cell belonging to the next burst data. 7. An ATM communication device for processing an ATM cell including burst data composed of a plurality of ATM cells, the ATM communication device comprising: a plurality of input lines; a plurality of output lines; The ATM cell is
Switching means for switching and transferring to any one of the output lines based on the header information of the TM cell; detecting the last cell of the burst data and identifying the first cell of the next burst data; When the next burst data conflicts with the ATM cell string passing through the line, the input of the plurality of cells to which the next burst data received by the input line belongs is stopped and the next burst is received. An ATM communication apparatus, comprising: switching means for performing discard control of a plurality of received cells including a head cell belonging to data. 8. An ATM communication device for processing an ATM cell including burst data composed of a plurality of ATM cells, wherein the ATM communication device receives data from one of a plurality of input lines, a plurality of output lines, and the input line. The ATM cell is
Switching means for switching and transferring to any one of the output lines based on the header information of the TM cell; detecting the last cell of the burst data and identifying the first cell of the next burst data; If the next burst data conflicts with the ATM cell train passing through the line, the next burst data is determined to be passed or discarded. And an exchange means for controlling writing of the cell into the buffer memory or discarding of a plurality of reception cells including a head cell belonging to the next burst data. 9. The burst data is burst data transmitted / received in accordance with a communication procedure specified by the type 5 of the ATM adaptation layer, detects a boundary based on an end indication given to the burst data, and is inputted next. 9. The ATM communication apparatus according to claim 1, wherein a cell is recognized as the head of the next burst data, and the determination of the contention and the ATM cell control of the burst data are executed.