JP3043332B2 - Receiving machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a receiver, and more particularly to a two-phase, four-phase, and eight-phase PSK in a hierarchical transmission system or the like.
The present invention relates to a receiver for demodulating a PSK modulated signal in which a digital signal modulated by a modulation method is time-multiplexed by using a carrier reproduced by a carrier reproducing means and outputting I and Q symbol stream data.

[0002]

2. Description of the Related Art A plurality of modulation schemes that require different C / N, such as 8PSK modulated wave, QPSK modulated wave, BP
A digital satellite T based on a hierarchical transmission system in which SK modulated waves are time-multiplexed and repeatedly transmitted for each frame.
Practical use of V broadcasting is in progress.

FIG. 1A is an explanatory diagram showing an example of a frame configuration in a hierarchical transmission system. One frame is BP
A SK-modulated frame synchronization signal pattern consisting of 32 symbols (the latter 20 symbols are actually used as the frame synchronization signal in 32 symbols), and a TPSK-modulated T symbol for identifying a transmission multiplex configuration consisting of 128 symbols.
MCC (Transmission and Multiplexing Configuration)
n Control) pattern, a superframe identification signal pattern consisting of 32 symbols (the latter 20 symbols are actually used as a superframe identification signal in 32 symbols), 8PSK (trellis codec 8PSK) modulated main signal of 203 symbols, A 4-symbol burst symbol signal (BS) in which a pseudo-random noise (PN) signal is BPSK-modulated, a 203-symbol main signal in which 8PSK (trellis codec 8PSK) is modulated, and a 4-symbol in which a pseudo-random noise (PN) signal is BPSK-modulated Symbol burst symbol signal (BS),..., QPS
A K-modulated 203-symbol main signal, a 4-symbol burst symbol signal (BS) in which a pseudo-random noise (PN) signal is BPSK-modulated, and a QPSK-modulated 203
The symbol is composed of a main signal and a BPSK-modulated burst symbol signal (BS) of four symbols.

[0004] In a receiver for receiving a digital modulated wave (PSK modulated wave) by the hierarchical transmission system, an intermediate frequency signal of a received signal received by a receiving circuit is demodulated by a demodulating circuit, and I signals having orthogonal relations to each other. Two series of I and Q baseband signals (hereinafter, I and Q baseband signals are also referred to as I and Q symbol stream data) representing instantaneous values for each symbol on the axis and the Q axis are obtained. The frame synchronization signal is captured from the demodulated I and Q baseband signals, the current received signal phase rotation angle is obtained from the signal point arrangement of the captured frame synchronization signal, and demodulated based on the obtained received signal phase rotation angle. By rotating the I and Q base band signals in opposite phases, an absolute phase conversion circuit that performs absolute phase matching to the transmission signal phase angle is performed.

As shown in FIG. 13, an absolute phase shift circuit of a receiver for receiving a PSK modulated wave according to the conventional hierarchical transmission method is provided at an output side of a demodulation circuit 1 to capture a frame synchronization signal. It comprises a frame synchronization detecting / reproducing circuit 2 as a synchronizing signal capturing means, a remapper 7 as an anti-phase rotating means comprising a ROM, and a received signal phase rotation angle detecting circuit 8 as a received signal phase rotating angle detecting means. Reference numeral 9 denotes a transmission multiplex configuration identification circuit for identifying the transmission multiplex configuration shown in FIG. 12A, and outputs a 2-bit modulation scheme identification signal DM.

The demodulation circuit 1 performs quadrature detection on the intermediate frequency signal to obtain I and Q baseband signals. 10 of the demodulation circuits 1
Is a carrier recovery circuit, and two reference carriers f _C1 (= cos ωt) and f _C2 (= sin ωt) whose frequency and phase are synchronized with the reception carrier and whose phases are shifted from each other by 90 ° and are orthogonal to each other.
To play. 60 and 61 are intermediate frequency signals IF and f _C1 , f
Multipliers for multiplying _C2 , 62 and 63 output the outputs of the multipliers 60 and 61 to A at a sampling rate twice the symbol rate.
A / D converters for performing A / D conversion, 64 and 65 are digital filters for performing band limitation on the outputs of A / D converters 62 and 63 by digital signal processing, and 66 and 67 are for the outputs of digital filters 64 and 65 to be 1 / 2 sampling rate, and outputs two sequences of I and Q baseband signals (I and Q symbol stream data) representing instantaneous values for each symbol on the I and Q axes. The decimation circuits 66 and 67 have I and Q baseband signals I (8) and Q (8) of 8 bits (two's complement system) (the numbers in parentheses indicate the number of quantization bits. Omitting the number of bits
I, Q).

[0007] Here, mapping for each modulation scheme on the transmission side will be described with reference to FIG. FIG.
(1) shows a signal point arrangement on an IQ phase plane (also referred to as an IQ vector plane or an IQ signal space diagram) when 8PSK is used as a modulation scheme. In the 8PSK modulation method, a 3-bit digital signal (abc) can be transmitted by one symbol, and the combination of bits forming one symbol is (000), (001), (010), (01).
1), (100), (101), (110), (11)
There are 8 types of 1). These 3-bit digital signals are converted into signal point arrangements “0” to “7” on the transmission-side IQ phase plane in FIG. 14A, and this conversion is called 8PSK mapping.

In the example shown in FIG. 14A, the bit string (00
0) to the signal point arrangement “0”, the bit string (001) to the signal point arrangement “1”, the bit string (011) to the signal point arrangement “2”, the bit string (010) to the signal point arrangement “3”,
The bit string (100) is assigned to the signal point arrangement “4”, the bit string (101) is assigned to the signal point arrangement “5”, and the bit string (111) is assigned.
Is converted into a signal point arrangement “6”, and the bit string (110) is converted into a signal point arrangement “7”.

FIG. 14B shows a signal point arrangement on the IQ phase plane when QPSK is used as a modulation method.
In the modulation method, a 2-bit digital signal (de) can be transmitted by one symbol, and there are four combinations of bits constituting the symbol: (00), (01), (10), and (11). In the example of FIG. 14B, for example, the bit string (00) is assigned to the signal point arrangement “1”, the bit string (01) is assigned to the signal point arrangement “3”, the bit string (11) is assigned to the signal point arrangement “5”, and the bit string ( 10) is converted to a signal point arrangement “7”.

FIG. 14 (3) shows a signal point arrangement when BPSK is used as a modulation method. In the BPSK modulation method, a 1-bit digital signal (f) is transmitted by one symbol.
In the digital signal (f), for example, bit (0) is converted into a signal point arrangement "0" and bit (1) is converted into a signal point arrangement "4". Note that the relationship between the signal point constellation and the constellation number for each modulation scheme is the same as that between the signal point constellation and the constellation number based on 8 BPSK. QPS in hierarchical transmission system
The I axis and Q axis of K and BPSK coincide with the I axis and Q axis of 8PSK.

If the phase of the received carrier wave and the phases of the reference carrier waves f _C1 and f _C2 reproduced by the carrier wave reproduction circuit 10 match, the signal point arrangement “0” to “0” on the IQ phase plane on the transmission side is obtained.
When the digital signal corresponding to “7” is received, the phase of the received signal point on the IQ phase plane by the I and Q baseband signals I (8) and Q (8) on the receiving side matches the transmitting side. I do. Therefore, the received digital signal can be correctly identified from the signal point arrangement of the reception signal points, using the correspondence between the signal point arrangement and the digital signal on the transmission side (see FIG. 14) as it is.

However, actually, the reference carrier f _C1 , f _C2
Can assume various phase states with respect to the received carrier,
The reception signal point on the reception side has a phase position rotated by a certain angle θ with respect to the transmission side. Then, if the phase of the received carrier changes, θ also changes. If the phase of the received signal point rotates at random with respect to the transmitting side, the received digital signal cannot be identified. For example, when θ = π / 8, 8
The digital signal (000) having the signal point arrangement "0" in the PSK modulation method is received at the signal point arrangement "0" because the reception signal point is located at the center of the signal point arrangements "0" and "1" on the receiving side. If it is assumed that the digital signal (000) has been received correctly, it is mistaken that the digital signal (001) has been received if it is assumed that the digital signal (001) has been received at the signal point arrangement "1". Therefore, the carrier recovery circuit 10 controls the reference carrier f so that the reception signal point keeps a certain rotation angle with respect to the transmission side.
The phases of _C1 and _fC2 are corrected so that digital signals can be correctly identified.

More specifically, the VCO of the carrier recovery circuit 10
A reference carrier f _C1 is created by oscillating a (voltage-controlled oscillator) 11 at the transmission carrier frequency, and a reference carrier f _C2 is created by delaying the phase of the oscillation signal of the VCO 11 by 90 ° by the 90 ° phase shifter 12. Then, by varying the control voltage of the VCO 11, the phases of the reference carrier waves f _C1 and f _C2 can be varied.

The carrier recovery circuit 10 has 8PSK, QP
For each modulation scheme of SK and BPSK, various data sets of I and Q baseband signals I (8) and Q (8) and carrier phase error data (hereinafter referred to as 8 bits (2's complement)) of quantization bits are used. , Which are also simply referred to as phase error data). The phase error tables 13, 14-1 and 14-2, 15-1 to 15-1 each configured by a ROM, in which the correspondence relation of Δφ (8) is tabulated.
5-4 are provided (see FIG. 15). The I and Q baseband signals I (8) and Q (8) are input in parallel to the respective phase error tables 13, 14-1 and 14-2, 15-1 to 15-4. The phase error table selectively enabled by the selector described later outputs phase error data Δφ (8) corresponding to the I and Q baseband signals I (8) and Q (8) input from the demodulation circuit 1. It has become.

The phase error table 13 is for 8PSK, and is displayed on the IQ phase plane of the received signal points indicated by the I and Q baseband signals I (8) and Q (8) in symbol units input from the demodulation circuit 1. The relationship between the phase angle φ (see FIG. 16) and the phase error data Δφ (8) is configured as shown in FIG. 18 (in FIG. 18, + FS / 2 corresponds to a phase error of + 2π / 4 and − FS / 2 corresponds to a phase error of -2π / 4). The selector 16 is a symbol-rate clock CLK _SYB synchronized with the output of the I and Q baseband signals I (8) and Q (8) from the demodulation circuit 1 (see FIG. 12 (2)).
Accordingly, while the demodulation circuit 1 is demodulating the digital modulated wave by the BPSK modulation method (specified by the modulation method identification signal DM from the transmission multiplex configuration identification circuit 9 described later), only the phase error table 13 is enabled ( Active), and each time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol,
(8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read.

The phase error data Δφ (8) is converted into a phase error voltage by a D / A converter 17 and then converted to a LPF 18
, A low-frequency component is extracted and applied to the VCO 11 as a control voltage. If the phase error data Δφ (8) is 0,
The output of the LPF 18 does not change, and the phases of the reference carriers f _C1 and f _c2 do not change. However, if the phase error data Δφ (8) is +, the output of the LPF 18 increases, and the phases of the reference carriers f _C1 and f _c2 increase. Is delayed, and conversely, the phase error data Δφ
(8) - the output of the LPF18 is reduced if the phase of the reference carrier f _C1, f _c2 is advanced.

In the phase error table 13, the modulation method is 8
In the case of PSK, I, Q baseband signals I (8), Q
The phase angle φ of the reception signal point indicated by (8) and the nearest signal point arrangement “0” to “7” that is the target phase convergence angle of the reception signal point
Is the phase error data Δφ (8). Incidentally, in FIG. 16, the received signal points have the IQ phase planes respectively having phases 0 and π / π of signal point arrangements “0” to “7”.
4, 2π / 4, 3π / 4, 4π / 4, 5π / 4, 6π /
A region DR ₀ divided into eight so that 4, 7π / 4 is the center.
If entered one certain region DR _i of the ~DR _7,
The target phase convergence angle of the received signal point by correcting the phases of the reference carriers f _C1 and f _C2 is i · (π / 4).

Therefore, the phases 0, π / 4, 2π / 4, 3π / 4, 4π / 4, 5π in the 8PSK modulation system on the transmitting side are obtained.
/ 4, 6π / 4, and 7π / 4 signal points are respectively arranged on the receiving-side IQ phase plane as Θ = m × π / 4.
(However, m is a certain integer from 0 to 7; see FIG. 17). Θ is the reception signal phase rotation angle (the reception signal phase rotation angle is the same as that of 8PSK in QPSK and BPSK). With this, 8PS
The received signal points of the K modulation method have phases 0, π / 4, 2π / 4,
Since they come at 3π / 4, 4π / 4, 5π / 4, 6π / 4, and 7π / 4, the signal point arrangement “0” to “7” on the IQ phase plane on the receiving side is transmitted. (However, the correspondence between the signal point arrangement and the digital signal changes according to Θ). If Θ is detected and the phase is rotated by −Θ in the opposite direction, the correspondence between the signal point arrangement and the digital signal can be made the same as that on the transmitting side (absolute phase conversion), and the received digital signal can be easily identified.

The phase error tables 14-1 and 14-2 have Q
For the PSK, the phase angle φ on the IQ phase plane of the received signal points indicated by the I and Q baseband signals I (8) and Q (8) in symbol units and the phase error data Δφ (8) The relationship is configured as shown in FIGS. 19 and 20 (FIGS. 19 and 20).
, + FS / 2 corresponds to a phase error of + 2π / 4, and −FS / 2 corresponds to a phase error of −2π / 4).
At the time of normal reception, the selector 16 _adjusts the received signal phase rotation angle ０ to 0, 2π / 4, 4π / 4 while the demodulation circuit 1 demodulates the digital modulated wave by the QPSK modulation method according to the symbol rate clock CLK _SYB. , 6π / 4,
Only the phase error table 14-1 is enabled, and the demodulation circuit 1 outputs the I and Q baseband signals I for one symbol.
Each time (8) and Q (8) are output, the I (8) and Q (8)
Phase error data Δφ (8) corresponding to the set data of (8)
From the phase error table 14-1 (see FIG. 19).

The phase error table 14-1 shows that the modulation method is QPSK and the received signal phase rotation angle Θ is 0, 2π / 4, 4
Used in the case of either π / 4 or 6π / 4,
The phase angles φ of the received signal points indicated by the I and Q baseband signals I (8) and Q (8), and the nearest signal point arrangements “1”, “3”, and “3” that are the target phase convergence angles of the received signal points. 5 "," 7 "
Is the phase error data Δφ. Incidentally, as shown in FIG. 21A, the received signal points occupy the IQ phase planes, respectively, and the signal point arrangements “1”, “3”, “5”, “7”
Phase π / 4,3π / 4,5π / 4,7π / 4 is out of the area ER ₀ to Er ₃ were divided into four so that the center region E
R _i , the target phase convergence angle is i · (2π /
4) + π / 4.

Therefore, the signal point constellations "1", "3", "5", and "7" of the phases π / 4, 3π / 4, 5π / 4, and 7π / 4 in the QPSK modulation method on the transmitting side are obtained. Each of the digital signals is corrected to a position rotated by Θ on the IQ phase plane of the receiving side. Θ = 0, 2π / 4, 4π / 4, 6
In the case of π / 4, the received signal point of the QPSK modulation
/ 4, 3π / 4, 5π / 4, 7π / 4. If Θ is detected and the phase is rotated by −Θ in the opposite direction, the correspondence between the signal point arrangement and the digital signal can be made the same as that on the transmitting side (absolute phase conversion), and the received digital signal can be easily identified.

The selector 16 determines whether the demodulation circuit 10
While demodulating a digital modulated wave by the SK modulation method, if Θ = π / 4, 3π / 4, 5π / 4, 7π / 4, only the phase error table 14-2 is enabled,
The demodulation circuit 1 outputs the I and Q baseband signals I for one symbol.
Each time (8) and Q (8) are output, the I (8) and Q (8)
Phase error data Δφ (8) corresponding to the set data of (8)
From the phase error table 14-2 (see FIG. 20).

The phase error table 14-2 shows that the modulation method is QPSK and the received signal phase rotation angle Θ is π / 4, 3π /
4, 5π / 4, or 7π / 4, and is used to determine the phase angle φ of the received signal point indicated by the I and Q baseband signals I (8) and Q (8), The nearest signal point constellation “0”, “2”, “4”, which is the target phase convergence angle,
The difference from the phase of “6” is the phase error data Δφ. Incidentally, as shown in FIG. 21 (2), the reception signal point is I
−Q phase planes are respectively assigned signal point arrangements “0”, “2”,
“4”, “6” phase 0, 2π / 4, 4π / 4, 6π /
If the region FR _{i is} included in the region FR _i among the regions FR _{0 to} FR ₃ divided into four so that the center is 4, the target phase convergence angle is i ·
(2π / 4).

Therefore, the signal point constellations "1", "3", "5", and "7" of the phases π / 4, 3π / 4, 5π / 4, and 7π / 4 in the QPSK modulation method on the transmission side are obtained. Each of the digital signals is corrected to the position rotated by Θ in the IQ phase plane on the receiving side. Θ = π / 4, 3π / 4, 5π / 4,
In the case of 7π / 4, the received signal point of the QPSK modulation method comes at the phase 0, 2π / 4, 4π / 4, 6π / 4. If Θ is detected and the phase is rotated by -Θ, the phase can be made the same as that of the transmitting side (absolute phase conversion), and the correspondence between the signal point arrangement and the digital signal can be made the same as that of the transmitting side. Can be identified.

The phase error tables 15-1 to 15-4 are B
For PSK, I and Q baseband signals I (8), Q
The phase angle φ on the IQ phase plane of the received signal point shown in (8)
And the phase error data Δφ (8) are shown in FIGS.
(+ F in FIGS. 22 to 25)
S / 2 corresponds to a phase error of + 2π / 4, and −FS / 2 corresponds to a phase error of −2π / 4). The selector 16 synchronizes with the symbol rate clock CLK _SYB , and while the demodulation circuit 1 is demodulating the digital modulated wave by the BPSK modulation method, the received signal phase rotation angle に よ る by correcting the phase of the 8PSK modulation portion is 0, 4π. In the case of / 4, only the phase error table 15-1 is enabled, and the demodulation circuit 1 outputs the I and Q baseband signals I (8) and Q (8) for one symbol.
Is output, the phase error data Δφ (8) corresponding to the set data of I (8) and Q (8) is stored in the phase error table 1.
Read from 5-1 (see FIG. 22).

The phase error table 15-1 is used when the modulation method is BPSK and the received signal phase rotation angle Θ is either 0 or 4π / 4, and the I and Q baseband signals I (8) , Q (8), the phase angle φ of the received signal point,
The difference between the phase of the nearest signal point arrangement “0” and “4” that is the target phase convergence angle of the received signal point is the phase error data Δφ. By the way, as shown in FIG. 26 (1), the reception signal point is divided into two parts such that the IQ phase plane is divided into two so that the phases 0 and 4π / 4 of the signal point arrangement “0” and “4” are centered. G
Of R _0, GR _1, if entered in the area GR _i, the target phase convergent angle is i · (4π / 4). Therefore, the digital signals having the signal point constellations “0” and “4” of the phases 0 and 4π / 4 in the BPSK modulation method on the transmitting side are respectively converted to the I signals on the receiving side.
The position is corrected to the position rotated by Θ in the −Q phase plane. Θ
In the case of = 0, 4π / 4, the received signal point of the BPSK modulation method comes to the phase 0, 4π / 4.

Further, while demodulating the digital modulated wave by the BPSK modulation method, the selector 16 outputs Θ = π /
In the case of 4, 5π / 4, only the phase error table 15-2 is enabled, and each time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-2 (see FIG. 23).

The phase error table 15-2 indicates that the modulation method is B
The PSK is used when the received signal phase rotation angle π is either π / 4 or 5π / 4, and the phase of the received signal point indicated by the I and Q baseband signals I (8) and Q (8). Angle φ
And the phase of the nearest signal point constellation “1” or “5” that is the target phase convergence angle of the received signal point is the phase error data Δφ
It has become. Incidentally, as shown in FIG. 26 (2), the received signal point divides the IQ phase plane into two such that the phases π / 4 and 7π / 4 of the signal point arrangements “1” and “5” are centered. The target phase convergence angle is i · (4π / 4) + π / 4 if it falls within the region HR _i among the regions HR ₀ and HR ₁ . Therefore, the phase 0 in the BPSK modulation method on the transmission side,
The 4π / 4 signal point constellation “0” and the digital signal of “4” are respectively corrected to the positions rotated by で on the IQ phase plane on the receiving side. If Θ = π / 4, 5π / 4, BP
The reception signal point of the SK modulation method comes at the phase of π / 4, 5π / 4.

Further, while demodulating the digital modulated wave by the BPSK modulation method, the selector 16 outputs Θ = 2π /
In the case of 4, 6π / 4, only the phase error table 15-3 is enabled, and each time the demodulation circuit 1 outputs the I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-3 (see FIG. 24).

The phase error table 15-3 shows that the modulation method is BPSK and the received signal phase rotation angle Θ is 2π / 4 and 6π /
4, the phase angle φ of the received signal point indicated by the I and Q baseband signals I (8) and Q (8), and the nearest target phase convergence angle of the received signal point. The difference between the signal point arrangements “2” and “6” is the phase error data Δ
φ. By the way, as shown in FIG. 26 (3), the received signal points are arranged on the IQ phase plane such that the phases 2π / 4 and 6π / 4 of the signal point arrangements “2” and “6” are centered.
Divided regions IR _0, of the IR _1, if it enters a region IR _i, the target phase convergent angle i · (4π / 4) + 2π / 4
It is. Therefore, the digital signals of the signal point constellation “0” and “4” of the phase 0 and 4π / 4 in the BPSK modulation method on the transmitting side are respectively rotated by the angle Θ on the IQ phase plane on the receiving side. Will be modified to When Θ = 2π / 4, 6π / 4, the received signal point of the BPSK modulation method has a phase of 2π / 4, 6π / 4.
Comes at π / 4.

Further, while demodulating the digital modulated wave by the BPSK modulation method, the selector 16 outputs Θ = 3π /
In the case of 4, 7π / 4, only the phase error table 15-4 is enabled, and every time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-4 (see FIG. 25).

The phase error table 15-4 shows that the modulation method is BPSK and the received signal phase rotation angle Θ is 3π / 4 and 7π /
4, the phase angle φ of the received signal point indicated by the I and Q baseband signals I (8) and Q (8), and the nearest target phase convergence angle of the received signal point. The difference between the signal point arrangements “3” and “7” is the phase error data Δ
φ. By the way, as shown in FIG. 26 (4), the received signal points are arranged on the IQ phase plane so that the phases 3π / 4 and 7π / 4 of the signal point arrangements “3” and “7” are centered.
If the divided areas JR ₀ and JR ₁ fall within the area JR _i , the target phase convergence angle is i · (4π / 4) + 3π / 4.
It is. Therefore, the digital signals of the signal point constellation “0” and “4” of the phase 0 and 4π / 4 in the BPSK modulation method on the transmitting side are respectively rotated by the angle Θ on the IQ phase plane on the receiving side. Will be modified to When Θ = 3π / 4, 7π / 4, the received signal point of the BPSK modulation method has a phase of 3π / 4, 7
Comes at π / 4. In the case of BPSK modulation as well, if 検 出 is detected and the phase is rotated in the opposite direction by − 位相, the phase can be made the same as that of the transmitting side (absolute phase conversion), and the correspondence between the signal point arrangement and the digital signal can be made the same as that of the transmitting side. The received digital signal can be easily identified.

On the other hand, as shown in FIG. 27, the frame synchronization detection / reproduction circuit 2 includes a BPSK demapper unit 3, synchronization detection circuits 40 to 47, a frame synchronization circuit 5, and an OR gate circuit 5.
3. It comprises a frame synchronization signal generator 6. As shown in FIG. 13, the reception signal phase rotation angle detection circuit 8 includes delay circuits 81 and 82, a 0 ° / 180 ° phase rotation circuit 83,
It is composed of averaging circuits 84 and 85 and a reception phase judgment circuit 86.

The I and Q baseband signals I (8) and Q (8) output from the demodulation circuit 1 are used, for example, to capture a BPSK-modulated frame synchronization signal. 3 and BP
The SK demapped bit stream B0 is output. The BPSK demapper unit 3 is constituted by, for example, a ROM.

Next, the frame synchronization signal will be described.
In the hierarchical transmission method, the frame synchronization signal is transmitted after being subjected to BPSK modulation requiring the lowest C / N. The bit stream of the frame synchronization signal composed of 20 bits is (S0S1... S18S19) = (11101)
100110100101000), and are sequentially transmitted from S0. Hereinafter, the bit stream of the frame synchronization signal is also referred to as “SYNCPAT”. This bit stream is converted to a signal point arrangement “0” or “4” by the BPSK mapping shown in FIG. 14 (3) on the transmission side, and the converted symbol stream is transmitted.

In order to capture a frame synchronization signal of 20 bits, that is, 20 symbols transmitted by BPSK modulation, contrary to the mapping converted on the transmission side,
It is necessary to convert received symbols into bits by the BPSK demapping shown in FIG. Therefore, as shown in FIG. 28A, when the demodulated signal is received in the hatched area on the IQ phase plane on the receiving side (0), and when the demodulated signal is received in the portion without the hatched ( 1) is determined. That is, the output is set to (0) or (1) depending on which of the two determination areas divided by the BPSK determination boundary indicated by the thick line in FIG. 28 (1) has been received, and thereby BPSK demapping is performed.

I, Q Baseband signals I (8), Q
(8) is BPSK demapping to perform BPSK demapping.
The bit stream B0 input to the K demapper 3 and subjected to BPSK demapping in the BPSK demapper 3
Is output. In this specification, a demapper refers to a circuit that performs demapping. The bit stream B0 is input to the synchronization detection circuit 40, and the synchronization detection circuit 40 captures a bit stream of a frame synchronization signal from the bit stream B0.

Next, the synchronization detecting circuit 40 will be described with reference to FIG. The synchronization detection circuit 40 is connected in series
It has zero D-flip-flops (hereinafter referred to as DF / F) D19 to D0, and these DF / FD19 to D0 constitute a 20-stage shift register. The bit stream B0 is input to the DF / FD19, and sequentially,
Shifted up to DF / FD0 and simultaneously DF
The parallel outputs from / FD19 to / D0 are input to the AND gate 51 after logical inversion is performed on a predetermined bit position. In the AND gate 51, the output states (D0D1... D18D19) of DF / FD19 to D0 are (111011001).
10100101000), the output SYNA0 of the AND gate 51 becomes high potential. That is, SY
When NCPAT is captured, SYNA0 becomes high potential.

The output SYNA0 of the synchronization detection circuit 40 is OR
The signal is input to the frame synchronization circuit 5 via the gate circuit 53. In the frame synchronization circuit 5, when it is confirmed that the output SYNA of the OR gate circuit 53 repeatedly becomes a high potential every fixed frame period, it is determined that the frame synchronization is established, and a frame synchronization pulse is output every frame period. You.

Normally, in a hierarchical transmission system in which a plurality of required modulation systems having different C / Ns are time-multiplexed and repeatedly transmitted for each frame, header data indicating their multiplex configuration is multiplexed. (T in FIG. 12 (1)
MCC pattern). The transmission multiplexing configuration discriminating circuit 9 determines that the frame synchronization has been achieved by the frame synchronization detecting / reproducing circuit 2 and then inputs the BPSK input from the frame synchronizing circuit 5.
TM indicating multiplex configuration from bitmap after demapper
The CC is extracted and decoded, and a modulation scheme identification signal DM indicating which modulation scheme is used for the current I and Q baseband signals I and Q is output to the selector 16 and the like (FIG. 12).
(See (2)). Also, the reception signal phase rotation angle detection circuit 8
Detects the received signal phase rotation angle Θ based on the reproduced frame synchronization signal output from the frame synchronization signal generator 6 after the frame synchronization detection / reproduction circuit 2 determines that the frame is synchronized. The bit reception signal phase rotation angle signal AR (3) is output to the remapper 7, the selector 16 of the carrier recovery circuit 10, and the like.

The selector 16 of the carrier recovery circuit 10 receives the modulation scheme identification signal DM from the transmission multiplex configuration identification circuit 9 and receives the received signal phase rotation angle signal AR (3) from the reception signal phase rotation angle detection circuit 8. After the input, the phase error data Δφ (8) is read from the phase error table corresponding to the modulation method and the received signal phase rotation angle Θ, and is output to the D / A converter 17. The phase error data Δφ (8) is read from the error table 13.

Thus, the demodulation circuit 1 always keeps 8P until the transmission multiplex configuration identifying circuit 9 identifies the multiplex configuration and the received signal phase rotation angle detection circuit 8 detects the received signal phase rotation angle Θ.
To operate as an SK demodulation circuit, the reference carrier waves f _C1 and f _C reproduced by the carrier reproduction circuit 10 in the demodulation circuit 1
Depending on the phase state of _C2, the received signal point is
The phase is rotated by m × π / 4 (m is a certain integer from 0 to 7).

That is, as shown in FIG. 14 (3), BPSK mapping is performed on the transmission side to signal point arrangement “0” for bit (0) and to signal point arrangement “4” for bit (1). The received signal point of the symbol stream of the frame synchronization signal is a signal point arrangement “0” where Θ = 0 as in the transmitting side depending on the phase state of the reference carriers f _C1 and f _C2 ,
In the case where it appears in “4”, in the case where it appears in signal point constellations “1” and “5” whose phases are rotated by Θ = π / 4, and in the case where Θ = 2π / 4
The signal point constellations "2" and "6" after phase rotation only, and the signal point constellations "3" and "7" phase shifted by Θ = 3π / 4, and Θ = 4π / 4 only The case where the phase is rotated and appears at signal point arrangements “4” and “0”;
= 5 [pi] / 4 signal point constellation "5", "1"
, 回 転 = 6π / 4 phase-rotated and appear in signal point arrangement “6”, “2”, and Θ = 7π / 4 phase-rotated in signal point arrangement “7”, “3” , There are eight different phase states of the demodulated frame synchronization signal. For this reason, it is necessary to be able to capture a frame synchronization signal that has been demodulated at any phase.

Therefore, the BPSK demapper unit 3 is
0, Θ = 0 (m = 0), Θ = π / 4 (m =
1), Θ = 2π / 4 (m = 2),..., Θ = 6π / 4
(M = 6) and BPSK demappers 30 to 37 corresponding to a phase rotation of Θ = 7π / 4 (m = 7).

FIG. 28 (2) shows that the symbol stream of the demodulated frame synchronization signal is rotated by Θ = π / 4 phase, bit (0) is in signal point arrangement “1” and bit (1) is
Shows the BPSK demapping for the case where appears in the signal point arrangement “5”. The BPSK determination boundary indicated by a bold line in FIG. 28 (2) is counterclockwise with respect to the BPSK determination boundary indicated by a bold line for BPSK demapping in FIG. Is rotated by π / 4. By using a BPSK demapper (see reference numeral 31 in FIG. 30) for performing BPSK demapping as shown in FIG. 28 (2), it is possible to stably capture a frame synchronization signal rotated by Θ = π / 4 phase. B with BPSK demapper 31
The PSK demapped bit stream is shown in FIG.
This is the output B1 of the PSK demapper unit 3.

Similarly, the BPSK demappers 32 to 37
Are 2π in the counterclockwise direction with respect to the BPSK determination boundary line indicated by the thick line for BPSK demapping in FIG.
BP rotating by / 4, 3π / 4, ..., 7π / 4
BPSK demapping at the SK determination boundary line, Θ = 2π /
A frame synchronization signal whose phase is rotated by 4, 3π / 4,..., 7π / 4 is stably captured. BPSK demapper 32
The bit streams subjected to BPSK demapping by .about.37 are the outputs B2 to B7 of the BPSK demapper unit 3 in FIG. The BPSK demapper 30 performs BPSK demapping at the BPSK determination boundary indicated by the thick line of the BPSK demapping in FIG. 28A, and stably captures a frame synchronization signal of Θ = 0. BPSK with BPSK demapper 30
The demapped bit stream is BPSK of FIG.
This is the output B0 of the demapper unit 3.

The circuit configuration of the synchronization detection circuits 41 to 47 is the same as that of the synchronization detection circuit 40. By providing such synchronization detection circuits 40 to 47, the demodulation circuit 1
Irrespective of the phase rotation of the baseband signal due to the phase state of the reference carrier waves f _C1 and f _C2 reproduced by the carrier reproduction circuit 10 in any one of the synchronization detection circuits 40 to
At 47, the frame synchronization signal is captured, and a high-potential SYNAn
(N is an integer from 0 to 7) is transmitted.

S output from the synchronization detection circuits 40 to 47
YNAn is input to the OR gate circuit 53, and the OR gate circuit 53 outputs the logical sum SYNA of SYNAn. When it is confirmed that the high potential of the SYNA is alternately and repeatedly input at regular frame intervals, the frame synchronization circuit 5 determines that frame synchronization is established, and outputs a frame synchronization pulse FSYNC at each frame period. .
According to the frame synchronization pulse FSYNC output from the frame synchronization circuit 5, the frame synchronization signal generator 6
The pattern S of the frame synchronization signal captured by the SK demapper unit 3, the synchronization detection circuits 40 to 47, and the frame synchronization circuit 5.
It generates the same bit stream as YNCPAT (this is called a playback frame synchronization signal).

A frame synchronization signal is captured from the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1 by the frame synchronization detection / reproduction circuit 2 shown in FIG. The process until the reproduction frame synchronization signal is output from the frame synchronization signal generator 6 has been described.

Next, the operation of the transmission multiplex configuration identifying circuit 9 will be described. The transmission multiplex configuration identification circuit 9 includes bit streams B0 to B7 output from the BPSK demapper unit 3 of the frame synchronization detection / reproduction circuit 2, SYNA0 to SYNA7 output from the synchronization detection circuits 40 to 47, and a frame output from the frame synchronization circuit 5. Synchronous pulse FSY
NC has been entered. Then, the frame synchronization pulse FS
When YNC is input, the bit stream Bn of the system that repeatedly becomes high potential among SYNA0 to SYNA7
12A, and using a predetermined timing signal generated from the frame synchronization pulse FSYNC, the TM of FIG.
The CC pattern is extracted and decoded, and a modulation scheme identification signal DM indicating what modulation scheme the current I and Q baseband signals I and Q use is output (see FIG. 12 (2)).

Next, the present received signal phase rotation angle is obtained from the signal point arrangement of the captured frame synchronization signal, and the demodulated I and Q baseband signals I (8 ) And Q (8) will be described in terms of absolute phase conversion by rotating them in opposite phases. Each symbol of the symbol stream of the frame synchronization signal, which is BPSK-mapped and transmitted on the transmission side and demodulated into I and Q baseband signals I (8) and Q (8) by the demodulation circuit 1, is converted by the BPSK demapper unit 3 The symbol is demapped to bit (0) or (1). The phase difference between the symbol demapped to bit (0) and the symbol demapped to (1) is 180 °. Therefore, the symbol stream demapped to bit (0) can be obtained by rotating the symbol demapped to bit (1) of the frame synchronization signal portion of the received symbol stream by 180 °.

Further, by determining the average value over a plurality of symbols of the symbol stream demapped to all the bits (0), the reception signal point arrangement for the BPSK bit (0) is obtained. Therefore, the received signal point for bit (0) of the determined BPSK,
The transmitting side obtains a phase difference from the signal point arrangement “0” mapped to bit (0), and calculates this as the received signal phase rotation angle Θ.
And η = −
By performing the phase rotation of Θ, the I and Q baseband signals I (8) and Q (8) can be made to have an absolute phase.

As described above, upon receiving the frame synchronization pulse output from the frame synchronization circuit 5, the frame synchronization signal generator 6 generates the pattern S of the captured frame synchronization signal.
The same bit stream as that of YNCPAT is generated and supplied to a 0 ° / 180 ° phase rotation circuit 83 in the reception signal phase rotation angle detection circuit 8 as a reproduced frame synchronization signal. 0
The {/ 180} phase rotation circuit 83 converts the I and Q baseband signals in the case of (1) based on the bit (0) or (1) in the bit stream of the supplied reproduced frame synchronization signal. The phase is rotated by 180 °, and in the case of (0), the phase is not rotated.

The timing between the bit stream of the reproduced frame synchronization signal sent from the frame synchronization signal generator 6 and the symbol stream of the frame synchronization signal in the I and Q symbol streams is 0 ° / 180 ° by the delay circuits 81 and 82. The phase is matched on the input side of the phase rotation circuit 83. Since the delay circuits 81 and 82 open their output gates only while the frame synchronization signal section signal is being output from the frame synchronization signal generator 6, the delay circuit 8
From I and 82, I and Q symbol streams DI (8) and DQ (8) of the frame synchronization signal portion are output. These I and Q symbol streams DI (8) and DQ (8)
The symbol portion corresponding to bit (1) in the bit stream of the reproduced frame synchronization signal is rotated by 180 ° in the 0 ° / 180 ° phase rotation circuit 83, and the symbol portion corresponding to bit (0) is not phase-rotated. , Symbol streams VI (8) and VQ (8) to the averaging circuits 84 and 85. The symbol streams VI (8) and VQ (8) are symbol streams when a BPSK-mapped signal is received on the transmission side on the assumption that all 20 bits forming the frame synchronization signal are bits (0).

FIG. 31A shows the received signal phase rotation angle Θ = 0.
FIG. 31 (2) shows the signal point arrangement of the I and Q symbol streams I (8) and Q (8) of the frame synchronization signal when the signal is received in FIG.
3, the I and Q symbol streams V converted
The signal point arrangement of I (8) and VQ (8) is shown. I and Q symbol streams VI (8), VQ (8)
Are sent to averaging circuits 84 and 85, respectively.
After the quantization bit length is converted to about 16 to 18 bits, four frames (20 × 4 = 80 symbols) are averaged, and the averaged value is based on the original 8-bit quantization bit length. Output as AVI (8) and AVQ (8). Here, the I and Q symbol streams VI (8), V
The averaging is performed on Q (8) so that the signal point arrangement can be stably obtained even when a small phase change or amplitude change of the received baseband signal occurs due to deterioration of the received C / N. To do that.

The received signal point [A of the signal in which the bit (0) is BPSK-mapped by the averaging circuits 84 and 85 [A
VI (8), AVQ (8)]. Next, the reception signal points [AVI (8), AVQ (8)] are input to the reception phase judgment circuit 86 composed of a ROM, and the signals A shown in FIG.
The received signal phase rotation angle Θ is obtained according to the received signal phase rotation angle determination table on the VI-AVQ phase plane, and a 3-bit (natural binary) phase rotation angle signal AR corresponding to Θ is obtained.
(3) is output. In FIG. 32, R = 0 to 7 indicate decimal numbers of the phase rotation angle signal AR (3). For example, the point Z = [AVI (8), AVQ shown in FIG.
(8)], the received signal phase rotation angle determined by the received signal phase rotation angle determination table is Θ = 0. Therefore, R = 0, and the received signal phase rotation angle signal AR
(000) is transmitted as (3). If the received signal phase rotation angle π is π / 4, R = 1, and (001) is transmitted as the received signal phase rotation angle signal AR (3).

The remapper 7 composed of a ROM receives the received signal phase rotation angle signal AR (3) and converts the I and Q baseband signals I (8) and Q (8) to the received signal phase rotation angle signal A (3).
By rotating the phase according to R (3), absolute phase conversion is achieved. The operation of the remapper 7 will be described. The remapper 7 receives the I and Q baseband signals I (8), Q
A phase conversion circuit is configured to make the signal point arrangement of (8) the same as that on the transmission side. The reception signal phase rotation angle detection circuit 8 calculates the reception signal phase rotation angle Θ, and supplies the reception signal phase rotation angle signal AR (3) corresponding to the reception signal phase rotation angle に to the remapper 7. here,
The decimal representation R of the received signal phase rotation angle signal AR (3) is 0.
And the relationship with the received signal phase rotation angle Θ is
It is defined as shown in the following equation (1).

R = Θ / (π / 4) (1) where Θ = m · (π / 4), and m is an integer of 0 to 7. The absolute phase conversion of the I and Q baseband signals may be performed by performing a reverse rotation, that is, a phase rotation of −Θ with respect to the received signal phase rotation angle Θ. Therefore, the remapper 7 rotates the phase of the input I and Q baseband signals I and Q by the angle η (= −Θ) according to the following equations (2) and (3), and sets the absolute phase I , Q baseband signal I ′
(8), Q '(8) (hereinafter the quantization bit number is omitted and I
'And Q'). I ′ = Icos (η) −Qsin (η) (2) Q ′ = Isin (η) + Qcos (η) (3)

After the frame synchronization signal is captured by the frame synchronization detecting / reproducing circuit 2 and the frame synchronization pulse is output, the transmission multiplex configuration identifying circuit 9 identifies the transmission multiplex configuration first, and thereafter, receives the received signal. The phase rotation angle detection circuit 8 may detect the phase rotation angle of the received signal.
First, the reception signal phase rotation angle detection circuit 8 detects the reception signal phase rotation angle, and then the transmission multiplex configuration identification circuit 9 may identify the transmission multiplex configuration. Detection of the received signal phase rotation angle by the detection circuit 8 and identification of the transmission multiplex configuration by the transmission multiplex configuration identification circuit 9 can be performed simultaneously and in parallel.

[0060]

However, in the above-mentioned conventional receiver, the phase error table 1 for correcting the phases of the reference carriers f _C1 and f _C2 at the time of demodulation in the 8PSK modulation system is used.
3 and the reference carrier f _C1 , f _C
A phase error table 14-1 for correcting the phase of _C2 ,
14-2 and the reference carrier f during demodulation of the BPSK modulation method.
_C1, the phase error table 15 for correcting the phase of the f _C2
There is a problem that a total of seven -1 to 15-4 must be prepared, and the required memory capacity becomes large. An object of the present invention is to provide a receiver that requires a small circuit scale.

[0061]

According to the receiver of the present invention, 2
A PSK modulated signal obtained by time-divisionally multiplexing a digital signal modulated according to the PSK modulation scheme of four phases, four phases, and eight phases using a carrier reproduced by a carrier reproducing means, and demodulating I and Q symbol streams in symbol units. Demodulating means for outputting data, I for each symbol output from the demodulating means,
Received signal phase rotation angle detection means for detecting the phase rotation angle に 対 す る of the Q symbol stream data with respect to the transmission side, and reception signal phase rotation angle detection for the I and Q symbol stream data phases for each symbol output from the demodulation means. An anti-phase rotation unit that rotates the phase by −Θ with respect to the phase rotation angle Θ detected by the unit, converts the phase into an absolute phase, and outputs the resultant signal; In the receiver, the anti-phase rotation means rotates the phases of the I and Q symbol stream data for each symbol output from the demodulation means by two kinds of phase rotation angles in a time division manner, and outputs them. one of the inner, but are to the - [theta], whereas, carrier recovery means, after the absolute phasing in a two-phase PSK modulation schemes I, carrier phase error de to Q symbol stream data pairs A phase error table storing data, in accordance with the modulation scheme identified by the modulation type discrimination means, I
Of the received signal points indicated by the I and Q symbol stream data sets for each symbol after the absolute phase conversion based on the positive direction of the axis or the negative direction of the I axis, based on the direction included in the phase error table. The shift angle Θ ′ to the target phase convergence angle in the modulation method is obtained, and the phase rotation is performed by − (Θ + Θ ′) as the other one of the two types in which the phase is rotated in a time division manner by the anti-phase rotation means. Phase error detection processing means for detecting the phase error of the reproduced carrier by reading the carrier phase error data corresponding to the I and Q symbol stream data sets from the phase error table, and detecting the phase error data detected by the phase error detection processing means. It is characterized in that the phase of the reproduced carrier is corrected based on the carrier phase error data.

The anti-phase rotator outputs the I and Q symbol stream data obtained by rotating the phase of the I and Q symbol stream data for each symbol output from the demodulator by -Θ to make it absolutely phased. According to the modulation scheme identified by the modulation scheme identification means in a time division manner, the absolute phase after the absolute phase conversion is measured based on the positive direction of the I-axis or the negative direction of the I-axis, which is included in the phase error table. The deviation angle between the received signal point indicated by the I and Q symbol stream data sets and the target phase convergence point in the modulation scheme is Θ ′, and −
The I and Q symbol stream data when the phase is rotated by (Θ + Θ ′) is output, and using this I and Q symbol stream data set, the phase error detection processing means reads carrier wave phase error data from the phase error table, Correct the phase of the recovered carrier. The carrier phase error data read from the phase error table is the modulation method of the reception signal being demodulated by the demodulation means, the reception signal phase rotation angle with respect to the transmission side,
Since the data corresponds to the received signal points, only one phase error table is required for the carrier recovery means, and the number of phase error tables provided for the carrier recovery means can be reduced, and the circuit configuration can be greatly simplified. Becomes

[0063]

Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a main part of a broadcast receiver (PSK modulated wave receiver) according to the present invention. The same components as those in FIG. 13 are denoted by the same reference numerals. In FIG. 13, the phase error table 1 is added to the carrier recovery circuit.
3, 14-1, 14-2, and 15-1 to 15-4, and corresponds to a set of I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit. Although the phase error data is read, in FIG. 1, only one phase error table 15-1A is provided.
In addition, the phase error data corresponding to the I and Q symbol stream data sets after the absolute phase conversion by the remapper 7A is read.

The remapper 7A outputs I and Q symbol stream data I / Q in symbol units output from the demodulation circuit 1A.
(8) and Q (8) are phase-rotated by -Θ based on the received signal phase rotation angle Θ detected by the received signal phase rotation angle detection circuit 8 in a time-sharing manner to be absolute phase, and I and Q symbol streams Data RI (8) = RI ₀ (8), RQ (8)
= RQ ₀ (8) or a remapper measured counterclockwise on the IQ phase plane with respect to the positive direction of the I axis for each modulation method based on the output of a phase error detection processing circuit described later. At 7A, the phase rotation by − (Θ + Θ ′) is performed, where ず れ ′ is the shift angle of the received signal point indicated by the I and Q symbol stream data for each symbol after absolute phase conversion to the target phase convergence angle, and the I, Q symbol Stream data RI (8) =
Output as RI ₁ (8), RQ (8) = RQ ₁ (8).

As shown in FIG. 8, the demodulation circuit 1A synchronizes with the symbol clock CLK _{SYB at} time t (t =..., K
_Assuming that a new I and Q symbol stream data set {I _t (8), Q _t (8)} is output in symbol units every time CLK _SYB rises at −1, k, k + 1 _,. ｛I at the falling edge of CLK _SYB
t (8), Q _t (8)}, and I and Q symbol stream data sets {RI
_0t (8), RQ _0t (8)}, _fetch {I _t (8), Q _t (8)} at the next rising timing of CLK _SYB , and rotate I, Q symbol stream data set @RI _1t (8), RQ
_1t (8) Output｝. The former I and Q symbol stream data RI _0t (8) and RQ _0t (8) are
8,69 is latched at the rising edge of the CLK _SYB, the absolute phase of the I, Q symbol stream data _{RI (8) '= RI 0t} (8), RQ (8)' = QI
Output as _0t (8).

The phase error table 15-1A provided in the carrier recovery circuit 10A stores various I and Q symbol stream data RI (8) and RQ (8) after absolute phase conversion by the remapper 7A in the BPSK modulation method. A ROM table shows a correspondence relationship between a set (where RI (8) ≧ 0) and phase error data Δφ (8) of 8 bits (two's complement system) of quantization bits. When the I coordinate of the symbol stream data RI (8) and RQ (8) on the IQ phase plane is 0 or more (see FIG. 2), in other words, when viewed at the phase angle φ of the received signal point, 0-2 in the direction
The range of π / 4 and the range of 6π / 4 to 8π / 4 are tabulated as defined domains (see the solid line in FIG. 3.
, + FS / 2 corresponds to a phase error of + 2π / 4, and −FS / 2 corresponds to a phase error of −2π / 4).

Reference numeral 70 denotes a phase error detection processing circuit, which outputs the I and Q symbol stream data I (8) and Q (8) in symbol units output from the demodulation circuit 1A in the latter half of one cycle of the symbol clock CLK _SYB. With remapper 7A
Is the I and Q symbol stream data RI after absolute phase conversion
While outputting (8) = RI ₀ (8) and RQ (8) = RQ ₀ (8), read the RI ₀ (8), RQ ₀ (8) and the phase error table 15-1A. Phase error data Δφ (8) = Δφ corresponding to the data set of the I and Q symbol stream data RI ₀ (8) and RQ ₀ (8)
₀ (8), the high-order 3-bit data Δφ ₀ (3) and the modulation scheme identification signal D input from the transmission multiplex configuration identification circuit 9
With M, the remapper 7A measured in the counterclockwise direction on the IQ phase plane with respect to the positive direction of the I-axis after the absolute phase conversion for each modulation scheme of the received signal currently demodulated by the demodulation circuit 1A. I, Q symbol stream data RI for each symbol
₀ (8), the shift angle Θ ′ of the received signal point indicated by RQ ₀ (8) to the target phase convergence angle is obtained. And (Θ + Θ´)
And outputs it to the remapper 7A. The input I, Q symbol stream data I (8), Q in the first half of the next one cycle of CLK _SYB for the phase error detection by the remapper 7A.
I and Q obtained by phase-rotating (8) by-(Θ + Θ ′)
Symbol stream data RI ₁ (8), RQ ₁ (8)
Output. Subsequently, phase error data Δφ (8) = Δφ ₁ (8) corresponding to RI ₁ (8) and RQ ₁ (8) is read from the phase error table 15-1A, and Δφ (8) ′
And outputs it to the D / A converter 17.

For the I and Q symbol stream data RI ₀ (8) and RQ ₀ (8) after the absolute phase conversion by the remapper 7A, the reception side subjected to 8PSK mapping processing to the signal point arrangements “0” to “7” on the transmission side. The signal points respectively have phases 0, π / 4, 2π / 4, 3π / on the IQ phase plane of FIG.
4,4π / 4,5π / 4,6π / 4,7π / 4 but will enter 8 to one of the divided areas KR ₀ ~KR ₇ around the reception symbol at a certain time t = k Signal point P _k
(RI _0k , RQ _0k ) is temporarily KR _i (where i = 0 to 7)
, The target phase convergence angle of the received signal point _Pk by the phase correction operation on the reference carrier waves f _C1 and f _C2 in the carrier recovery circuit 10A is i · (π / 4).
The shift angle Θ ′ from the positive direction of the I-axis is Θ ′ = i · (π / 4). (When the shift angle Θ ′ is measured counterclockwise on the IQ phase plane based on the negative direction of the I-axis, , Θ ′ = i · (π / 4) −
π). At this time, the I and Q symbol stream data RI _{k obtained} by phase-rotating the I and Q symbol stream data I _k (8) and Q _k (8) in the opposite direction by − (Θ + 逆 ′).
_1k (8) and RQ _1k (8) are converted to the phase error table 15-1A.
Is the phase error data Δφ (8) = Δφ
_1k (8) is the RI obtained when the solid line graph in FIG.
_0k (8) and _RQ0k (8).

For example, when the deviation angle Θ ′ is measured counterclockwise with respect to the positive direction of the I axis when the reception signal point P _k is in the region KR ₂ , the graph of the solid line in FIG. The phase error data Δφ (8) corresponding to RI _0k (8) and RQ _0k (8) obtained by moving by 2π / 4 in the positive direction of FIG. Φ
= Portion of 3π / 8~5π / 8 is the same as part of φ = 3π / 8~5π / 8 corresponding to the area KR ₂ in FIG. i
Is other than 2, so that Δφ _1k (8) gives the I and Q symbol stream data I _0k (8), Q _0k after absolute phase conversion in the phase error table of FIG.
This means that the phase error data corresponding to (8) has been obtained.
I, Q symbol stream data I _0k (8), Q
_{Since 0k} (8) is absolutely phased, the received signal point P _k
Target phase convergence angle becomes the same as the signal point arrangement on the transmitting side,
Regardless of the received signal phase rotation angle Θ, the carrier phase error with respect to the received signal point P _k in the 8PSK modulation method can be correctly obtained.

In contrast, the I and Q symbol stream data RI ₀ (8), R
In Q ₀ (8), the signal point arrangement “1”, “3”,
The received signal points subjected to QPSK mapping processing to “5” and “7” respectively have phases π / 4, 3π / 4, 5π / 4, and 7π / 4 on the IQ phase plane in FIG. Although will enter the 4 one of the divided regions ER ₀ to Er ₃ around the reception signal point of a symbol at a certain time t = k P
If _k enters ER _i (where i = 0 to 3), the target phase convergence angle of the received signal point P _k by the phase correction operation on the reference carrier waves f _C1 and f _C2 in the carrier recovery circuit 10A is i · (2π / 4) + π / 4. The shift angle Θ ′ from the positive direction of the I axis is Θ ′ = i · (2π / 4) + π / 4 (the shift angle Θ ′ is counterclockwise on the IQ phase plane with respect to the negative direction of the I axis. When measuring, Θ ′ = i · (2π / 4) + π / 4
−π). At this time, the I and Q symbol stream data RI _{1k obtained} by phase-rotating the I and Q symbol stream data I _k (8) and Q _k (8) in the opposite direction by − (Θ + Θ ′).
(8), Phase error data Δφ (8) = Δφ when RQ _1k (8) is input to phase error table 15-1A
_1k (8) is the RI obtained when the solid line graph in FIG.
_0k (8) and _RQ0k (8).

For example, when the received signal point P _k is in the area ER ₀ and the deviation angle Θ ′ is measured counterclockwise with respect to the positive direction of the I axis, the table indicated by the solid line in FIG. Is moved by π / 4 in the positive direction, and the phase error data Δφ (8) corresponding to RI _0k (8) and RQ _0k (8) when replaced by the graph of FIG. 5 is obtained. Φ = 0
The portion of .about.2π / 4 corresponds to the region ER ₀ in FIG.
It is the same as the portion of 0 to 2π / 4. The same applies to the case where i is other than 0. Thus, Δφ _1k (8) indicates that the I and Q symbol stream data I _0k (8) and Q _0k (8) after the absolute phase conversion in the phase error table of FIG. This means that the corresponding phase error data has been obtained. Since the I and Q symbol stream data I _0k (8) and Q _0k (8) are absolutely phased, the target phase convergence angle of the reception signal point P _k becomes the same as the signal point arrangement on the transmission side, and the reception signal phase Regardless of the rotation angle Θ, the received signal point P in the QPSK modulation method
_The carrier phase error for _k is determined correctly.

Further, I, after the absolute phase conversion by the remapper 7A,
Q symbol stream data RI ₀ (8), RQ
_{0 In} (8), the signal point arrangement "0" and "4"
The received signal points subjected to the PSK mapping are shown in FIG.
The phase 0, 4π / 4 on the IQ phase plane of 6 (1)
Is divided into two regions GR ₀ and GR ₁ divided by the center, and the reception signal point P _k of the symbol at a certain time t = _k is temporarily GR _i (where i = 0, 1). When entering, the target phase convergence angle of the reception signal point _Pk by the phase correction operation on the reference carrier waves f _C1 and f _C2 in the carrier recovery circuit 10A is i · (4π / 4). The shift angle Θ ′ from the positive direction of the I-axis becomes Θ ′ = i · (4π / 4) (when the shift angle Θ ′ is measured counterclockwise on the IQ phase plane with reference to the negative direction of the I-axis. Θ ′ = i · (4π / 4) −π). At this time, the I and Q symbol stream data I _k (8), Q
_k (8) is phase-rotated in the opposite direction by − (） + Ｉ ′),
Q symbol stream data RI _1k (8), RQ
_1k (8) phase error data [Delta] [phi when were input to the phase error table _{15-1A (8) = Δφ 1k (} 8) is moved by Θ'amount the solid line graph in the positive direction of φ-axis in FIG. 3 This is the same as the phase error data for RI _0k (8) and RQ _0k (8) as seen in the graph.

For example, if the deviation angle Θ ′ is measured counterclockwise with respect to the positive direction of the I axis when the reception signal point P _k is in the area GR ₁ , the solid line graph of FIG. When R is moved by π in the positive direction and replaced with the graph of FIG.
Phase error data Δ corresponding to I _0k (8) and RQ _0k (8)
φ (8) is obtained, and φ = 2π / 4- in the graph of FIG.
The portion of 6π / 4 corresponds to the region GR ₁ in FIG.
It is the same as the part of π / 4 to 6π / 4. The same applies to the case where i is 0. Therefore, Δφ _1k (8) corresponds to I and Q symbol stream data I _0k (8) and Q _0k (8) after absolute phase conversion in the phase error table of FIG. That is, the obtained phase error data is obtained. Since the I and Q symbol stream data I _0k (8) and Q _0k (8) are absolutely phased, the target phase convergence angle of the reception signal point P _k becomes the same as the signal point arrangement on the transmission side, and the reception signal phase Regardless of the rotation angle Θ, the received signal point P in the BPSK modulation method
_The carrier phase error for _k is determined correctly.

FIG. 7 is a block diagram showing a specific configuration example of the phase error detection processing circuit 70, and FIG. 8 is a time chart showing the operation of the phase error detection processing circuit 70. Hereinafter, the configuration of the phase error detection processing circuit 70 will be described with reference to FIG. Note that Θ ′ is 0, π / 4, 2π / 4, 3π / 4,
Any one of 4π / 4, 5π / 4, 6π / 4, 7π / 4
Takes two values, each with two bits and three digits, (00
0), (001), (010), (011), (10
0), (101), (110), and (111).

In order to make the description easy to understand, a description will be given by taking as an example I and Q symbol stream data I _k (8) and Q _k (8) for one symbol output from demodulation circuit 1A at time t = k. The remapper 7A _rotates I _k (8) and Q _k (8) by −Θ to make absolute phase RI _k (8) = RI _0k (8), RQ in one cycle of CLK _SYB by time division.
_k (8) = Q _0k (8)
_k (8), Q _k a (8) - (Θ + Θ' ) was only rotation R
A data set of I _k (8) = I _1k (8) and RQ _k (8) = Q _1k (8) is output. The former is latched by the latch circuits 68 and 69 and output to the subsequent stage.

Of the phase error detection processing circuit 70, 71, 7
2 latches the sign bit data which is the MSB of RI _0k (8) and RQ _0k (8) output from the remapper 7A every time the predetermined timing signal T1 is input, and Ri (1)
= _Riok (1), Rq (1) = _Rq0k (1). 73 is a selector, and RI shown by Ri _0k (1)
_{According to} the sign of _0k (8), if RI _0k (8) ≧ 0, then Θ
'000 representing' = 0 is selected and output, and RI
_0k (8) <0 represents Θ ′ = 4π / 4 (10
By selecting and outputting 0), when the BPSK modulation part of the received signal by the hierarchical transmission method is demodulated, the signal on the IQ phase plane is based on the positive direction of the I axis. The deviation angle Θ ′ = B of the received signal point P _k indicated by RI _0k (8) and RQ _0k (8) measured counterclockwise to the target phase convergence angle.
Outputs R _BPSK (3). The selector 73 sets the RI
_{When 0k} (8) ≧ 0, P _k is the area GR _{0 in} FIG.
Since the target phase convergence angle = 0, (000)
And when RI _0k (8) <0, P _k is
Has entered the area GR ₁ (1), the target phase convergent angle = 4
Since it is π / 4, (100) is selected.

Reference numeral 74 denotes a selector, and Ri _0k (1), R
From the positive and negative combinations of RI _0k (8) and RQ _0k (8) indicated by q _0k (1), (001) representing 表 す ′ = π / 4, Θ ′
= 3π / 4 (011), Θ ′ = 5π / 4 (101), and Θ ′ = 7π / 4 (111) are selected and output, and the received signal of the hierarchical transmission scheme is selected. When the QPSK modulation method is demodulated,
The deviation angle ＲＩ of the received signal point _Pk indicated by RI _0k (8) and RQ _0k (8) measured to the target phase convergence angle, which is measured counterclockwise on the IQ phase plane with reference to the positive direction of the I axis. ´ = BR
Outputs _QPSK (3).

Specifically, RI _0k (8) ≧ 0 and RQ _0k
When (8) ≧ 0, P _k is in the region ER ₀ of FIG. 21A, and the target phase convergence angle = π / 4.
1) and RI _0k (8) <0 and RQ _0k (8) ≧ 0
At this time, since P _k is in the area ER ₁ of FIG. 21A and the target phase convergence angle is 3π / 4, (011) is selected. Also, RI _0k (8) <0 and RQ _0k (8) <0
At this time, since P _k is in the area ER ₂ of FIG. 21A and the target phase convergence angle is 5π / 4, (101) is selected, and RI _0k (8) <0 and RQ _0k (8) When ≧ 0,
Since P _k is in the area ER ₃ of FIG. 21A and the target phase convergence angle is 7π / 4, (111) is selected.

Reference numeral 75 denotes an inverting circuit, and RI _k (8) = R
Both I _0k (8) and RQ _k (8) = RQ _0k (8)
-RI _k (8) with the same absolute value but inverted by the positive and negative signs
= −RI _0k (8), _{−RQ k} (8) = − RQ _0k (8) The phase angle of the received signal point indicated by -RI _0k (8) and -RQ _0k (8) was added π to the phase angle φ of the original RI _0k (8) and RQ _0k (8) is the received signal point shown It will be. 7
6 is a selector, while the CLK _SYB is falls, when Ri _0k (1) indicates the _{RI 0k (8) ≧ 0,} RI k (8) = RI 0k (8), RQ k ( 8) = RQ
_0k (8) is directly input to the phase error table 15-1A, and from the phase error table 15-1A, RI _0k (8),
Phase error data Δφ _k (8) corresponding to RQ _0k (8) =
To output [Delta] [phi _0k (8), on the contrary, when Ri _0k (1) indicates a negative, -RI _0k entering the domain of the phase error table 15-1A (8), - RQ _0k (8) The phase error table 15-1A is input to the phase error table 15-1A.
1A from -RI _0k (8), - the phase error data Δφ _k (8) corresponding to the RQ _0k (8) = to output Δφ _0k (8). Note that while the CLK _SYB is rising, the selector 76 outputs RI (8) and R (8) output from the remapper 7A.
Q (8) is directly input to the phase error table 15-1A, and RI (8), R
The phase error data Δφ (8) corresponding to Q (8) is output.

Reference numeral 77 denotes a latch circuit, which receives a predetermined timing signal T2 every time a predetermined timing signal T2 is input.
Phase error data Δφ _k (8) output from 1A = Δφ
_0k Phase error data Δφ as upper 3 bits of (8)
_k (3) = Δφ _0k (3) is latched and output. Δφ _0k
From (3), the absolute value of the phase error is (π / 8) + s ·
It can be determined whether (π / 8) (s is 0, 1, 2) is larger or smaller (see FIG. 3). _Combining this Δφ _0k (3) and the sign bit data Rq _0k (1), which is the MSB of RQ _0k (8), and _performing a simple arithmetic processing, the 8PSK modulation method part of the received signal by the hierarchical transmission method Is demodulated, it is determined which of the eight regions KR _{0 to} KR ₇ the reception signal point P _k indicated by RI _0k (8) and RQ _0k (8) belongs to. RI _0k (8), RQ _0k (8) measured counterclockwise on the IQ phase plane with reference to the direction
The deviation angle 受 信 of the received signal point P _{k to} the target phase convergence angle indicated by Θ
'= BR _8PSK (3) can be output.

Reference numeral 78 denotes a 4-bit adder for adding 4-bit data (however, the carry to the 5th bit is not performed), and Rq (1) = Rq is added to the most significant bit on one input side.
_0k (1) is input, and the output of the latch circuit 77 is input to the lower three bits. The 4-bit data A (4) = (0001) is input to the other input side of the adder 78. The adder 78 performs the 4-bit addition of the two inputs. When the upper 3 bits of the added value are demodulated in the 8PSK modulation method out of the received signal by the hierarchical transmission method, the adder 78 outputs the I-axis signal. The deviation angle Θ ′ of the reception signal point _Pk indicated by RI _0k (8) and RQ _0k (8) measured to the target phase convergence angle measured in the counterclockwise direction on the IQ phase plane with respect to the positive direction.
_Is output as BR _8PSK (3).

Reference numeral 80 denotes a selector, which shifts the input from the selector 73 according to the modulation scheme identification signal DM input from the transmission multiplex configuration identification circuit 9 while the demodulation circuit 1A is demodulating the BPSK modulation portion. As BR (3) indicating that the input from the selector 74 is shifted while the demodulation circuit 1A is demodulating the QPSK modulation portion.
R (3), and while the demodulation circuit 1A is demodulating the 8PSK modulation portion, the input from the adder 78 is shifted by the shift angle Θ
'As BR (3). This BR (3)
During the period when CLK _SYB is falling and after the timing signal T2, I after absolute phase conversion measured counterclockwise on the _IQ phase plane with respect to the positive direction of the I axis. Q symbol stream data RI _0K (8), RQ _0K
Demodulation circuit 1A of reception signal point P _k indicated by set data of (8)
Represents a shift angle Θ ′ up to the target phase convergence angle in the modulation method under demodulation. 81 is a 3-bit adder (however, 4
The carry to the bit is not carried out), and the received signal phase rotation angle detection signal AR (3) output from the received signal phase rotation angle detection circuit 8 is added to the output of the selector 80.

_Reference numeral 82 denotes a latch circuit, which is an adder 81 based on a timing signal T3 input during a period when CLK _SYB is falling and after the timing signal T2.
Is latched, and CR (3) indicating (Θ + Θ ′) is output to the remapper 7A. When CLK _SYB rises next, the remapper 7A _outputs RI _1k (8) and R _1k (8) that have been phase-rotated by − (Θ + Θ ′) with respect to I _k (8) and Q _k (8).
Q _1k (8) is output. This RI _1k (8), RQ
_1k (8) is the phase error table 1
5-1A and the corresponding phase error data Δφ
_k (8) = Δφ _1k (8) is read. This Δφ
_1k (8) is a latch circuit 83 based on the timing signal T4.
And output to the D / A converter 17 as Δφ (8) ′. The other components in FIG. 1 are configured exactly the same as in FIG.

Next, the operation of the above embodiment will be briefly described. (1) Start of reception At the start of reception, the reception signal phase rotation angle detection circuit 8 sets AR (3) = () corresponding to the reception signal phase rotation angle Θ = 0 as an initial value until the first reception signal phase rotation angle can be detected. 00
0), and the transmission multiplex configuration identification circuit 9 outputs a modulation scheme identification signal DM corresponding to 8PSK modulation as an initial value until the first modulation scheme can be identified.

The remapper 7A outputs the signal from the demodulation circuit 1A at time t.
(However, with respect to I _t (8) and Q _t (8) in symbol units output at t =..., K-1, k, k + 1,.
RI _0t (8) (= I _t (8)), RQ rotated by − 回 転 in the second half of one cycle of the symbol clock CLK _SYB
0t (8) (= Q _t (8)) is output, latched by the latch circuits 68 and 69 and output to the subsequent stage. In the phase error detection processing circuit 70, the reception signal phase rotation angle detection circuit 8
, The selector 80 selects the output BP _8psk (3) of the adder 78 until the transmission multiplex configuration identifying circuit 9 identifies the modulation method, and selects the BR.
Output as (3). Since AR (3) is (000), CR (3) = BP _8psk (3) is input to the remapper 7A.

BP _8psk (3) _converts all received signals to 8 PS
When considered as the K modulation method, RI _0t (1) measured counterclockwise on the IQ phase plane with reference to the positive direction of the I axis,
Since RQ _0t (1) represents the deviation angle Θ ′ of the received signal point P _{0t up to} the target phase convergence angle (see FIG. 9 (1)), the remapper 7A does not respond to CR (3) (Θ + Θ ′). ,-(Θ
+ Θ ′) RI _1t (1), RQ
_As shown in FIG. 9 (2), the received signal point P _1t by _1t (1)
Enters the range of [pi / 4 around the phase 0 on -Q phase plane, and phase angle phi _1t of difference in phase angle phi _0t and target phase convergent angle of the received signal point P _0t is the received signal point P _1t , The phase error detection processing circuit 70 sets the phase error table 15-1A
From the phase error data Δφ _1t (8) corresponding to RI _1t (1) and RQ _1t (1),
Correct phase error data Δφ when considered as K modulation method
_t (8) ′ = Δφ _1t (8) can be output to the D / A converter 17.

The Δφ _1t (8) is converted into a phase error voltage by the D / A converter 17, and a low-frequency component is extracted by the LPF 18 and applied to the VCO 11 as a control voltage. If the phase error data Δφ _1t (8) is 0, the output of the LPF 18 does not change and the phases of the reference carriers f _C1 and _{fc 2} do not change, but if the phase error data Δφ (8) is +, the LPF 1
8 becomes large, the phases of the reference carriers f _C1 and f _c2 are delayed, and conversely, if the phase error data Δφ (8) is −, L
The output of PF18 is reduced, the phase of the reference carrier f _C1, f _c2 is advanced. Thereby, the phases of the reference carriers f _C1 and f _c2 are corrected so as to maintain a fixed relationship with the phase of the received carrier. As a result, the demodulation circuit 1A outputs the phase 0, π on the transmitting side.
/ 4, 2π / 4, 3π / 4, 4π / 4, 5π / 4, 6π
/ 4 and 7π / 4 signal point constellations “0” to “7” are respectively converted into Θ = m × π on the IQ phase plane on the receiving side.
The corrected I _t (8) and Q _t (8) are output at a position rotated by / 4 (where m is an integer of 0 to 7).

The frame synchronization detection / reproduction circuit 2
_t (8), and acquisition of the frame synchronization signal based on the Q _t (8), the frame sync pulses, reproduction frame synchronization signal, performs output of the frame synchronizing signal section signal, the received signal phase rotation angle detection circuit 8 I _t ( 8), Q _t (8), the reproduced frame synchronization signal, and the frame synchronization signal section signal.
AR (3) representing Θ _W by detecting the received signal phase rotation angle に 対 す る (referred to as Θ _W in order to distinguish this from the initial value = 0) with respect to the transmitting side as seen in _t (8) and Q _t (8). Is output to the remapper 7A and the phase error detection processing circuit 70. When the transmission multiplex configuration identification circuit 9 receives the frame synchronization pulse FSYNC, the transmission multiplex configuration identification circuit 9 captures the bit stream Bn of the system having a high potential repeatedly among SYNA0 to SYNA7, by using a predetermined timing signal generated from the frame sync pulse FSYNC, TMCC pattern to extract, decode to current I _t (8) in FIG. 12 (1), or not Q _t (8) is by any modulation scheme Is output (see FIG. 12 (2)).

Here, assuming that the received signal phase rotation angle Θ _W is detected first, the remapper 7A outputs I _t (8),
Q _t (8) is phase-rotated in the opposite direction by −Θ _W to make absolute I
_0t (8) and Q _0t (8) are output. Since CR (3) output from the phase error detection processing circuit 70 is (Θ _W + Θ ′),
Even if Θ changes from the initial value 0 to Θ _W , the remapper 7A
For (Θ _W + Θ ′) indicated by R (3), − (Θ _W + Θ
′), The received signal point P _1t by RI _1t (1) and RQ _1t (1) is rotated by π / 4 centered on the phase 0 on the IQ phase plane as shown in FIG. 9 (2). enters the range and the difference in phase angle phi _0t and target phase convergent angle of the received signal point P _0t is equal to the phase angle phi _1t of the received signal point P _1t, the phase error detecting processing circuit 70 the phase error table 15- RI from 1A
_1t (1), phase error data Δφ corresponding to RQ _1t (1)
By inputting and latching _1t (8), correct phase error data Δφ _t (8) when the 8PSK modulation method is considered.
'= Δφ _1t (8) can be output to the D / A converter 17.

(2) Normal Reception Operation Hereinafter, as an example, Θ _W = 3π / 4 (AR (3) = (01)
1)). (I) 8PSK modulation method part (see FIG. 9) Subsequent to the reception signal phase rotation angle detection circuit 8, the transmission multiplex configuration identification circuit 9 identifies the multiplex configuration, and the current I and Q symbols output from the demodulation circuit 1A. stream I _t (8), Q
_{When the} modulation scheme identification signal DM indicating which modulation scheme part _t (8) is output, the selector 80 of the phase error detection processing circuit 70 selects and outputs the output of the adder 78 when DM indicates 8PSK. . 8 for signal point arrangement “3” on the transmitting side
Received signal point of PSK mapped digital signals (abc) in the case of Θ _W = 3π / 4, when viewed in an output of the demodulation circuit _{1A I t (8), Q} t (8), the signal point arrangement Although the phase falls within the range of π / 4 centered on the phase 6π / 4 of “6”, the reception signal point P _0t by the outputs I _0t (8) and Q _0t (8) of the remapper 7A becomes absolutely different from the transmission side by the absoluteization. Similarly, it falls within the range of π / 4 centered on the phase 3π / 4 of the signal point arrangement “3”.

At this time, BR (3) = BR _8PSK (3) becomes (011) indicating Θ ′ = 3π / 4, and (Θ _W + Θ
') = 6π / 4, so that the received signal point P _1t based on I _1t (8) and Q _1t (8) falls within the range of π / 4 centered on phase 0. Since the phase angle difference phi _0t and target phase convergent angle of the received signal point P _0t is equal to the phase angle phi _1t of the received signal point P _1t, RI _1t (8 phase error detection processing circuit 70 from the phase error table 15-1A ), The phase error data Δφ _1t (8) corresponding to RQ _1t (8) is read and latched to obtain RI
_0t (8), RQ _0t (8)
D / A converter 1 converts the phase error data that converges to
7 can be output. On the transmitting side, other signal point arrangements "0", "1", "2", "4", "5", "6",
The digital signal (a
Similarly, for bc), the received signal points as seen from the outputs RI _0t (8) and RQ _0t (8) of the remapper 7A are phase 0, π / 4, 2π / 4, 4π / 4 and 5π, respectively. / 4,
Phase error data that converges to 6π / 4 and 7π / 4 can be output to the D / A converter 17.

(Ii) QPSK Modulation System Part The selector 80 of the phase error detection processing circuit 70
When indicating PSK, the output of the selector 74 is selected and output. For example, when Θ _W = 3π / 4, the reception signal points of the digital signal (de) QPSK-mapped to the signal point arrangement “7” on the transmission side are I _t (8), Q which are the outputs of the demodulation circuit 1A. _t When viewed in (8), signal point arrangement “2”
In the range of 2π / 4 centered on the phase 2π / 4 of
The received signal point P _0t based on the outputs I _0t (8) and Q _0t (8) of the remapper 7A is 2π / 4 centered on the phase 7π / 4 of the signal point arrangement “7” as in the transmitting side due to the absoluteization. Enter the range.

At this time, BR (3) = BR _QPSK (3) becomes (111) indicating Θ ′ = 7π / 4, and (Θ _W + Θ
') = 2π / 4, so the received signal point P _1t based on I _1t (8) and Q _1t (8) falls within the range of 2π / 4 centered on phase 0. Since the phase angle difference phi _0t and target phase convergent angle of the received signal point P _0t is equal to the phase angle phi _1t of the received signal point P _1t, RI _1t (8 phase error detection processing circuit 70 from the phase error table 15-1A ), And read out and latch the phase error data Δφ _1t (8) corresponding to RQ _1t (8) to obtain RI _0t
(8), RQ _{0t The} received signal point viewed at (8) is phase 7π / 4
D / A converter 17 converts the phase error data converging to
Can be output to The same applies to the digital signal (de) QPSK-mapped to the other signal point constellations “1”, “3”, and “5” on the transmitting side, in exactly the same manner, and outputs RI _0t (8) and RQ _0t (8) of the remapper 7A. ) Can be output to the D / A converter 17 so as to converge the received signal points as indicated by the phases π / 4, 3π / 4, and 5π / 4, respectively.

(Iii) BPSK Modulation Part The selector 80 of the phase error detection processing circuit 70
When indicating PSK, the output of the selector 73 is selected and output. For example, the reception signal point of the digital signal (f) BPSK-mapped to the signal point arrangement “1” on the transmission side is:
For Θ _W = 3π / 4, which is the output of the demodulation circuit 1A I _t
(8), Q _t (8), the signal point arrangement “7” falls within the range of 4π / 4 centered on the phase 7π / 4, but the outputs I _0t (8), Q _{0t of the} remapper 7A. The reception signal point P _0t according to (8) falls within the range of 4π / 4 centered on the phase 4π / 4 of the signal point arrangement “1” as in the transmission side due to the absoluteization.

At this time, BR (3) = BR _BPSK (3) becomes (100) indicating Θ ′ = 4π / 4, and (Θ _W + Θ
') = 7π / 4, the received signal point P _1t based on I _1t (8) and Q _1t (8) is 4π / 4 centered on the phase 4π / 4.
In the range. Since the phase angle difference phi _0t and target phase convergent angle of the received signal point P _0t is equal to the phase angle phi _1t of the received signal point P _1t, the phase error detecting processing circuit 70 the phase error table 15
By reading out and latching the phase error data Δφ _1t (8) corresponding to RI _1t (8) and RQ _1t (8) from _−1A , the reception signal point viewed at RI _0t (8) and RQ _0t (8) Phase error data that converges to a phase of 4π / 4 is D / A
It can be output to the converter 17. The same applies to the digital signal BPSK-mapped to the signal point arrangement "0" on the transmission side in the same manner as the output RI of the remapper 7A.
_0t (8), RQ _0t It is possible to output phase error data to the D / A converter 17 so as to converge the received signal point as seen from _0t (8) to the phase 0.

The reception signal phase rotation angle detection circuit 8 repeatedly performs the reception signal phase rotation angle detection operation, and when Θ _W is 3π / 4
Even when it is a value other than operate in exactly the phase error detecting processing circuit 70 similarly, therefore, the value of the modulation scheme, the original digital signal, regardless of the value of theta _W, viewed in the output side of the remapper 1A Phase error data that causes the received signal point to converge to the same phase as the transmitting side can be output to the D / A converter 17.

According to this embodiment, the remapper 7A
Are I, Q for each symbol output from the demodulation circuit 1A.
In addition to outputting the symbol stream data I _0t and Q _0t that have been phase-rotated by − 逆 with respect to the symbol stream data I _t and Q _t to make them absolutely phased, time-division, modulation scheme-dependent I-axis Of the I and Q symbol stream data sets after the absolute phase measurement based on the positive direction of the I axis included in the domain of the phase error table 15-1A in the positive direction or the negative direction of the I axis. I, Q symbol stream data when the phase of the received signal point is shifted to the target phase convergence point by Θ ′ and the phase is rotated in the opposite direction by − (Θ + 逆 ′).
I _1t and Q _1t are output, and a phase error detection processing circuit 70 is provided by using the set of I and Q symbol stream data I _1t and Q _1t.
Is the phase error data Δ from the phase error table 15-1A.
φ _1t (8) is read and output to the D / A converter 17 to correct the phases of the reference carriers f _C1 and f _C2 . The phase error data Δφ _1t (8) is based on the modulation scheme of the received signal being demodulated by the demodulation circuit 1A, the received signal phase rotation angle に 対 す る with respect to the transmitting side as viewed at the output point of the demodulation circuit 1A, and the phase angle φ of the received signal point. Therefore, only one phase error table is required to be provided in the carrier recovery circuit 10A, and the number of phase error tables provided in the carrier recovery circuit 10A can be reduced, and the circuit configuration is greatly simplified. Becomes possible.

In the above-described embodiment, the phase error table 15-1A is provided with a table in which the region where I ≧ 0 of the IQ phase plane is defined as a domain (FIG. 2,
Alternatively, a table may be provided in which an area where I ≦ 0 is defined (see FIGS. 10 and 11). In this case, the BR (3) output from the selector 80 of the phase error detection processing circuit 70 is I, I, for each symbol after absolute phase conversion by the remapper 7A measured counterclockwise with respect to the negative direction of the I axis. A deviation angle Θ ′ up to a target phase convergence angle in a modulation method being demodulated by a demodulation circuit of a reception signal point indicated by the Q symbol stream data is represented.

Specifically, the selector 73 in FIG.
When the output Ri (1) of the latch circuit 71 indicates the output RI (8)> 0 of the remapper 7A, (100) is output, and RI is output.
(8) When ≤0, output (000),
The selector 74 outputs the output Ri of the latch circuits 71 and 72.
(1), RI (8) ≦ 0 and RQ (8) ≦
When 0 (001), RI (8)> 0 and RQ (8) ≦
When it is 0 (011), RI (8)> 0 and RQ (8)>
When 0 (101), RI (8) ≦ 0 and RQ (8)>
When it is 0, it selects and outputs (111), and the selector 76 sets RI (1) to RI while CLK _SYB is falling.
(8) When ≤0, the output RI of the remapper 7A
(8), RQ (8) is directly used as phase error table 15-
1A. On the contrary, when Ri (1) indicates RI (8)> 0, the output of the inverting circuit 75 is -RI.
(8) and -RQ (8) are input to the phase error table 15-1A, and the adder 78 has A (4) = 0001
Is input instead of B (4) = 1001. On the other hand, while CLK _SYB is rising, selector 76
Are RI (8) and RQ (8) output from the remapper 7A.
Is directly input to the phase error table 15-1A.

Also, the phase error table 15-1A has I-
A table may be provided in which the entire region of the Q phase plane is defined as a domain. In this case, the BR (3) output from the selector 80 of the phase error detection processing circuit 70 has the positive and negative directions of the I axis. Of each symbol after the absolute phase conversion by the remapper 7A measured counterclockwise with respect to one of them,
The deviation angle 表 す ′ up to the target phase convergence angle in the modulation method being demodulated by the demodulation circuit of the reception signal point indicated by the Q symbol stream data may be represented. For example, when the shift angle Θ ′ measured counterclockwise with respect to the positive direction of the I-axis is represented, the selector 73 in FIG.
When i (1) indicates the output RI (8)> 0 of the remapper 7A, (000) is output, and when i (1) indicates RI (8) ≦ 0, (1) is output.
00), and the selector 74 outputs the RI indicated by the outputs Ri (1) and Rq (1) of the latch circuits 71 and 72.
(8), RI is obtained from the positive / negative combination of RQ (8).
When (8) ≧ 0 and RQ (8) ≧ 0 (001), RI
(8) When <0 and RQ (8) ≧ 0 (011), RI
When (8) <0 and RQ (8) <0 (101), RI
(8) When ≧ 0 and RQ (8) <0, (111) is selected and output, the inverting circuit 75 and the selector 76 are omitted, and the outputs RI (8) and RQ (8) of the remapper 7A are phased as they are. What is necessary is just to make it input into the error table 15-1A.

In the above-described embodiments and modifications, the latch circuit 71 in FIG. 7 is omitted, and Ri (1), which is the MSB of RI (8) output from the remapper 7A, is used as the selector 73, 74, 76, the latch circuit 72 may be omitted, and Rq (1) which is the MSB of RQ (8) output from the remapper 7A may be directly output to the selector 74 and the adder 78.

[0102]

According to the present invention, only one phase error table is provided for the carrier recovery means, and the number of phase error tables provided for the carrier recovery means can be reduced, and the circuit configuration can be greatly simplified. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a domain of a phase error table in FIG. 1;

FIG. 3 is an explanatory diagram showing a relationship between a phase angle of a received signal point and phase error data in a phase error table in FIG. 1;

FIG. 4 is an explanatory diagram showing an operation of a phase error detection processing circuit.

FIG. 5 is an explanatory diagram showing an operation of a phase error detection processing circuit.

FIG. 6 is an explanatory diagram illustrating an operation of the phase error detection processing circuit.

FIG. 7 is a block diagram illustrating a configuration of a phase error detection processing circuit.

FIG. 8 is a time chart illustrating an operation of the phase error detection processing circuit.

FIG. 9 is an explanatory diagram showing an operation of the phase error detection processing circuit.

FIG. 10 is an explanatory diagram of a domain of a phase error table according to a modification of the present invention.

FIG. 11 is an explanatory diagram showing a relationship between a phase angle of a reception signal point and phase error data in a phase error table according to a modification of the present invention.

FIG. 12 is an explanatory diagram showing an example of a frame configuration in the hierarchical transmission scheme.

FIG. 13 is a block diagram showing a configuration around a demodulation circuit of a PSK modulated wave receiver using a conventional hierarchical transmission scheme.

FIG. 14 is an explanatory diagram showing a signal point arrangement in PSK mapping.

FIG. 15 is a block diagram in which a part of the carrier wave recovery circuit in FIG. 12 is omitted.

FIG. 16 is an explanatory diagram of how to measure the phase of a received signal point.

FIG. 17 is an explanatory diagram of how to measure a received signal phase rotation angle.

FIG. 18 is an explanatory diagram of a phase error table for 8PSK.

FIG. 19 is an explanatory diagram of a phase error table for QPSK.

FIG. 20 is an explanatory diagram of a phase error table for QPSK.

FIG. 21 is an explanatory diagram illustrating a relationship between a phase angle of a reception signal point and a target phase convergence angle in QPSK.

FIG. 22 is an explanatory diagram of a phase error table for BPSK.

FIG. 23 is an explanatory diagram of a phase error table for BPSK.

FIG. 24 is an explanatory diagram of a phase error table for BPSK.

FIG. 25 is an explanatory diagram of a phase error table for BPSK.

FIG. 26 is an explanatory diagram illustrating the relationship between the phase angle of a received signal point and the target phase convergence angle in BPSK.

FIG. 27 is a block diagram of a synchronization detection / reproduction circuit in FIG.

FIG. 28 is an explanatory diagram for explaining BPSK demapping;

FIG. 29 is a circuit diagram showing a configuration of a synchronization detection circuit in FIG. 27;

FIG. 30 is a circuit diagram showing a configuration of a BPSK demapper section in FIG. 27;

FIG. 31 is a signal point arrangement diagram of a frame synchronization signal before and after passing through a 0 ° / 180 ° phase rotation circuit in FIG. 13;

32 is an explanatory diagram of a reception signal phase rotation angle determination table used by the reception phase determination circuit in FIG.

[Explanation of symbols]

 Reference Signs List 1A demodulation circuit 2 frame synchronization detection / reproduction circuit 7A remapper 8 reception signal phase rotation angle detection circuit 9 transmission multiplex configuration identification circuit 10A carrier recovery circuit 11 VCO 12 90 ° phase shifter 15-1A phase error table 17 D / A converter 18 LPF 70 phase error detection processing circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-321813 (JP, A) JP-A-10-215291 (JP, A) JP-A-11-46224 (JP, A) JP-A-9-209 186730 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] 1. A PSK modulated signal in which a digital signal modulated by a two-phase, four-phase, or eight-phase PSK modulation method is time-multiplexed, demodulated using a carrier reproduced by a carrier reproducing means, and symbol-wise demodulated. Demodulation means for outputting the I and Q symbol stream data, and reception signal phase rotation angle detection means for detecting a phase rotation angle に 対 す る with respect to the transmitting side of the I and Q symbol stream data for each symbol output from the demodulation means. I for each symbol output from the demodulation means,
The anti-phase rotation means for rotating the phase of the Q symbol stream data by -Θ with respect to the phase rotation angle Θ detected by the reception signal phase rotation angle detection means and converting it into an absolute phase, and the demodulation means are demodulating And a modulation scheme identifying means for identifying the modulation scheme of the above. The anti-phase rotation means sets the phase of the I and Q symbol stream data for each symbol output from the demodulation means to two types in time division. , And one of the two types is referred to as -Θ. On the other hand, the carrier recovery means is provided with the I and Q symbol stream data after the absolute phase conversion in the two-phase PSK modulation method. A phase error table storing carrier phase error data for the set, and a phase error table in the positive direction of the I-axis or the negative direction of the I-axis according to the modulation scheme identified by the modulation scheme identification means. The deviation angle Θ ′ of the received signal point indicated by the I and Q symbol stream data sets for each symbol after absolute phase conversion measured on the basis of the one which has been measured to the target phase convergence angle in the modulation method is determined. Of the two types of phase rotation performed by the anti-phase rotation means in a time-division manner, the carrier wave phase error data corresponding to the I and Q symbol stream data sets when the phase is rotated by-(Θ + Θ ′) is the other one. Phase error detection processing means for detecting a phase error of the reproduced carrier by reading from the error table, wherein the phase of the reproduced carrier is corrected based on the carrier phase error data detected by the phase error detection processing means. A receiver characterized in that: