JP3040319B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly to a frequency synthesizer.

[0002]

2. Description of the Related Art A frequency synthesizer is used in a frequency hopping system, which is one of the spread spectrum communication systems, and an inexpensive device capable of high-speed frequency switching is required. Utilizing the fact that the frequency hopping sequence of the frequency hopping method is periodic, the steady-state phase difference at the time of frequency output is measured and stored in a memory, which is read out at the next hopping to the same frequency and initialized. A so-called initial value presentation type PLL synthesizer that presents a value as a value has been proposed. (See, for example, JP-A-3-229.
No. 517, IEICE Technical Report SST 93-29, pp. 61-66. The initial value presentation type PLL synthesizer temporarily opens the PLL circuit at the time of frequency switching, and sets the phase difference in the steady state as an initial value to P
This is a method of switching the frequency at a high speed by giving it to the LL. In this method, when the PLL is in a steady state, the phase difference information is stored in a memory, and the next time hopping to the same frequency is performed as initial value data for the target frequency.
The phase difference is read out from the memory and compared with the phase difference information after the frequency is switched to the target frequency, and a timing pulse is generated at the time when they become equal to reproduce the steady state phase difference.

FIGS. 3 and 4 are a block diagram and a timing chart and waveform chart for explaining the operation of a conventional frequency synthesizer for presenting initial values, and FIG. 4A shows a reference signal FR. FIG. 4B shows the frequency-divided signal FV, FIG. 4C shows the phase difference output signal of the phase comparator 41, and FIG.
2 (e), frequency hopping and VC
It is a figure showing an O control voltage.

[0004] The case of hopping from frequency f1 to f2 will be described with reference to FIGS. When a hopping instruction from frequency f1 to f2 is input to input terminal 60 at time ta, the frequency division ratio of frequency divider 52 is set to a predetermined frequency division ratio corresponding to frequency f2, and switch 45 is turned on. To open, the switch 54 is switched to the terminal a,
The L circuit enters an open state. Further, data corresponding to the frequency f2 stored in the ROM 50 in advance and RAM
After the initial value data V0 corresponding to the frequency f2 stored in advance in 47 is added by the adder 48 via the D / A converters 49 and 46, control is performed in place of the control signal from the PLL circuit. VCO (variable oscillator) as signal
The VCO 51 oscillates at a frequency close to the frequency f2.

On the other hand, the integrator 42 starts the integration operation at the arrival time t1 of the first reference signal after the hopping instruction.
The integrated value is led to the comparator 53, read out from the RAM 47 and compared with the initial value data V0. When the two values match (time t2), the pulse SO generated.
Is applied to the phase comparator 41 via the terminal a of the switch 54 and compared with the reference signal. Then, the voltage V0 corresponding to the phase difference is sample-held. The switch 54 is switched to the terminal b immediately after the application of the pulse S0.

The pulse S0 is applied to the frequency divider 52 as a reset release pulse. Therefore, the frequency divider 52 operates at the time t.
2, the frequency division operation is started, the frequency division output B1 is output to the phase comparator 41, and the voltage V1 corresponding to the phase difference is sampled and held, and the difference between the initial values V0 and V1 (referred to as .DELTA.V). ) Is calculated by the arithmetic circuit 44 and held. This difference ΔV is a difference between the phase of the output sine wave of the previous VCO 51 and the phase of the VCO output at time t2 in the current hopping. When the next frequency-divided output B2 is output, a phase difference signal V2 is created at time td, added to the above-described difference ΔV by the arithmetic circuit 44, and the switch 45 is short-circuited. Is switched from the initial value VO from the RAM 50 to the above-mentioned added value (added value ΔV + V2), and controls the oscillation output of the VCO 51. Thereafter, the phase difference signal V3 is sample-held at time te in the same manner as when the next frequency-divided output is obtained, and added to the above-mentioned difference ΔV to obtain a control voltage. When hopping from frequency f2 to the next frequency, the frequency f
The value of the RAM 47 corresponding to 2 is updated from the initial value V0 to the added value (ΔV + V2), and is used as the initial value for the next hopping.

Therefore, the fastest hopping time is used to obtain the initial value presentation period in the R0 section, the VCO phase shift measurement period in the next R1 section, and the initial value data at the next hopping to the same frequency. , Three cycles of the reference signal FR are required. A / D converter 4
3 are V0, V1, V2, and V3 sampled and held in the sections R0, R1, R2, and R3.
The input data of the / A converter 46 is divided into sections R0, R1, R2
V0 and ΔV + V2 in the section R3 (the value of ΔV is near zero), and the data input to the A / D converter and the D / A converter are almost the same and the same number of bits as the number of bits used by the D / A converter A / D converter is required.

[0008]

However, the conventional frequency synthesizer requires a minimum hopping time of three cycles of the reference frequency, which limits the speed of hopping. Furthermore, the A / D converter and the D / A converter require the same number of bits, and have a problem that a high-resolution A / D converter is required. An object of the present invention is to solve the above problems and to provide a high-speed frequency synthesizer which enables the use of a low-bit A / D converter.

[0009]

In order to achieve the above object, a frequency synthesizer according to the present invention comprises a means for presenting an initial value of a phase locked loop from a storage device at the time of hopping and a reference signal F.
Means for measuring the phase difference between R and the frequency-divided signal FV, and a first frequency-divided output and a reference signal obtained by driving at a first frequency-division ratio smaller than the normal frequency-division ratio during hopping , And after the first frequency division output, the frequency division ratio is changed to a normal frequency division ratio, and as the frequency division signal FV, all the frequency division outputs of the VCO 51 are used. It has a configuration that creates a phase difference signal and stores the updated initial value in a storage device.

[0010]

According to this configuration, at the time of hopping, the PLL circuit is set to the open state, the frequency divider is reset, and the VCO is driven with the initial value stored in the RAM in advance. A frequency division operation is started at a first frequency division ratio, a first phase difference signal up to the first frequency division output is generated, and a difference signal between the first phase difference signal and an initial value is generated. After the first frequency division output, the frequency divider is operated at a regular frequency division ratio according to the frequency to obtain a frequency division output. A second phase difference signal from a reference signal based on a frequency division output obtained by a normal frequency division ratio is added to the difference signal, and the sum is used as a next initial value. Therefore, since the divided output of the VCO is all used as the divided signal, the initial value at the next hopping can be created without measuring the phase shift of the VCO. Also, the D / A converter must create VCO control voltages corresponding to all hopping frequencies, but the A / D converter only needs to be able to handle the voltage value corresponding to the first phase difference described above. The number of bits used by the A / D converter may be smaller than the number of bits of the D / A converter.

[0011]

1 and 2 show an embodiment of the present invention.
Hopping from the frequency f1 to the frequency f2 will be described with reference to FIG. FIG. 1 is a block diagram showing an embodiment of the frequency synthesizer of the present invention, FIG. 2 is a timing chart and a waveform diagram for explaining the operation of the present invention, and FIG. FIG. 2B shows the divided signal FV,
4C shows the output of the phase comparator, FIG. 4D shows the output of the integrator, and FIG. 5E shows the hopping frequency and the VCO control voltage. When a hopping instruction from frequency f1 to f2 is input to input terminal 20 at time ta, frequency divider 19 is reset, and switch 15 is opened at the same time as switch P15.
The LL circuit is in an open state. Further, the initial value data V corresponding to the frequency f2 stored in the RAM 16 in advance.
0 is applied to the VCO (variable oscillator) 18 via the D / A converter 17 as a control signal instead of the control signal from the PLL circuit, and the VCO 18 oscillates at a frequency close to the frequency f2. The first reference signal A1 (t
1) is applied to the frequency divider 19 as a reset release signal, and the frequency divider synchronizes with the reference signal A1 and divides the frequency at a predetermined first frequency division ratio corresponding to the frequency f2. The operation starts, but is driven at a frequency division ratio lower than the normal frequency division ratio corresponding to the frequency f2, and the frequency division output signal B1 (time t
2), and outputs the reference signal A1 and the divided output signal B.
A phase difference signal C1 from 1 is obtained by the phase comparator 11.
When the first frequency division ratio is set to a value such that the frequency of the frequency-divided signal FV is eight times the frequency of the reference signal FR, for example, the first frequency division ratio is delayed by π / 4 phase with respect to the reference signal FR. The circumference signal FV is obtained. This phase delay amount can be set almost arbitrarily in a wide range in consideration of the resolution of the A / D converter 13 as well as around π / 4.

On the other hand, the integrator 12 starts the integration operation from the arrival time t1 of the first reference signal A1 after the hopping instruction, and integrates the integrated value until the generation of the first output pulse B1 of the frequency divider 19 (time t2). V1, that is, a voltage corresponding to the phase difference between the reference signal A1 and the divided output pulse B1 is sampled and held at time tb.

Then, a difference ΔV = (V0−V1) between the voltage V1 and the initial value V0 is calculated by the arithmetic circuit 14 and held. When the output pulse B1 is generated (time t
2) After that, the frequency division ratio is changed to a predetermined second frequency division ratio (a normal frequency division ratio corresponding to the hopping frequency) at which a frequency divided output equal to the frequency of the reference signal can be obtained. Values V2 and V3 according to the phase difference between the divided output signal and the reference signal
Are sequentially sampled and held by the integrator 12 at times tc and td.

When the first integral value V2 after the change to the second frequency dividing ratio is obtained (time tc), the switch 15 is short-circuited and the PLL operation is performed. That is, V2 is added to the held difference ΔV by the arithmetic circuit 14, and the added value is output to the D / A converter 17 instead of the initial value V0, and a new value is output to the VCO 18. Control voltage. Thereafter, when the next integral value is obtained, the value added to the difference ΔV is set as a control voltage and V
The voltage is applied to the CO 18 to operate as a PLL circuit. sand
That is, as is clear from FIG. 2, at time tc, the difference ΔV
And a value V2 corresponding to the phase difference is added to (V0-V1) +
V2 is obtained, and V3 is added at the next td (V0−V1) +
The signal of V3 is obtained.

Further, when hopping from the frequency f2 to another frequency, the value obtained by adding the difference ΔV to the phase difference signal at the time of the hopping is replaced with the initial value V0, stored in the RAM 16, and stored in the RAM 16 next time. This is the initial value for hopping. Therefore, the initial value for the next time is obtained at t
After c, the fastest hopping time is two cycles of the reference signal FR. In other words, during the fastest hopping,
The sum (V0−V1) + V2 is stored in the RAM 16 and
To the initial number of times.

In the system using the A / D converter and the D / A converter for the initial value presentation circuit, if a device having a large number of bits is used for the A / D converter and the D / A converter, the quantization error will be reduced. Although it is possible to reduce the size and improve the resolution, it is particularly desirable to use a device with a small number of bits of the A / D converter in view of cost and speed. In the present invention, the hopping RAM 1
5 is set in the D / A converter 17, so that the D / A
The converter 17 is required to have the number of bits capable of outputting voltage levels corresponding to all hopping frequencies, but the A / D converter 13 only needs to be able to correspond to the maximum output value of the integrator 12. The maximum value of the integrator 12 is the voltage value V1 of the integrator output corresponding to a phase difference of about π / 4 (this value can be set arbitrarily as described above). Therefore, the A / D converter 1
The number of bits of 3 may be smaller than the number of bits of the D / A converter 17.

[0017]

As described above, according to the present invention, the fastest hopping time of the frequency synthesizer in the frequency hopping method can be set to two cycles of the reference signal FR, and a high-speed frequency synthesizer can be realized. A /
The number of bits of the D converter may be smaller than the number of bits of the D / A converter, thereby improving the hopping speed and enabling the use of the low bit A / D converter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a frequency synthesizer of the present invention.

FIG. 2 is a timing chart and a signal waveform diagram for explaining an operation principle of the embodiment.

FIG. 3 is a block diagram showing one embodiment of a conventional frequency synthesizer.

FIG. 4 is a timing chart and signal waveform diagrams for explaining the operation principle of the embodiment.

[Explanation of symbols]

 11, 41 Phase comparator 12, 42 Integrator 13, 43 A / D converter 14, 44 Operation circuit 15, 45, 54 Switch 16, 47 RAM 17, 46, 49 D / A converter 18, 51 VCO (variable Oscillator) 19, 52 frequency divider

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ^7/ 16-7/22

Claims (3)

(57) [Claims] An oscillation output of a variable oscillator whose oscillation frequency changes according to a control signal is phase-divided by a frequency divider with a stable reference signal. A frequency synthesizer for controlling the oscillation output of the variable oscillator by having a phase control loop applied to the variable oscillator as a control signal, and changing a frequency division ratio of the frequency divider. At the time of frequency hopping for changing the oscillation output from a predetermined first frequency to a predetermined second frequency, an initial value previously stored in a storage device is used instead of the output of the phase control loop. Is applied as a control signal to the variable oscillator to change the oscillation frequency to a frequency approximating the second frequency, and synchronize the frequency divider to the second frequency in synchronization with the reference signal. Drive is performed with the frequency division ratio set lower than the corresponding normal frequency division ratio, and a first phase difference signal indicating a phase difference between the initial first frequency division output and the reference signal is generated. 1 to generate a difference signal indicating the difference between the phase difference signal and the initial value. After the first frequency division output, the frequency division ratio is changed to a normal frequency division ratio. A second phase difference signal indicating a phase difference from the reference signal is sequentially created, and a sum component of the difference signal and the second phase difference signal at the time of hopping to the next third frequency is converted to the next second A frequency synthesizer storing an initial value at the time of hopping to said frequency in said storage device. 2. After the second phase difference signal is created, a sum component of the difference signal from the initial value and the second phase difference signal is applied to the variable oscillator instead of the initial value. The frequency synthesizer according to claim 1. 3. A phase difference signal between a reference signal and a frequency-divided signal is represented by A /
D-converted and A / D-converted first phase difference signal ;
A signal indicating the initial value from the storage device calculated by the arithmetic circuit,
A sum component of the difference signal and the second phase difference signal is created, and a first phase difference signal obtained from the sum component signal and a second phase difference signal are generated.
2. The method according to claim 1, wherein a difference from the phase difference signal is applied to a variable oscillator via a D / A converter, and the initial value signal is also applied to the variable oscillator via the D / A converter. Frequency synthesizer.