JP3033793B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a large scale integrated circuit (L
In particular, the present invention relates to an element structure of an input protection circuit unit.

[0002]

2. Description of the Related Art Generally, in a semiconductor device such as an LSI, a high voltage is accidentally applied to an external terminal of the device, or an electrostatic discharge (El) in which static electricity charged on a human body is discharged to an external terminal.
When ectroStatic Discharge (ESD) occurs, the elements inside the chip are destroyed. As a countermeasure,
An input protection circuit is provided to protect elements inside the LSI.

FIG. 1 shows a conventional LSI, for example, a dynamic random access memory (DRA) of 1 Mbit.
3 shows an example of the element structure of the input protection circuit section in M). Here, 21 is a P-type semiconductor substrate, 22 is an n + -type first semiconductor region formed on a part of the surface region of the P-type substrate 21 and connected to an input pad 25 to which an external signal is inputted. (N + diffusion layers) 23 and 24 are n + -type second semiconductor regions (n + diffusion layers) formed in part of the surface region of the P-type substrate 21 and to which the ground potential Vss is applied. . The input pad 25 is connected to an input circuit (not shown) of the LSI.

FIG. 2 shows an equivalent circuit of the input protection circuit shown in FIG. 26 is an input pad 25 and an n + diffusion layer
Reference numeral 27 denotes a resistance component between the N + diffusion layer 22 and a parasitic bipolar transistor (NPN transistor) formed by the n + diffusion layer 22, the P-type substrate 21, and the n + diffusion layers 23 and 24. The base potential of the parasitic bipolar transistor 27 is the potential of the substrate 21, and is normally supplied with the back gate bias potential _VBB .

[0005] The input protection circuit section having the above-described structure includes an input pad.
When a large voltage is accidentally applied to an external terminal (not shown) connected to 25 or an electrostatic discharge occurs, this input pad is
25 from the n + diffusion layer 22 connected to the n + diffusion layer
Excessive current flows to 23 and 24 to prevent destruction of circuit elements inside the LSI.

[0006]

However, the base potential of the parasitic bipolar transistor 27 is the back gate bias potential _VBB . This back gate bias potential V _BB is used in transistors in a memory cell array section and a cell peripheral circuit section (not shown) provided in the semiconductor substrate 21. Therefore, when an excessive current flows from an external terminal (not shown) to the input pad 25 due to electrostatic discharge, a large amount of current flows to the semiconductor substrate 21 and the substrate potential becomes unstable, and the memory cell array unit and the The transistor in the cell peripheral circuit may be destroyed.

In testing an integrated circuit, a predetermined negative potential (V _IL ) is applied to an external terminal (not shown) connected to the input pad 25. Then, minority carriers generated from the n + diffusion layer 22 connected to the input pad 25 flow out to the semiconductor substrate 21 to make the back gate bias potential V _BB unstable. For this reason, a transistor using the back gate bias potential V _BB may cause a malfunction other than the input protection circuit section.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to solve the problem when an excessive current flows due to electrostatic discharge to an input pad to which a signal is externally supplied. In addition, a semiconductor device having a highly reliable input protection circuit unit that can stably maintain the substrate potential and prevent the transistors using the substrate potential from being destroyed in circuits other than the input protection circuit unit. It is something to offer.

It is another object of the present invention to stably maintain a substrate potential even when a negative input potential (V _IL ) for testing is applied to an input pad, and to provide a circuit other than the input protection circuit section. Another object of the present invention is to provide a semiconductor device having a highly reliable input protection circuit portion, which can prevent a malfunction of a transistor using a substrate potential and can provide a highly reliable input protection circuit portion.

[0010]

According to the present invention, there is provided an N-type semiconductor substrate, a P-type well region formed in a part of a surface region of the semiconductor substrate, and an N-type semiconductor substrate. An N-type first semiconductor region formed in a part of the surface region of the semiconductor device and connected to an input pad to which an external signal is input; and formed on both sides of the first semiconductor region in the surface region of the well region. And an N-type second semiconductor region to which a ground potential is applied, and a surface region of the well region, which is provided near the second semiconductor region and surrounding the first and second semiconductor regions. And a P-type third semiconductor region to which a ground potential is applied, wherein the well region does not include a semiconductor region other than the first, second, and third semiconductor regions. Independent of other semiconductor circuits provided in The first semiconductor region, the well region, and the second semiconductor region form a parasitic bipolar transistor between an input pad and a ground potential; and the first semiconductor region, the well region, and the third semiconductor region are connected to an input pad. A parasitic diode connected in parallel with the parasitic bipolar transistor is formed between the pad and the ground potential.

The present invention also provides an N-type semiconductor substrate,
A P-type well region formed in a part of the surface region of the semiconductor substrate and dedicated to the protection circuit, which is distinguished from other circuit regions, and formed in a part of the surface region of the well region to receive an external signal. and the N-type first semiconductor region which is connected to an input pad that is, the well region, respectively formed in the surface region on both sides of the first semiconductor region, a second N-type ground potential is applied, respectively And a P-type third region provided in the surface region of the well region, in contact with the second semiconductor region, surrounding the first and second semiconductor regions, and applied with a ground potential. A semiconductor region, wherein the first semiconductor region, the well region, and the second semiconductor region form a parasitic bipolar transistor between an input pad and a ground potential, and the first semiconductor region, the well region, and the third semiconductor region. Semiconductor area Forming the parasitic bipolar transistor and connected in parallel parasitic diode between the pad and the ground potential. Further, the first semiconductor region is provided near the input pad. In addition, in contact with a lower side of the first semiconductor region inside the well region.
An N-type well region is formed.

Further, the present invention provides an N-type semiconductor substrate, a P-type first well region formed in a part of a surface region of the semiconductor substrate and supplied with a potential lower than the ground potential, A memory circuit formed in one well region and receiving an external signal from an input pad; a P-type second well region formed in a part of a surface region of the semiconductor substrate;
An N-type first semiconductor region formed in a part of the surface region of the second well region and connected to the input pad;
A ground potential is applied to the surface of the second well region on both sides of the first semiconductor region.
An N-type second semiconductor region and a surface region of the second well region, which is formed in the vicinity of the second semiconductor region on the side opposite to the first semiconductor region side of the second semiconductor region. And a P-type third semiconductor region to which a ground potential is applied, wherein the first semiconductor region, the second well region, and the second semiconductor region have a parasitic bipolar transistor between an input pad and a ground potential. Forming the first semiconductor region;
The second well region and the third semiconductor region form a parasitic diode connected in parallel with the parasitic bipolar transistor between the input pad and the ground potential.

Further, the present invention provides an N-type semiconductor substrate,
And the P-type well region formed in a part of the surface region of the semiconductor substrate, is formed on a part of the surface area of the well region, N-type connected to an input pad an external signal is input <br / A first semiconductor region and a surface region of the well region,
An N-type second semiconductor region formed on both sides of the first semiconductor region, to which a ground potential is applied, and a first region of the second semiconductor region in a surface region of the well region;
A third P-type semiconductor region formed in the vicinity of the second semiconductor region on the side opposite to the semiconductor region side, and one end connected to the third semiconductor region and the other end connected to the ground potential Wherein the first semiconductor region, the well region, and the second semiconductor region form a parasitic bipolar transistor between an input pad and a ground potential, and the first semiconductor region, the well region, and the second semiconductor region. The third semiconductor region forms a parasitic diode connected in parallel with the parasitic bipolar transistor between the input pad and the ground potential.

The present invention further provides an N-type semiconductor substrate, a P-type first well region formed in a part of a surface region of the semiconductor substrate, and supplied with a potential lower than the ground potential, A memory circuit formed in one well region and receiving an external signal from an input pad; a P-type second well region formed in a part of a surface region of the semiconductor substrate;
An N-type first semiconductor region formed in a part of the surface region of the second well region and connected to the input pad;
A ground potential is applied to the surface of the second well region on both sides of the first semiconductor region.
An N-type second semiconductor region and a surface region of the second well region, which is formed in the vicinity of the second semiconductor region on the side opposite to the first semiconductor region side of the second semiconductor region. A third P-type semiconductor region, and a resistance element having one end connected to the third semiconductor region and the other end connected to the ground potential, wherein the first semiconductor region and the second The well region and the second semiconductor region form a parasitic bipolar transistor between the input pad and the ground potential, and the first semiconductor region, the second well region and the third semiconductor region form the parasitic bipolar transistor between the input pad and the ground potential. A parasitic diode connected in parallel with the parasitic bipolar transistor is formed.

Further, the present invention provides an N-type semiconductor substrate,
A P-type well region formed in a part of the surface region of the semiconductor substrate and dedicated to the protection circuit, which is distinguished from other circuit regions, and formed in a part of the surface region of the well region to receive an external signal. and the N-type first semiconductor region which is connected to an input pad that is, the well region, respectively formed in the surface region on both sides of the first semiconductor region, a second N-type ground potential is applied, respectively And a P-type third semiconductor region provided in a surface region of the well region and in contact with the second semiconductor region and surrounding the first and second semiconductor regions. And a resistance element having one end connected to the third semiconductor region and the other end connected to the ground potential, wherein the first semiconductor region, the well region, and the second semiconductor region are connected to an input pad and a ground. Form a parasitic bipolar transistor between potentials And said first semiconductor region, the well region and the third semiconductor region is a parasitic diode formed between the input pad ground potential, the cathode of the parasitic diode is connected directly to the collector of the parasitic bipolar transistor.

[0016]

[0017]

[0018]

[0019]

In other words, the present invention relates to an N-type semiconductor substrate.
Provided a P-type well region, a first semiconductor region of the connected N-type to the input pad to the well region, a second N-type ground potential is provided on both sides of the first semiconductor region is provided And a P-type third semiconductor region which is arranged near the second semiconductor region and surrounding the first and second semiconductor regions and to which a ground potential is applied. A parallel circuit of a parasitic bipolar transistor and a parasitic diode is formed between the ground and the ground. Therefore, when an excessive current flows through the input pad due to electrostatic discharge, the parasitic bipolar transistor becomes conductive, and an excessive current can flow from the first semiconductor region to the second semiconductor region. In addition, the input protection circuit is formed in a dedicated well region, the input protection circuit is separated from other circuits, and the base potential of the parasitic bipolar transistor, that is, the potential of the well region is different from the back gate bias potential and is different from the ground potential. It is. Therefore, even if an excessive current flows through the bipolar transistor, the internal circuit can be prevented from being destroyed. Further, even when a negative potential for testing is applied to the input pad to bias the first semiconductor region and the well region in the forward direction and minority carriers are generated from the first semiconductor region, the well region remains in the other region. Since the potential is independent of the circuit and is set to the ground potential, the back gate bias does not fluctuate due to the generated carrier, and the destruction of data in the internal circuit can be prevented.

Further, the input protection circuit section is surrounded by a well region and is independent of other transistors, and the base potential of the parasitic bipolar transistor is set to a fixed potential such as a ground potential instead of a back gate bias potential. Have been. Therefore, even if a large voltage or electrostatic discharge is accidentally applied to the input pad and a large amount of current flows to the well region, the substrate potential does not become unstable, and the substrate potential is reduced except in the input protection circuit section. Destruction of other transistors used can be prevented. Further, by forming the well region immediately below the first semiconductor region, the first region can be prevented from an excessive current.
Semiconductor region can be protected.

Further, by setting the third semiconductor region to a lower potential than the second semiconductor region by using a resistor or a plurality of potentials, it becomes difficult for the parasitic diode to easily conduct, and the parasitic diode is connected to the anode side of the parasitic diode. By supplying the potential from the independent potential generation circuit, even when the parasitic diode becomes conductive, the substrate potential does not become unstable, and other circuits using the substrate potential other than the input protection circuit section are used. Malfunction can be prevented.

[0022]

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 3 and 4 show the first embodiment of the present invention and show an example of the element structure of an input protection circuit section in an LSI, for example, a 16 Mbit DRAM.

In the input protection circuit section IPC shown in FIGS. 3 and 4, a P-type well region (P-well) 17 is formed in a part of the surface region of the N-type semiconductor substrate 11. An n + -type first semiconductor region (n + diffusion layer) 12 is formed in a part of the surface region of the P-well 17.
An input pad 18 to which an external signal is input is connected to 12. The input pad 18 is provided near the first semiconductor region 12. The input pad 18 is connected to an input circuit IN of an integrated circuit constituted by, for example, an inverter circuit, and receives an external signal. Connected to an external terminal 16.

A part of the surface area of the P well 17
On both sides of the semiconductor region 12, n + type second semiconductor regions (n + diffusion layers) 13 and 14 are formed. A constant potential, for example, a ground potential Vss is applied to these second semiconductor regions 13 and 14, respectively. A part of the surface region of the P-well 17 and around the second semiconductor regions 13 and 14 are formed a third semiconductor region (p + diffusion layer) 15 of p + type.
The third semiconductor region 15 has a portion 15a along the second semiconductor region 13 and a portion 15b along the second semiconductor region 14. In this third semiconductor region 15,
A constant potential, for example, a ground potential Vss is applied. Therefore, the potential of the well region 17 is set to the ground potential Vss via the third semiconductor region 15.

The well region 17 does not include any semiconductor regions other than the first, second, and third semiconductor regions 12, 13, 14, and 15. That is, as shown in FIG. 3, the input protection circuit section is provided in one independent well region 17, and the other circuits are provided in the semiconductor substrate 11 in a P-type circuit provided separately from the well region 17. Is formed in the well region 17a. In the well region 17a, memory cells MC forming a memory cell array portion are provided. This memory cell MC is composed of, for example, a MOS transistor 17b and a capacitor 17c. Further, in the well region 17a, a cell peripheral circuit portion (not shown) and the like are formed, and ap + diffusion layer 17d is formed. A constant potential, for example, a back gate bias potential _VBB is applied to the p + diffusion layer 17d. Therefore, the potential of well region 17a becomes p +
The potential V _BB is set via the diffusion layer 17d.

FIG. 5 shows the input protection circuit shown in FIGS.
The equivalent circuit of IPC is shown. Reference numeral 19 denotes a parasitic transistor (NPN transistor) formed by the n + diffusion layer 12, the P well 17, and the n + diffusion layers 13 and 14.
Reference numeral 10 denotes a parasitic diode formed by the n + diffusion layer 12, the P well 17, and the p + diffusion layer 15.

According to the above configuration, the parasitic transistor 19 and the parasitic diode 10 are formed in the input protection circuit section IPC, and the input protection circuit section IPC is connected to the well region 1 in the N-type substrate 11.
It is surrounded by 7 and is independent of the transistors that make up the memory cell array and cell peripheral circuitry. Moreover,
The base potential of the parasitic transistor 19, i.e., the potential of the P-well 17, rather than the back gate bias potential V _BB, is set to the ground potential Vss.

Thus, when a large voltage is accidentally applied to the external terminal 16 connected to the input pad 18 or an electrostatic discharge occurs in the external terminal 16, the parasitic transistor connected to the input pad 18 Excess current flows through 19 and does not flow into the memory cell array section or the cell peripheral circuit section. Therefore, it is possible to prevent the destruction of the circuit element inside the integrated circuit. In this case, even if a considerable amount of current flows to the P well region 17 when an excessive current flows, the substrate potential does not become unstable, and the transistors in the memory cell array portion and the cell peripheral circuit portion are destroyed. Never.

In the test of the integrated circuit, even if a negative input potential (V _IL ) for testing is applied to the external terminal 16 connected to the input pad 18 and a current flows through the parasitic diode 10, In the case of this embodiment, the substrate potential can be stably held. Therefore, transistors other than the input protection circuit unit IPC do not malfunction. FIG. 6 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and only different parts will be described. In the second embodiment, the n + diffusion layer 13 is connected to a p + diffusion layer 15a, and the n + diffusion layer 14 is connected to a p + diffusion layer 15b.

[0030] The second embodiment also, it is Rukoto obtain substantially the same effect as the first embodiment described above. Only
Also, the second semiconductor region and the third semiconductor region are connected to each other.
Occupied area of the input protection circuit
The size of the entire semiconductor device can be reduced. In this embodiment, in order to strengthen the measures against electrostatic discharge, it is preferable that the n + diffusion layer 12 and the n + diffusion layers 13 and 14 are brought closer to each other to improve the operation speed of the parasitic transistor 19. FIG. 7 shows a third embodiment of the present invention.
The same parts as those of the embodiment are denoted by the same reference numerals, and only different parts will be described.

In this embodiment, an N well 30 is formed inside the well region 17 and immediately below the n + diffusion layer 12. According to this configuration, at the time of electrostatic discharge, the N + diffusion layer 12 can be protected from an excessive current by the N well 30, and the n + diffusion layer 12 can be prevented from being destroyed. FIG.
Shows a fourth embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and only different parts will be described.

In this embodiment, n + diffusion layer 13 and p +
The distance a between the diffusion layers 15a and the n + diffusion layer 14 and p +
The distance a between the diffusion layers 15b is the distance b between the n + diffusion layer 12 and the n + diffusion layer 13n +, and the distance a between the diffusion layer 12 and the n + diffusion layer.
It is made larger than the distance b between the fourteen. The distance b is longer than the design rule of the integrated circuit. FIG. 9 shows an equivalent circuit of the input protection circuit unit IPC shown in FIG. 8. The same parts as those in the first embodiment are denoted by the same reference numerals, and only different parts will be described.

In this embodiment, a parasitic resistor 20 is connected between the anode of the parasitic diode 10 and the ground potential Vss. The parasitic resistance 20 is a parasitic well resistance between the n + diffusion layer 12 and the p + diffusion layers 15a and 15b.

According to this embodiment, the same effect as that of the first embodiment can be obtained. Moreover, in this embodiment, the p @ + diffusion layers 15a and 15b are formed on the outer peripheral portion of the well region 17 and the n @ + diffusion layer 12 and the p @ + diffusion layer are different from those of the first embodiment.
The parasitic resistance 20 between the diffusion layer 15a and the parasitic resistance 20 between the n + diffusion layer 12 and the p + diffusion layer 15b is increased. Therefore, when a negative input potential (V _IL ) for test is applied, a parasitic diode
In case that only the entered negative potential lower than the ground potential Vss forward voltage V _F of 10 also, by the action of the parasitic resistance 20, a parasitic diode 10 is hardly turned. Therefore, a large current does not flow through the entire integrated circuit, and the conventional functional failure does not occur. FIG. 10 and FIG.
This shows a fifth embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and only different parts will be described.

10 and 11, the p + diffusion layer 15a
Is connected to the ground potential Vss via the resistance element 31, and the p + diffusion layer 15b is connected to the ground potential Vss via the resistance element 32.

More specifically, as shown in FIG. 11, the p + diffusion layers 15a and 15b
One end of each of the resistance elements 31 and 32 is connected through Al, and the other end of each of the resistance elements 31 and 32 is connected through a second aluminum wiring layer 2Al provided above the first aluminum wiring layer 1Al. Connected to the ground potential Vss. This second aluminum wiring layer 2Al is connected to n @ + diffusion layers 12,13. The resistance elements 31 and 32 are, for example, 10 KΩ.
It is composed of a certain degree of polysilicon. These resistance elements 31 and 32 can use diffusion resistance or the like.

In this embodiment, the ground potential Vss is supplied to the p + diffusion layers 15a and 15b via the resistance elements 31 and 32, respectively, so that the potential of the p + diffusion layers 15a and 15b is
lower than ss. Thus, the negative input potentials for example test input pad 18 (V _IL) is applied, even when the potential of the input pad 18 is lower than the forward voltage V _F by the ground potential Vss of the parasitic diode 10, The action of the resistors 31 and 32 makes it difficult for the parasitic diode 10 to turn on. Therefore, a large current does not flow through the entire integrated circuit, and the conventional functional failure does not occur.

Further, according to this configuration, the substrate potential can be stably held at the time of electrostatic discharge or application of a negative input potential (VIL) for testing, and the transistors constituting the circuits other than the input protection circuit section can be maintained. Destruction can be prevented.

[0039]

[0040]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046]

In addition, the present invention is not limited to the above-described embodiment, but may be modified within the scope of the invention.
Needless to say, various modifications can be made.

[0048]

As described above in detail, according to the present invention, it is possible to prevent the substrate potential from becoming unstable at the time of electrostatic discharge or at the time of applying a test negative potential (VIL). It is possible to provide a semiconductor device having a highly reliable input protection circuit which can prevent destruction or malfunction of a transistor using a substrate potential other than the above.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an input protection circuit section of a conventional semiconductor device.

FIG. 2 is an equivalent circuit diagram of the input protection circuit unit shown in FIG.

FIG. 3 is a sectional view showing a first embodiment of the present invention.

FIG. 4 is an exemplary plan view showing a pattern of the input protection circuit unit shown in FIG. 3;

FIG. 5 is an equivalent circuit diagram of the input protection circuit unit shown in FIG. 3;

FIG. 6 is a sectional view showing a second embodiment of the present invention.

FIG. 7 is a sectional view showing a third embodiment of the present invention.

FIG. 8 is a sectional view showing a fourth embodiment of the present invention.

9 is an equivalent circuit diagram of the input protection circuit unit shown in FIG.

FIG. 10 is a sectional view showing a fifth embodiment of the present invention.

FIG. 11 is a plan view showing a pattern of a main part of FIG. 10;

[Explanation of symbols]

10 ... parasitic diode, 11 ... N-type semiconductor substrate, 12 ... n + type first semiconductor region (n + diffusion layer), 13, 14 ... n + type second semiconductor region (n + diffusion layer), 15a, 15b ... p + -type third semiconductor region (p + diffusion layer), 16 ... external terminal, 17 ...
P-type well region (P-well), 18 ... input pad, 19 ...
Parasitic transistor (NPN transistor), 20: parasitic resistance, 31, 32: resistive element, IPC: input protection circuit section, IN: input circuit, Vss: ground potential.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideyoshi Fujii 1st Toshiba Research Institute, Komukai-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Kenji Numata Kenji Numata Komukai-Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa No. 1 Toshiba Research Institute, Inc. (72) Inventor Masaharu Wada No. 1, Komukai Toshiba-cho, Koyuki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Inc. (56) References JP-A-1-286354 (JP, A) JP-A-63-137478 (JP, A) JP-A-2-119262 (JP, A) JP-A-58-121663 (JP, A) JP-A-51-39065 (JP, A)

Claims (8)

(57) [Claims] An N-type semiconductor substrate, a P-type well region formed in a part of a surface region of the semiconductor substrate, and an external signal are formed in a part of a surface region of the well region. An N-type first semiconductor region connected to an input pad, and a ground potential formed on both sides of the first semiconductor region in a surface region of the well region.
An N-type second semiconductor region, a P region provided in a surface region of the well region, disposed near the second semiconductor region and surrounding the first and second semiconductor regions, and applied with a ground potential. and a third semiconductor region of the mold, said well region, said first, second, does not contain a semiconductor region other than the third semiconductor region, the other semiconductor circuit provided in the semiconductor substrate Independently, the first semiconductor region, the well region, and the second semiconductor region form a parasitic bipolar transistor between an input pad and a ground potential, and the first semiconductor region, the well region, and the third semiconductor region are A semiconductor device, wherein a parasitic diode connected in parallel with the parasitic bipolar transistor is formed between an input pad and a ground potential. 2. An N-type semiconductor substrate, a P-type well region formed in a part of a surface region of the semiconductor substrate and dedicated to a protection circuit and distinguished from other circuit regions; and a surface of the well region. An N-type first semiconductor region formed in a part of the region and connected to an input pad to which an external signal is input; and an N-type first semiconductor region formed on both sides of the first semiconductor region in a surface region of the well region; Ground potential is applied respectively
An N-type second semiconductor region; and a P which is provided in a surface region of the well region, is in contact with the second semiconductor region, surrounds the first and second semiconductor regions, and is applied with a ground potential. and a third semiconductor region of the mold, said first semiconductor region, the well region and the second semiconductor region is a parasitic bipolar transistor is formed between the input pad ground voltage, said first semiconductor region, the well A semiconductor device, wherein the region and the third semiconductor region form a parasitic diode connected in parallel with the parasitic bipolar transistor between an input pad and a ground potential. 3. The semiconductor device according to claim 1, wherein the first semiconductor region is provided near the input pad. 4. The semiconductor device according to claim 1, wherein an N-type well region is formed inside said well region and in contact with a lower side of said first semiconductor region. 5. An N-type semiconductor substrate; a P-type first well region formed in a part of a surface region of the semiconductor substrate and supplied with a potential lower than a ground potential; A memory circuit that receives an external signal from an input pad; a second P-type well region formed in a part of a surface region of the semiconductor substrate; An N-type first semiconductor region formed in a portion and connected to the input pad; and a surface region of the second well region formed on both sides of the first semiconductor region, and a ground potential is applied. Was done
An N-type second semiconductor region; and a surface region of the second well region, which is formed in the vicinity of the second semiconductor region on a side opposite to the first semiconductor region side of the second semiconductor region. And the ground potential is applied to P
A first semiconductor region, a second well region, and a second semiconductor region forming a parasitic bipolar transistor between an input pad and a ground potential; A semiconductor device, wherein the region, the second well region, and the third semiconductor region form a parasitic diode connected in parallel with the parasitic bipolar transistor between an input pad and a ground potential. 6. An N-type semiconductor substrate, a P-type well region formed in a part of a surface region of the semiconductor substrate, and an external signal formed in a part of a surface region of the well region. and the N-type first semiconductor region which is connected to an input pad that, the surface area of the well region, wherein each are formed on both sides of the first semiconductor region, a second N-type ground potential is applied A semiconductor region, and a P-type third semiconductor formed in the surface region of the well region and near the second semiconductor region on the side opposite to the first semiconductor region side of the second semiconductor region. And a resistance element having one end connected to the third semiconductor region and the other end connected to the ground potential, wherein the first semiconductor region, the well region, and the second semiconductor region are connected to an input pad. Parasitic bipolar transistor between ground potential The semiconductor device, wherein the first semiconductor region, the well region, and the third semiconductor region form a parasitic diode connected in parallel with the parasitic bipolar transistor between an input pad and a ground potential. 7. An N-type semiconductor substrate; a P-type first well region formed in a part of a surface region of the semiconductor substrate and supplied with a potential lower than a ground potential; A memory circuit that receives an external signal from an input pad; a second P-type well region formed in a part of a surface region of the semiconductor substrate; An N-type first semiconductor region formed in a portion and connected to the input pad; and a surface region of the second well region formed on both sides of the first semiconductor region, and a ground potential is applied. Was done
An N-type second semiconductor region; and a surface region of the second well region, which is formed in the vicinity of the second semiconductor region on a side opposite to the first semiconductor region side of the second semiconductor region. A third P-type semiconductor region, and a resistance element having one end connected to the third semiconductor region and the other end connected to the ground potential, wherein the first semiconductor region, the second The well region and the second semiconductor region form a parasitic bipolar transistor between the input pad and the ground potential, and the first semiconductor region, the second well region and the third semiconductor region form the parasitic bipolar transistor between the input pad and the ground potential. A semiconductor device, wherein a parasitic diode is formed in parallel with a parasitic bipolar transistor. 8. An N-type semiconductor substrate, a P-type well region formed in a part of a surface region of the semiconductor substrate and dedicated to a protection circuit and distinguished from other circuit regions, and a surface of the well region. An N-type first semiconductor region formed in a part of the region and connected to an input pad to which an external signal is input; and an N-type first semiconductor region formed on both sides of the first semiconductor region in a surface region of the well region; Ground potential is applied respectively
An N-type second semiconductor region; and a P-type third semiconductor provided in a surface region of the well region and in contact with the second semiconductor region and surrounding the first and second semiconductor regions. And a resistor element having one end connected to the third semiconductor region and the other end connected to the ground potential, wherein the first semiconductor region, the well region, and the second semiconductor region are connected to an input pad. A parasitic bipolar transistor is formed between a ground potential, the first semiconductor region, the well region, and the third semiconductor region form a parasitic diode between an input pad and a ground potential, and a cathode of the parasitic diode is connected to the parasitic bipolar transistor. A semiconductor device directly connected to a collector of the semiconductor device.