JP3033346B2 - Sample hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit.

[0002]

2. Description of the Related Art As a conventional technique, as shown in FIG. 5, after a switch 4 is turned on to charge an input voltage Vin to a capacitor 6, the switch 4 is turned off to hold the voltage charged in the capacitor 6. Is what you do.

[0003]

In the prior art, a part of a control signal leaks to an output terminal side of the switch through a parasitic capacitance of a transistor constituting a switch, so that a voltage between an input voltage and an output voltage is increased. An error occurs, and it is difficult to maintain an output voltage equal to the input voltage.

The present invention solves such a problem. As shown in FIG. 4, means for outputting a voltage difference and at least two equivalent switches which are controlled by the same control signal and have different inputs are used. It is an object of the present invention to provide a sample-and-hold circuit having a sufficiently small error between the input voltage and the output voltage.

[0005]

According to the present invention, there is provided a sample and hold circuit which samples a signal potential based on a control signal, and holds and outputs the signal potential for a certain period of time. A first switch controlled by a signal, a second switch that receives a second signal potential, and a second switch that is controlled by the control signal, and a second charge holding unit that holds an output potential of the second switch A first charge holding unit that holds an output potential of the first switch and has a charge capacity substantially twice that of the second charge holding unit; and an output potential of the first charge holding unit. A first operational amplifier having an input as an input, a second operational amplifier having an output of the second charge holding means as an input,
And a means for outputting a difference between the output potentials of the first and second charge holding means. Further, the second signal potential is a reference potential.

[0006]

In the sample hold circuit configured as described above, the difference between the output voltages of the charge holding means controlled by the same control signal and holding the output voltages from at least two equivalent switches having different inputs is determined. Output.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments. FIG. 1 is a block diagram of a sample and hold circuit according to an embodiment of the present invention. 1 is an input terminal, 2 is a control signal, and 3 and 4 are switches composed of transistors and equivalent to each other, and are controlled by the control signal 2. An external signal is applied to the input of the switch 3, and the input of the switch 4 is grounded to GND.
Reference numerals 5 and 6 denote capacitors for holding the output voltages of the switches 3 and 4, respectively.
Ch: Ch is 2: 1. 7 is a means for outputting the difference between the output voltages of the capacitors 5 and 6, and 8 is an output terminal.

FIG. 2 shows the switches 3 and 4 in FIG. 2 is a control signal for turning on and off the switch, 21 and 22 are P-type and N-type MOS transistors, respectively, and 23 and 24 are between the gate and drain or between the source and drain of the P-type and N-type MOS transistors, respectively. The parasitic capacitances 23 and 24 are determined by the parasitic capacitances Cp and Cn.
, A part of the control signal 2 leaks to the output terminal side.

FIG. 3 shows an example of the input / output relationship of the switch shown in FIG. 2. Reference numeral 30 denotes an input waveform to the input terminal 1, 33 denotes the control signal 2 through the parasitic capacitances Cp and Cn. Is an output waveform corresponding to the input waveform 30, and a waveform 33 is added thereto. 31 is the waveform of the control signal 2,
Numeral 32 denotes a waveform that should be originally output with respect to the input signal 30.

FIG. 4 shows an example of a subtractor 7 for outputting the difference between the output voltages of the capacitors in FIG. 40, 41
Is an operational amplifier, 42 is a resistor and the resistance values are all equal.

Assuming that the input voltages of the operational amplifiers 40 and 41 are Vi 1 and Vi 2, respectively, and the charge when a part of the control signal 2 leaks to the output terminal side through the parasitic capacitances 23 and 24 is Q, FIG. , Vi1 = Q / 2Ch + Vin (1) Vi2 = Q / Ch (2), and Q / 2Ch and Q / C in equations (1) and (2), respectively.
h represents an error voltage generated by the switches 2 and 3.

The closed-loop gain G1 of the operational amplifier 40 is given by: G1 = 1 + R / R = 2 (3) The closed-loop gain G2 of 41 is given by: G2 = -R / R = -1 (4)

Therefore, assuming that the output voltages of the operational amplifiers 40 and 41 are Vo1 and Vo2, respectively, Vo1 = Vi1 × G1 + Vo2 (5) Vo2 = Vi2 × G2 (6) The output voltage of the subtractor is represented by Vout. Then, Vout = (R / 2R) × Vo1 = R / 2R {(Q / 2Ch + Vin) × (1 + R / R) −Q / Ch × 1} = 1/2 (Q / Ch + 2Vin−Q / Ch) = Vin ( 7), and Q / 2Ch, Q / in equations (1) and (2), respectively.
Ch is canceled and an output voltage equal to the input voltage appears at the output terminal, and no error occurs between the input voltage and the output voltage.

[0014]

As described above, the sample and hold circuit of the present invention cancels an error voltage caused by a part of the control signal leaking to the output terminal through the parasitic capacitance of the transistor constituting the switch.

Therefore, no error occurs between the input voltage and the output voltage, and the output voltage equal to the input voltage can be maintained. This is effective especially when a minute voltage which is easily affected by the error voltage is input. is there.

Further, even if the parasitic capacitance of the switch fluctuates due to the fluctuation of the power supply voltage, the ambient temperature, the fluctuation of the process, and the like, there is an effect that it is hardly affected by the fluctuation.

[Brief description of the drawings]

FIG. 1 is a block diagram of a sample and hold circuit according to the present invention.

FIG. 2 is a detailed view of a switch unit in FIG.

FIG. 3 is a view showing an example of input and output to and from the switch in FIG. 2;

FIG. 4 is a diagram of a means for outputting a difference between output voltages according to the embodiment of the present invention.

FIG. 5 is a block diagram of a sample and hold circuit according to a conventional technique.

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Control signal 3, 4 Switch 5, 6 Output means for outputting difference between output voltages of capacitors 7 5, 6 8 Output terminal 21 P-type MOS transistor 22 N-type MOS transistor 23 Parasitic capacitance (P MOS transistor) 24 Parasitic capacitance (N-type MOS transistor) 30 Example of input waveform 31 Example of control signal 32 Example of waveform to be output 33 Example of error waveform 34 Output waveform for 30 40, 41 Operational amplifier 42 Resistance

Claims (2)

(57) [Claims] 1. A sample-and-hold circuit for sampling a signal potential based on a control signal, holding the output for a fixed time, and outputting the first signal potential, a first switch controlled by the control signal, 2, a second switch controlled by the control signal, a second charge holding unit for holding an output potential of the second switch, and holding an output potential of the first switch. A first charge holding means having a charge capacity substantially twice that of the second charge holding means; a first operational amplifier having an input of an output potential of the first charge holding means; A second operational amplifier that receives the output potential of the charge holding unit as an input; and a resistor that is substantially equivalent to each other, and outputs a difference between the output potentials of the first and second charge holding units. Means and A sample-and-hold circuit. 2. The sample and hold circuit according to claim 1, wherein said second signal potential is a reference potential.