JP3028746B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mask ROM, EP
The present invention relates to a semiconductor memory device such as a ROM and an EEPROM, and more particularly to a semiconductor memory device that facilitates a test for an initial failure.

[0002]

2. Description of the Related Art Mask ROMs have become
It has become very difficult to analyze chip failures. For example,
NAND type mask RO made by submicron rule
It is very difficult to optically observe the M chip to find a defect. Normally, for screening, an electrical check (die sort) is performed to determine whether there is a defective bit by reading memory data before cutting a chip from a wafer. At this time, even if there is a defect of a plurality of bits, it is not easy to determine whether the defect is a writing defect of a memory cell, a word line defect, or a bit line defect. It is possible to perform a scramble process to change to a bit pattern corresponding to the layout on the actual chip and calculate whether a defect of a plurality of bits is along the word line direction or the bit line direction by calculation. take time. Even if a defect in the word line direction is known, it is difficult to determine whether the word line is open or short.

[0003]

As described above, in the conventional semiconductor memory device, failure analysis becomes difficult due to miniaturization of elements. The present invention has been made in view of the above points, and has as its object to provide a semiconductor memory device that facilitates word line failure analysis.

[0004]

SUMMARY OF THE INVENTION The present invention provides an N-stage NAND type memory cell array in which memory cells are arranged at intersections of a plurality of word lines and bit lines, and a word for selectively driving a word line. in a semiconductor memory device having a line selection circuit, and a sense amplifier circuit for reading bit line data, distribution to the word line terminating portion of the memory cell array
To detect open or short of N word lines.
N-stage NAND type having N pairs of bit lines for output
Having a configuration and patterns that are opposite to each other with respect to each bit line pair.
A test memory cell array in which test data has been written with down, and a test for the sense amplifier circuit for reading bit line data of the test memory cell array Yes
It is characterized in that.

In the present invention, preferably, the test
Select one of the bit line pairs of the memory cell array for
Bit line for connecting to the test sense amplifier circuit
It has a selection circuit. In the present invention,
For example, the test memory cell array has N words.
When paying attention to a certain word line among word lines, this word line
First and second vias of a bit line pair for checking for
The word line of interest and the first bit
The memory cell at the intersection with the gate line is of the E type,
The remaining memory cells along one bit line are D-type.
The intersection between the word line of interest and the second bit line
Memory cells are of the D type, and the second bit line
The remaining memory cells along are tested to be of E type.
Data pattern is written.

[0006]

According to the present invention, a test memory cell array in which a predetermined test data pattern has been written is arranged at the word line end portion, and the data line can be read to easily check the open defect and the short defect of the word line. it can.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a NAN according to an embodiment of the present invention.
2 is a block diagram of a main part of a D-type mask ROM. As illustrated, a plurality of word lines WL (WL0, WL1,
..) And bit lines BL (BL0, BL1,...), Each having a memory cell arranged therein, a memory cell array 11 in which data is mask-programmed, a word line selection circuit 12 for selectively driving the word line, a bit line Selection circuit 1
3, and a sense amplifier circuit 14 for reading data of the selected bit line.

At the end of the word line WL of the memory cell array 11, a test memory cell array 15 driven by these word lines WL and having the same memory cells as the memory cell array 11 arranged in a predetermined data pattern is provided. Have been. A bit line selection circuit 16 and a sense amplifier circuit 17 are also provided for the test memory cell 15.

FIG. 2 shows a specific configuration of the memory cell array 11 and the test memory cell array 15 in the case of an 8-stage NAND type mask ROM. As shown in the figure, eight memory MOS transistors adjacent to each other are connected in series so as to share a source and a drain and are connected to one bit line. Each memory MOS transistor of the memory cell array 11 is set to the D type by, for example, selective ion implantation, or remains in the E type state having a high threshold voltage. The memory transistors circled in FIG. 2 are D-type, and the others are E-type.
Type.

In the test memory cell array 15, eight pairs of bit lines are prepared for eight word lines WL. Data is written in the eight word lines WL in a data pattern necessary to detect open or short. FIG. 3 shows the data pattern. The circles in FIG. 3 correspond to the circles in FIG. 2 and indicate that the memory MOS transistor there is a D type.

For example, focusing on the bit line pair BL01 and BL02 of the test memory cell array 15, the bit line pair BL01 and BL02 is for testing the word line WL7.
When viewed along BL01, only the intersection with WL7 is of E type, the others are of D type, and along BL02, the pattern is reverse to that of BL01. Next bit line pair BL11 and BL
Numeral 12 is for inspecting the word line WL6, and when viewed along BL11, only the intersection with WL6 is of E type, the others are of D type, and along BL12, the pattern is reverse to that of BL11. Hereinafter, similarly, test data are written in reverse patterns along one pair of bit lines so that one is of the E type and the other is of the D type.

As shown in FIG. 3, the sense amplifier circuit 17 includes sense amplifiers SA0, SA0 provided for each bit line pair.
SA1,... As the bit line selecting circuit 16, there are provided select gate MOS transistor pairs (S00, S01), (S10, S11),... For selectively connecting one of the bit line pairs to the sense amplifiers SA0, SA1,. . These select gate MOS transistor pairs are selected by select gate lines S0 and S1.

With such a configuration, at the time of die sorting after the completion of the wafer process, the word lines WL are
Is checked. The defect check of the word line WL7 will be described. First, the word line WL7 =
“H”, WL0 to WL6 = “L”, and select gate lines S0 = “H”, S1 = “L”. Under this condition, if there is no defect such as open or short-circuit of the word line WL7, all the memory MOS transistors along the bit line BL01 conduct, and the current amplifier draws the sense amplifier SA0.
Is at the "L" level. At this time, since the other sense amplifiers SA1 to SA7 do not draw current,
These input nodes remain at "H".

When the word line WL7 is open or short-circuited with the adjacent word line WL6, the memory MOS transistor at the intersection of the word line WL7 and the bit line BL01 is not turned on or has an intermediate potential together with the adjacent word line WL6.
A memory transistor at the intersection of WL7 and BL01;
The memory transistors 6 and BL11 are turned on at the same time, and current is drawn in these bit lines BL01 and BL11. The former can be detected by reading the output of the sense amplifier SA0, and the latter can be detected by obtaining the same output from the two sense amplifiers SA0 and SA1. From the above, it can be determined whether the word line WL7 is open or short-circuited or normal.

The open defect or short defect of the word line WL7 is determined in the opposite manner to the above case.
This is also performed by setting “L”, WL0 to WL6 = “H”, and setting the selection gate line to S0 = “L” and S1 = “H”. Under this condition, even if the word line WL7 is open, if the other word lines are normal, all the memory MOS transistors along the bit line BL02 are turned on.
The potential at the input node of A0 drops. At this time, no current is drawn in the other sense amplifiers SA1 to SA7. If the word lines WL7 and WL6 are short-circuited, the potential of the word line WL6 drops, the E-type memory MOS transistor on the word line WL6 cannot be conducted, and there is no current draw at the input node of the sense amplifier SA0. Either the word lines WL6 and WL7 are at an intermediate potential and the memory transistors at the intersections of the bit lines BL01 and BL11 and these word lines are turned on, and the same output is obtained at the sense amplifiers SA0 and SA1. It will be. This allows
It can be determined whether the word line WL7 is open or short-circuited.

The same applies to other word lines WL6, WL5,. That is, the selection gate line is set to S0 = “H”, S
1 = “L”, the word lines are sequentially changed to “H” one by one, and the scan for keeping the rest at “L” is performed.
By setting the word lines to "L" one by one and setting the remaining word lines to "L" one by one while setting "L" and S1 = "H", the output of the sense amplifiers SA0, SA1,. , WL6,... Can be inspected for open or short-circuit defects.

As described above, according to this embodiment, a test memory cell array in which a predetermined test data pattern has been written can be arranged at the end of a word line to easily check for an open or short failure of a word line. it can. The memory cell array for test has 16 bit lines in the case of an 8-stage NAND type memory and 32 bit lines even in the case of a 16-stage NAND type memory, and its area is ignored with respect to the area of the original memory cell array. Since it is as small as possible, an increase in chip area is of little concern. Also, the data of the test memory cell is only tested by the probe at the wafer stage during die sort,
Output terminals after packaging are of course not required.

The present invention is not limited to the above embodiment. For example, in the embodiment, the NAND type mask ROM has been described.
The present invention can be similarly applied to a PROM or an EEPROM, or to a case where a NOR type memory cell configuration is used.

[0019]

As described above, according to the present invention, a test memory cell array in which a predetermined test data pattern has been written is arranged at the word line end portion, and the data read out thereof makes it easy to open the word line. In addition, a semiconductor memory device capable of checking for short-circuit failure can be obtained.

[Brief description of the drawings]

FIG. 1 shows a main configuration of a mask ROM according to an embodiment of the present invention.

FIG. 2 shows a configuration of a memory cell array and a test memory cell array of the embodiment.

FIG. 3 shows a configuration of a test memory cell array of the embodiment.

[Explanation of symbols]

11: memory cell array, 12: word line selection circuit, 1
3 ... bit line selection circuit, 14 ... sense amplifier circuit, 15
… Test memory cell array, 16… bit line selection circuit, 17… sense amplifier circuit.

Claims (5)

(57) [Claims] An N-stage NAND type memory cell array in which memory cells are arranged at intersections of a plurality of word lines and bit lines, and a word line selection circuit for selectively driving word lines And a sense amplifier circuit that reads out bit line data, wherein the semiconductor memory device is disposed at a word line end of the memory cell array ,
To detect open or short of N word lines
N-stage NAND type configuration having N pairs of bit lines
And have patterns opposite to each other for each bit line pair.
The semiconductor memory device characterized by having a test memory cell array in which data has been written for the test, a test for the sense amplifier circuit for reading bit line data of the test memory cell array Te. 2. The semiconductor memory device according to claim 1, further comprising a bit line selection circuit for selectively connecting one of a bit line pair of said test memory cell array to said test sense amplifier circuit. . 3. The test memory cell array includes N
When attention is paid to a certain word line among the word lines, regarding the first and second bit lines of the bit line pair for inspecting a defect of the word line, the word line of interest and the first bit line Are of the E type, the remaining memory cells along the first bit line are of the D type, and the memory cell at the intersection of the word line of interest and the second bit line is 2. The semiconductor memory device according to claim 1, wherein a test data pattern is written so that the remaining memory cells along the second bit line are of the D type and are of the E type. 4. The test method for a semiconductor memory device according to claim 3, wherein the word line of interest has an “H” level at which an E-type memory cell is conductive, and the remaining word lines have an E-type memory cell. Is supplied with an “L” level that does not conduct, the open defect of the word line of interest is checked by reading data of the first bit line, and the word line of interest is checked by reading the data of the first and second bit lines. A test method for a semiconductor memory device, wherein a short-circuit defect with an adjacent word line adjacent to the word line is inspected. 5. The test method for a semiconductor memory device according to claim 3, wherein the word line of interest has an “L” level at which no E-type memory cell conducts, and the remaining word lines have an E-type memory cell. Is turned on, an "H" level is applied, and the quality of word lines other than the word line of interest is checked by reading data of the second bit line, and attention is paid by reading data of the first and second bit lines. A test method for a semiconductor memory device, wherein a short-circuit failure between a word line and an adjacent word line adjacent to the word line is inspected.