JP3019493U - High frequency multiplier - Google Patents

Abstract

(57) [Abstract] [Purpose] Performs integer multiplication of 2 except 2 with a simple circuit configuration while maintaining a minute level of the signal. A source signal in a high frequency band is applied to the base of a transistor Q, and a tuning circuit 13 that resonates at a frequency four times the frequency of the source signal is connected to the collector. Then, in the plane where the base voltage is the horizontal axis and the collector current is the vertical axis, the operating point of the transistor Q is set near the maximum value of the second derivative of the curve showing the relationship between the base voltage and the collector current of the transistor Q. ..

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a high-frequency multiplier circuit in which a source signal in a high-frequency band is applied to the base of a transistor, and a collector is connected to a tuning circuit that resonates at a frequency that is an integer multiple of 2 except 2 of the frequency of the source signal. .

[0002]

[Prior art]

 One of the conventional techniques for multiplying a signal in a high frequency band is a PLL circuit including a phase comparator, a loop filter, a charge pump, and a VCO. However, this PLL circuit is expensive because the circuit configuration is complicated. Further, when the signal to be handled is an analog signal, it is necessary to shape the analog signal with a sufficient amplitude into a digital signal, which further complicates the circuit configuration. Therefore, the PLL circuit is rarely used for multiplication of the analog signal except when the phase relationship between the source signal and the multiplied signal is made to be a strict relationship.

A conventional technique used exclusively for multiplication of an analog signal is to generate a signal containing many harmonics by operating a transistor in class C, and set the frequency of a tuning circuit connected to a collector to a desired frequency. Therefore, there is a circuit that multiplies the source signal. Also, by removing the half-wave component of the guided signal, a signal containing a large number of even-numbered harmonics is generated, and the tuning circuit provided in the subsequent stage is set to the desired frequency to perform multiplication. There is a diode multiplier circuit.

[0004]

[Problems to be solved by the device]

 However, in a circuit that operates a transistor in class C, it is necessary to set the level of the source signal applied to the base to a sufficiently large level because the operating point is set to class C. Therefore, the level of the harmonic signal generated in the collector is also extremely high. This means that when used in a device that handles very small signals, such as a receiver or receiver, it does not want to receive unwanted signals internally. There was a problem that it was necessary to sufficiently shield the coil to be used.

Further, in the diode multiplication circuit, since the diode is a passive element, the attenuation of the signal at the time of multiplication is large. Therefore, it is necessary to provide an amplifier circuit in the preceding stage and give a source signal with a sufficient level to the diode multiplying circuit, or a amplifying circuit in the latter stage for amplifying the multiplied signal. Therefore, there has been a problem that the circuit configuration for multiplication becomes complicated.

The present invention was devised to solve the above-mentioned problems, and the object of the invention as set forth in claim 1 is to provide 2 with a simple circuit configuration while maintaining a minute level of a signal. Another object is to provide a high-frequency multiplier circuit capable of performing an even multiplication except the above.

Another object of the present invention is to provide a high-frequency multiplier circuit capable of accurately setting the operating point to a predetermined operating point even when the hfe of the transistor varies.

[0008]

[Means for Solving the Problems]

 In order to solve the above-mentioned problems, in a high-frequency multiplier circuit according to the invention of claim 1, a high-frequency source signal is applied to the base of the transistor, and the collector of the transistor is an integer of 2 excluding 2 of the frequency of the source signal. It is applied to a high-frequency multiplier circuit in which a tuning circuit that resonates at a double frequency is connected.The relationship between the base voltage of a transistor and the collector current of a transistor is plotted on a plane with the base voltage on the horizontal axis and the collector current on the vertical axis. The operating point of the transistor is set near the maximum value of the second derivative of the curve.

According to a second aspect of the high-frequency multiplier circuit of the present invention, the base of the transistor is connected to a power source for applying a potential to the collector of the transistor via a base resistor, and a collector current corresponding to a desired operating point of the transistor is connected. The value is set according to the resistance value of the emitter resistor connected to the emitter.

[0010]

[Action]

 The operation of the device according to claim 1 will be described below. The first derivative of the curve showing the relationship between the base voltage and the collector current means that the linearity of amplification is good when the coefficient is constant, and the coefficient shows the amplification factor. Further, the fact that the primary differential coefficient is constant means that the secondary differential coefficient is zero. From the opposite point of view, the operating point where the second derivative is the maximum means the operating point that gives the maximum distortion. In addition, the collector current of the transistor is uniquely increased in response to the increase in the base voltage. Therefore, the operating point where the second derivative is the maximum is the operating point where the distortion with the most asymmetric waveform is obtained. In other words, it is an operating point where more even harmonics can be obtained. Further, since this operating point is in the class A operating region, it is possible to obtain a signal with a predetermined distortion without being affected by the magnitude of the input signal level.

The operation of the device according to claim 2 will be described below. The transistor may be any type of NPN type or PNP type, but for simplicity of explanation, the case where the transistor is an NPN type will be described below. The base of the transistor is connected through a base resistor to a power supply that applies a potential to the collector of the transistor. For this reason, when the hfe of the transistor varies to the large side, the base current decreases and the base potential is displaced in the direction of increasing. Further, when hfe varies to the smaller side, the base current increases and the base potential is displaced to the lower side. However, since the operating point of the transistor is an operating point where the collector current is very small, the resistance value of the emitter resistance that sets the collector current is large. Therefore, the potential of the emitter is largely displaced by the minute displacement of the emitter current. Therefore, even if the base current corresponding to the desired collector current is displaced by a very small amount from the desired current value, the potential of the emitter shifts so as to follow variations in the base potential. Also, the influence of the displacement of the base current on the collector current at this time is insignificant. For this reason, the base-emitter voltage, which is the base voltage of the transistor, is set to a voltage corresponding to the collector current with a slight fluctuation. That is, even when hfe varies, the operating point of the transistor is set near the desired operating point.

[0012]

【Example】

 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an electrical connection of an embodiment of a high frequency multiplier circuit according to the present invention.

The present embodiment is an apparatus in which a television receiver, a video tape recorder, or a video tape recorder and a television receiver are integrally incorporated, and an image by a received video signal, a number or a character indicating a channel, etc. It is part of the device that displays information on the screen in parallel. That is, this embodiment is roughly classified into a high-frequency signal source 11 that outputs a signal that is phase-synchronized with the received video signal (phase-synchronized in which a constant phase difference is maintained), and four capacitors C1 to C4. A high-frequency multiplier circuit consisting of three resistors R1 to R3, a coil L, and a transistor Q, which multiplies the source signal by four, and a signal that has been multiplied by four by the high-frequency multiplier circuit as a reference clock, in parallel with the received video signal. The on-screen circuit 12 generates a video signal such as a character to be displayed subsequently. The high frequency multiplying circuit is not limited to one that multiplies the source signal by four, but includes one that performs even multiplication such as six and eight.

In the figure, a high-frequency signal source 11 is a block provided in a chroma circuit that reproduces a color signal from a received video signal. As a signal phase-synchronized with the video signal, a color subcarrier is used. And a source signal having a frequency that is in phase synchronization with the color subcarrier and whose frequency is four times the frequency of the color subcarrier. Then, the generated source signal is sent to the base of the transistor Q via the capacitor C1. It also sends the generated color sub-carrier wave to the chroma circuit body (the color sub-carrier and the chroma circuit body are not shown).

The transistor Q is an element that generates a harmonic of an even multiple by applying asymmetrical distortion to the source signal transmitted from the high frequency signal source 11. The collector of the transistor Q is connected to one terminal of the tuning circuit 13 composed of the capacitor C2 and the coil L. The other terminal of the tuning circuit 13 is connected to a plus power source P + which is a 5V power source. The tuning frequency of the tuning circuit 13 is set to be four times the frequency of the source signal.

The base of the transistor Q is connected to a plus power source P + that gives a potential to the collector via a base resistor R1. The emitter of the transistor Q is grounded via an emitter resistor R2 for setting the collector current of the transistor Q to a predetermined value. The emitter of the transistor Q is grounded via a series circuit of a capacitor C4 and a resistor R3.

For the capacitor C4, a value that sufficiently reduces the impedance is adopted in a predetermined band which is a frequency higher than the frequency of the source signal. Therefore, in the predetermined band, the emitter is grounded via the resistor R3. As a result, the transistor Q is only provided with current feedback by the resistor R3 in the predetermined band. Further, in terms of direct current, current feedback is given by the resistor R2. The resistor R3 is a resistor for reducing the variation of the amplification factor caused by the variation of hfe of the transistor Q, and gives a small amount of current feedback to the transistor Q in a predetermined band. Therefore, a small resistance value is used for the resistance of the resistor R3.

Further, the on-screen circuit 12 to which the collector of the transistor Q is connected via the capacitor C3 is phase-locked with the color subcarrier and operates with a signal having a frequency four times as high as the color subcarrier as a reference clock. Then, in parallel with the display of the received video signal, it is a block for generating a signal for displaying a character or a symbol. The content displayed by the generated signal is a number indicating the channel during remote control, a symbol indicating the volume, or characters indicated by the character data received during the blanking period.

FIG. 2 is an explanatory diagram showing a method of determining the operating point of the transistor Q. A curve a shown in the same figure is a curve showing the characteristics of the transistor Q shown on a plane in which the horizontal axis represents the base voltage and the vertical axis represents the collector current. Further, the curve b shows the change in the primary differential coefficient of the curve a. Further, the curve c shows the change of the second derivative of the curve a.

The first-order differential coefficient indicated by the curve b indicates that the region where the coefficient is constant is a region where the linearity of amplification is good, and the value of the coefficient indicates the amplification factor in the corresponding region. Further, the fact that the primary differential coefficient is constant means that the secondary differential coefficient has a value near 0, as shown by the curve c. From the opposite point of view, the operating point 21 (base voltage is V1, collector current is I1) at which the second-order differential coefficient is maximum means that the operating point gives the maximum distortion. .

Further, as shown by the curve a, the collector current of the transistor is uniquely increased as the base voltage increases, corresponding to this increase. Therefore, it means that the operating point 21 where the second derivative is the maximum is the operating point where the most asymmetric distortion of the waveform is obtained. In other words, it is an operating point where more even harmonics can be obtained. Moreover, since the operating point 21 is in the class A operating region, the input signal level is not limited, and a signal with a predetermined distortion can be obtained at an arbitrary input level of the source signal.

As a method of setting the operating point of the transistor Q to the operating point 21 described above, in this embodiment, a method of setting the collector current by the resistance value of the emitter resistor R2 is adopted. That is, the value of the collector current I1 corresponding to the operating point 21 of the transistor Q shown in FIG. 1 is about 300 μA, the voltage of the positive power source P + is 5 V, and the collector-emitter voltage at the operating point 21 is about 5 V. Since it is 0.5 V, the value of the emitter resistance R2 is set to 15 KΩ in order to set the collector current to 300 μA.

The value of the base resistance R1 that connects the base of the transistor Q to the positive power source P + is selected from a relatively wide range of values because a large amount of current feedback is given by the emitter resistance R2. In this embodiment, the value of the base resistor R1 is set to 15 KΩ which is the same as the value of the emitter resistor R2. Further, the value of the resistor R3 for reducing the variation of the amplification factor caused by the variation of hfe of the transistor Q is 100Ω.

The operation of the embodiment having the above configuration will be described below. The base of the transistor Q is connected to the plus power source P + via the base resistor R1. For this reason, when the hfe of the transistor Q varies to the larger side, the base current decreases and the base potential is displaced in the direction of increasing. Further, when hfe varies toward the smaller side, the base current increases and the base potential is displaced toward the lower side. However, since the operating point of the transistor Q is the operating point 21 where the collector current becomes minute, the resistance value of the emitter resistor R2 that sets the collector current is as large as 15 KΩ. Therefore, the potential of the emitter is largely displaced by the minute displacement of the emitter current.

Assuming now that the potential of the emitter of the transistor Q is a potential corresponding to the standard value of hfe, when hfe is larger than the standard value, the base current is the desired current corresponding to 300 μA of the desired collector current. More than the value (300 / hfe). However, since the base current has increased only slightly more than the desired current value and the value of the emitter resistance R2 is large, the potential of the emitter greatly increases. As a result, feedback occurs in which an increase in the base current is suppressed by an increase in the emitter potential, and the emitter potential is displaced so as to follow variations in the base potential.

Therefore, the base-emitter voltage, which is the base voltage of the transistor Q, is set to a voltage corresponding to the collector current, which has a slight variation. That is, even when hfe varies, the operating point of the transistor is set near the desired operating point 21, and the collector current has a value near 300 μA. This also applies when hfe is smaller than the standard value. That is, even if the hfe of the transistor Q varies, the operating point of the transistor Q is set near the desired operating point 21.

FIG. 3 is an explanatory diagram showing a source signal waveform given to the base of the transistor Q and a signal waveform appearing at the collector.

The operating point of the transistor Q is set near the operating point 21 as described above. The source signal, which is a sine wave transmitted from the high-frequency signal source 11, has a pp value of about 0.4 to 0.5 V, as indicated by the waveform d, in order to prevent unwanted signals from radiating into the device. It is a very low level signal. Then, the source signal d having this minute level is transferred by the curve a showing the characteristics of the base voltage and the collector current of the transistor Q and appears at the collector. Therefore, the signal waveform appearing at the collector becomes a waveform that is greatly asymmetrically distorted, as shown by the waveform e, and is a signal containing a large amount of even-numbered harmonics. Further, the signal level becomes a signal of a minute level with a pp value of about 1V.

On the other hand, a tuning circuit 13 that resonates at a frequency four times as high as the source signal is connected to the collector of the transistor Q. The tuning circuit 13 has the maximum impedance at a frequency four times as high as the source signal. Therefore, the tuning circuit 13 emphasizes only the signal level (voltage) of the four times higher harmonic component among the signals represented by the waveform e. As a result, a signal obtained by multiplying the source signal by 4 is output from the collector of the transistor Q. The signal multiplied by 4 is guided to the on-screen circuit 12 and used as a basic clock signal.

As described above, the television receiver, the video tape recorder, or the device in which the video tape recorder and the television receiver are integrally incorporated in the present embodiment is phase-synchronized with the color sub-carrier and A high frequency signal source 11 for outputting a signal having a frequency that is an integral multiple of 2 excluding 2 of the subcarrier as a source signal is provided. Further, the on-screen circuit 12 is provided with a high-frequency multiplier circuit for multiplying the source signal by an integer multiple of 2 except 2, and the on-screen circuit 12 uses the signal obtained by multiplying 2 by 2 by the high-frequency multiplier circuit as a basic clock.

Therefore, the signal given to the on-screen circuit 12 becomes a signal which is phase-synchronized with the color signal of the image signal with a constant phase difference. This means that it is not necessary to generate the basic clock (clock that is phase-synchronized with the color signal of the image signal), which is indispensable for on-screen display in which characters and the like are displayed together with the received image. Therefore, the on-screen circuit 12 does not require a circuit block such as a PLL circuit for performing phase synchronization, and thus the configuration of the on-screen circuit 12 is simplified.

Further, since the pp value of the voltage applied to the coil L constituting the tuning circuit 13 is as small as about 1 V, the signal level radiated from the coil L is low. As a result, the effect of unwanted side-effects on the image signal path is minimal, and it is possible to prevent the interference such as the occurrence of image stripes caused by the unwanted signals being incident on the device. It has gained.

[0033]

[Effect of device]

 In the high frequency multiplication circuit according to the invention as set forth in claim 1, a source signal in a high frequency band is applied to the base of the transistor, and the collector of the transistor is tuned to resonate at an integer multiple of 2 excluding 2 of the frequency of the source signal. It is applied to the high-frequency multiplier circuit to which the circuit is connected. Then, on the plane where the base voltage is on the horizontal axis and the collector current is on the vertical axis, the operating point of the transistor is located near the maximum value of the second derivative of the curved line showing the relationship between the base voltage of the transistor and the collector current of the transistor. It is set. As a result, an asymmetrically distorted waveform appears at the collector even when the input signal is at a very low level. Therefore, it is possible to perform doubling with a simple circuit configuration while maintaining a very low level of the signal. It is possible.

According to a second aspect of the high-frequency multiplier circuit of the present invention, the base of the transistor is connected to a power source for applying a potential to the collector of the transistor via a base resistor, and a collector current corresponding to a desired operating point of the transistor is connected. The value is set by the resistance value of the emitter resistor connected to the emitter. Therefore, the resistance value of the emitter resistance increases, and the amount of current feedback increases. This large amount of current feedback reduces the effect of variations in transistor hfe on the operating point. Therefore, even when the transistor hfe varies, the operating point can be set accurately to the specified operating point. It is possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing electrical connection of an embodiment of a high-frequency multiplier circuit according to the present invention.

FIG. 2 is an explanatory view showing a method of determining an operating point of the high frequency multiplier circuit according to the present invention.

FIG. 3 is an explanatory view showing a signal waveform of a base and a signal waveform of a collector of the high frequency multiplier circuit according to the present invention.

[Explanation of symbols]

 11 high-frequency signal source 12 on-screen circuit 13 tuning circuit Q transistor R1 base resistance R2 emitter resistance a curve showing the relation between base voltage and collector current b first derivative c second derivative

Claims (2)

[Scope of utility model registration request] 1. A high-frequency source signal is applied to a base of a transistor, and a tuning circuit is connected to a collector of the transistor, the tuning circuit resonating at a frequency that is an integral multiple of 2 excluding 2 of the frequency of the source signal. In the multiplication circuit, in the plane where the horizontal axis represents the base voltage and the vertical axis represents the collector current, the transistor near the maximum value of the second derivative of the curve showing the relationship between the base voltage of the transistor and the collector current of the transistor A high frequency multiplication circuit characterized in that the operating point of is set. 2. The base of the transistor is connected to a power source for applying a potential to the collector of the transistor through a base resistor, and the collector current value corresponding to the desired operating point of the transistor is connected to the emitter of the emitter resistor. The high frequency multiplier circuit according to claim 1, wherein the high frequency multiplier circuit is set by a resistance value.