JP3011234B2 - Method and apparatus for detecting wire open in semiconductor device - Google Patents
Method and apparatus for detecting wire open in semiconductor deviceInfo
- Publication number
- JP3011234B2 JP3011234B2 JP9273184A JP27318497A JP3011234B2 JP 3011234 B2 JP3011234 B2 JP 3011234B2 JP 9273184 A JP9273184 A JP 9273184A JP 27318497 A JP27318497 A JP 27318497A JP 3011234 B2 JP3011234 B2 JP 3011234B2
- Authority
- JP
- Japan
- Prior art keywords
- pads
- semiconductor device
- lead
- wire open
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は，パワーＭＯＳＦＥ
Ｔ等のパワー半導体装置，その不良検出方法及びと不良
検出装置に関する。TECHNICAL FIELD The present invention relates to a power MOSFET.
TECHNICAL FIELD The present invention relates to a power semiconductor device such as T, a method for detecting a failure thereof, and a failure detection device.
【０００２】[0002]
【従来の技術】従来，パワーＭＯＳＦＥＴ（酸化金属電
界効果型トランジスタ）等のパワー半導体装置は，伝達
される電流が大きいため，図２に示すように，第１乃至
第３のデバイスセル（Ｍｆ１〜３）５２ａ，５２ｂ，５
２ｃに夫々接続された複数のパッド（Ｐａｄ１〜３）５
１ａ，５１ｂ，５１ｃとパッケージ５０のリード５４と
の間を結合する結合ワイヤ５３ａ，５３ｂ，５３ｃを複
数本にする必要性がある。パワー半導体装置は，複数の
結合ワイヤ５３ａ，５３ｂ，５３ｃに対応して複数のパ
ッド５１ａ，５１ｂ，５１ｃを持つ複数のデバイスセル
５２ａ，５２ｂ，５２ｃに分割されるが，ＤＣ及び高周
波（ＲＦ）動作の際のアンバランスを防ぐため，各デバ
イスセルの端で電極間金属配線５５ａ，５５ｂにより短
絡されている。2. Description of the Related Art Conventionally, a power semiconductor device such as a power MOSFET (Metal Oxide Field Effect Transistor) or the like transmits a large amount of current, and therefore, as shown in FIG. 3) 52a, 52b, 5
Plural pads (Pad 1 to Pad 3) 5 connected to 2c respectively
It is necessary to use a plurality of connecting wires 53a, 53b, 53c for connecting between the leads 1a, 51b, 51c and the leads 54 of the package 50. The power semiconductor device is divided into a plurality of device cells 52a, 52b, 52c having a plurality of pads 51a, 51b, 51c corresponding to a plurality of coupling wires 53a, 53b, 53c. In order to prevent imbalance at the time of the above, the device cells are short-circuited at the end of each device cell by the inter-electrode metal wires 55a and 55b.
【０００３】ここで，ワイヤ付着等のオープン不良があ
っても，複数のワイヤ５３ａ〜５３ｃの内，１本でも結
合されていれば正常なデバイス動作をするため，不良検
出ができない。ワイヤオープン不良のあるデバイスは，
短期的には正常動作をするが，ワイヤ５３ａ〜５３ｃの
安全に使用できる許容電流を越えているため，長期的に
は，ワイヤ破損を生じて正常なデバイス動作をしなくな
る。Here, even if there is an open defect such as wire adhesion, if at least one of the plurality of wires 53a to 53c is connected, a normal device operation is performed, so that a defect cannot be detected. Devices with wire open defects are:
Although the normal operation is performed in the short term, the current exceeds the allowable current of the wires 53a to 53c which can be safely used, and thus, in the long term, the wire is broken and the normal device operation is not performed.
【０００４】この欠点を解消するために，特開平８−５
１１９０号公報（従来技術１と呼ぶ）には，電圧レギュ
レーターを用いた検出方法が開示されている。[0004] To solve this disadvantage, Japanese Patent Laid-Open Publication No.
Japanese Patent Publication No. 1190 (referred to as Conventional Technique 1) discloses a detection method using a voltage regulator.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら，従来技
術１においては，検出端子間を定電圧にする用途のみに
限定され，通常のパワー半導体装置に適用できないとい
う欠点を有している。However, the prior art 1 has a drawback that it is limited to only a use where a constant voltage is applied between the detection terminals and cannot be applied to a normal power semiconductor device.
【０００６】また，従来技術１によるパワー半導体装置
の複数本の結合ワイヤ５３ａ〜５３ｃにおいて，結合ワ
イヤ５３ａ〜５３ｃが１本以上結合されていれば，短期
的にはデバイスは正常動作するために，ワイヤオープン
不良があっても，複数のうち１本だけでも，結合ワイヤ
５３ａ〜５３ｃが正常に結合されていれば不良検出がで
きないという欠点がある。In addition, if a plurality of connecting wires 53a to 53c of a plurality of connecting wires 53a to 53c of the power semiconductor device according to the prior art 1 are connected, the device operates normally in a short term. Even if there is a wire open defect, even if only one of the plurality is defective, the defect cannot be detected if the coupling wires 53a to 53c are normally coupled.
【０００７】そこで，本発明の技術的課題は，複数本の
ワイヤを使用するパワー半導体装置において，ワイヤオ
ープン不良を検出し，デバイスの長期正常動作の信頼性
を確保することができる半導体装置とそのワイヤオープ
ン検出方法と検出装置とを提供することにある。Accordingly, a technical problem of the present invention is to provide a power semiconductor device using a plurality of wires, which can detect a wire open defect and can ensure the reliability of long-term normal operation of the device and the semiconductor device. An object of the present invention is to provide a wire open detection method and a detection device.
【０００８】[0008]
【課題を解決するための手段】本発明によれば，デバイ
スセルに対応して設けられた複数の第１のパッドとパッ
ケージの単一の第１のリードとの間に，前記複数の第１
のパッドと同数の複数の第１の結合ワイヤを設けたパワ
ー半導体装置のワイヤオープンを検出する装置におい
て，更にワイヤオープン検出用の第２のリードとワイヤ
オープン検出用の第２のパッドとを第２の結合ワイヤを
介して設け，前記複数の第１のパッドと前記第２のパッ
ドとの間を，前記複数の第１のパッドと同数の抵抗を介
して接続し，前記第１のリードと前記第２のリードとの
間の抵抗値を基にワイヤオープン検出する構造を備えて
いることを特徴とする半導体装置のワイヤオープン検出
装置が得られる。According to the present invention, a plurality of first pads are provided between a plurality of first pads provided corresponding to device cells and a single first lead of a package.
In a device for detecting wire open of a power semiconductor device provided with a plurality of first connection wires of the same number as the number of pads, a second lead for wire open detection and a second pad for wire open detection are further provided. And two connection wires are provided, and the first and second pads are connected through the same number of resistors as the plurality of first pads. A wire open detection device for a semiconductor device is provided, which has a structure for detecting wire open based on a resistance value between the second lead and the second lead.
【０００９】また，本発明によれば，前記パワー半導体
装置のワイヤオープン検出装置において，前記各抵抗は
略同一抵抗値を有することを特徴とする半導体装置のワ
イヤオープン検出装置が得られる。According to the present invention, there is provided a wire open detection device for a semiconductor device, wherein the resistors have substantially the same resistance value in the wire open detection device for the power semiconductor device.
【００１０】ここで，本発明において，前記半導体装置
のワイヤオープン検出装置において，前記各抵抗値は，
構成する材料によるが，１０Ω〜１０ｋΩの範囲内であ
ることが好ましい。Here, in the present invention, in the wire open detection device of the semiconductor device, each of the resistance values is:
It is preferably in the range of 10 Ω to 10 kΩ, depending on the constituent material.
【００１１】また，本発明によれば，デバイスセルの複
数の第１のパッドと，パッケージの単一の第１のリード
との間に，前記複数の第１のパッドと同数の複数の第１
の結合ワイヤを設けたパワー半導体装置のワイヤオープ
ンを検出する方法において，更にワイヤオープン検出用
の第２のリードとワイヤオープン検出用の第２のパッド
とを設け，前記第１のパッドと前記第２のパッドとの間
を，前記第１のパッドと同数の抵抗を介して接続し，前
記第１のリードと前記第２のリードとの間の抵抗値を基
にワイヤオープン検出することを特徴とする半導体装置
のワイヤオープン検出方法が得られる。According to the present invention, a plurality of first pads of the same number as the plurality of first pads are provided between the plurality of first pads of the device cell and the single first lead of the package.
In the method for detecting a wire open of a power semiconductor device provided with the above-described coupling wire, a second lead for detecting a wire open and a second pad for detecting a wire open are further provided. The second pad is connected via the same number of resistors as the first pad, and wire open detection is performed based on a resistance value between the first lead and the second lead. And a wire open detection method for a semiconductor device.
【００１２】また，本発明によれば，前記半導体装置の
ワイヤオープン検出方法において，前記各抵抗に，略同
一抵抗値を有するものを使用することを特徴とする半導
体装置のワイヤオープン検出方法が得られる。Further, according to the present invention, there is provided a wire open detecting method for a semiconductor device, wherein the resistors having substantially the same resistance value are used for the respective resistors. Can be
【００１３】ここで，本発明のパワー半導体装置のオー
プン検出方法において，前記各抵抗値は，構成する材料
にもよるが，１０Ω〜１０ｋΩの範囲内であることが好
ましい。Here, in the open detection method for a power semiconductor device according to the present invention, it is preferable that each of the resistance values is in a range of 10 Ω to 10 kΩ, although it depends on a constituent material.
【００１４】また，本発明によれば，デバイスセルの複
数の第１のパッドとパッケージの単一の第１のリードと
の間に，前記複数の第１のパッドと同数の複数の第１の
結合ワイヤを設けた構造を備えた半導体装置において，
更にワイヤオープン検出用の第２のリードとワイヤオー
プン検出用の第２のパッドとを第２の結合ワイヤを介し
て設け，前記複数の第１のパッドと前記第２のパッドと
の間を，前記複数の第１のパッドと同数の抵抗を介して
接続し，前記第１のリードと前記第２のリードとの間の
抵抗値を基にワイヤオープン検出する構造を備えている
ことを特徴とする半導体装置が得られる。According to the present invention, between the plurality of first pads of the device cell and the single first lead of the package, the same number of the first pads as the plurality of first pads are provided. In a semiconductor device having a structure provided with connecting wires,
Further, a second lead for wire open detection and a second pad for wire open detection are provided via a second connecting wire, and a plurality of first pads and a second pad are provided between the plurality of first pads and the second pad. A structure is provided that is connected to the plurality of first pads via the same number of resistors and detects wire open based on a resistance value between the first lead and the second lead. Semiconductor device is obtained.
【００１５】また，本発明によれば，前記半導体装置に
おいて，前記各抵抗は略同一抵抗値を有することを特徴
とする半導体装置が得られる。Further, according to the present invention, in the semiconductor device, the semiconductor device is characterized in that the resistors have substantially the same resistance value.
【００１６】ここで，本発明の半導体装置において，前
記各抵抗値は，構成する材料にもよるが，１０Ω〜１０
ｋΩの範囲内であることが好ましい。Here, in the semiconductor device of the present invention, the above-mentioned respective resistance values may be in the range of 10Ω to 10Ω, depending on the constituent materials.
It is preferably within the range of kΩ.
【００１７】また，本発明によれば，前記いずれかの半
導体装置において，パワーＭＯＳＦＥＴ（酸化金属電界
効果型）を構成していることを特徴とする半導体装置が
得られる。According to the present invention, there is provided a semiconductor device characterized in that any one of the above-mentioned semiconductor devices constitutes a power MOSFET (metal oxide field effect type).
【００１８】[0018]
【発明の実施の形態】以下，本発明の実施の形態につい
て，図１を参照して説明する。Embodiments of the present invention will be described below with reference to FIG.
【００１９】図１は本発明の実施の形態によるワイヤオ
ープン検出装置のパワー半導体装置の構成を示す図であ
る図１を参照すると，パワー半導体装置は，パッケージ
１０内に設けられた第１乃至第３のデバイスセル（Ｍｆ
１〜Ｍｆ３）２ａ〜２ｃに分割され，各セルに対応する
各パッド（Ｐａｄ１〜Ｐａｄ３，以下，第１のパッドと
呼ぶ）１ａ〜１ｃを介して３本の結合ワイヤ（以下，第
１の結合ワイヤーと呼ぶ）３ａ〜３ｃにより，リード
（以下，第１のリードと呼ぶ）４に接続されている。各
第１のパッド１ａ，１ｂ，１ｃから，ワイヤオープン検
出用の第２のパッド（Ｐａｄ４）１ｄに，第１乃至第３
の抵抗（Ｒ１，Ｒ２，Ｒ３）６ａ，６ｂ，６ｃを介して
接続している。第１及び第２のリード４，５は，図示し
ないこの第１及び第２のリード４，５間の抵抗値を検出
するための抵抗検出手段に接続されている。FIG. 1 is a diagram showing the configuration of a power semiconductor device of a wire open detection device according to an embodiment of the present invention. Referring to FIG. 3 device cells (Mf
1 to Mf3) divided into 2a to 2c, and three connecting wires (hereinafter, referred to as first bonding) via respective pads (Pad1 to Pad3, hereinafter referred to as first pads) 1a to 1c corresponding to the respective cells. Leads (hereinafter, referred to as first leads) 4 are connected by wires 3a to 3c. From the first pads 1a, 1b, 1c, the first to third pads are connected to a second pad (Pad4) 1d for wire open detection.
(R1, R2, R3) 6a, 6b, 6c. The first and second leads 4 and 5 are connected to a resistance detecting means (not shown) for detecting a resistance value between the first and second leads 4 and 5.
【００２０】第２のパッド１ｄは第２のワイヤ３ｄを介
して第２のリード５に接続されている。第１及び第２の
結合ワイヤ３ａ〜３ｄ，第１及び第２のパッド１ａ〜１
ｄ，及び配線は，金やＡｌなどの金属によって形成す
る。抵抗６ａ〜６ｃは，Ｓｉ基板に不純物を導入した拡
散層や，不純物を導入したポリシリコン層，あるいはＷ
Ｓｉなど，金属に比べて十分に高い抵抗材を用いて形成
する。The second pad 1d is connected to the second lead 5 via the second wire 3d. First and second bonding wires 3a to 3d, first and second pads 1a to 1
d and the wiring are formed of a metal such as gold or Al. The resistors 6a to 6c are formed by a diffusion layer in which impurities are introduced into a Si substrate, a polysilicon layer in which impurities are introduced, or a W layer.
It is formed using a resistance material sufficiently higher than metal such as Si.
【００２１】ここで，第１乃至第３の抵抗６ａ〜６ｃの
各抵抗値をＲ１＝Ｒ２＝Ｒ３＝９０Ωに設定すると，ワ
イヤオープン不良がなく正常の場合，第１及び第２のリ
ード４，５間の抵抗値は３０Ωである。Here, when the respective resistance values of the first to third resistors 6a to 6c are set to R1 = R2 = R3 = 90Ω, the first and second leads 4 and 4 can be used when there is no wire open failure and the wiring is normal. The resistance value between 5 is 30Ω.
【００２２】しかし，第１のリード４から各第１のパッ
ド（Ｐａｄ１〜Ｐａｄ３）１ａ〜１ｃへの第１も結合ワ
イヤ３ａ〜３ｃでオープンがあった場合，１本オープン
で第１及び第２のリード４，５間の抵抗は４５Ω，２本
オープンで，第１及び第２のリード４，５間の抵抗は９
０Ω，３本全てオープンで第１及び第２のリード４，５
間の抵抗もオープン（∞）と抵抗値が変化する。However, if there is an opening from the first lead 4 to each of the first pads (Pad1 to Pad3) 1a to 1c by the coupling wires 3a to 3c, the first and second pads are opened by one. The resistance between the leads 4 and 5 is 45Ω, the two leads are open, and the resistance between the first and second leads 4 and 5 is 9
0Ω, all three open, first and second leads 4,5
The resistance between them also changes between open (∞) and the resistance value.
【００２３】従って，第１及び第２のリード４，５間の
抵抗を測定することにより，ワイヤオープンを検出する
ことができる。Therefore, by measuring the resistance between the first and second leads 4 and 5, it is possible to detect a wire open.
【００２４】なお，検出用の第２のリード５と第２のパ
ッド（Ｐａｄ４）１ｄ間の第２のワイヤ１１ｄがオープ
ンであった場合も，第１及び第２のリード間はオープン
となる。また，抵抗検出手段は，検出する抵抗値のオー
ダーに対応し（∞は除く），且つ全てオープンを検出で
きるものであるならば，どのような構成を有するもので
あっても良い。Incidentally, even if the second wire 11d between the second lead 5 for detection and the second pad (Pad4) 1d is open, the space between the first and second leads is open. The resistance detecting means may have any configuration as long as it corresponds to the order of the resistance value to be detected (except for Δ) and can detect all open states.
【００２５】次に，本発明の実施の形態の動作につい
て，図１を参照して説明する。Next, the operation of the embodiment of the present invention will be described with reference to FIG.
【００２６】第１の結合ワイヤ３ａ〜３ｃにオープンが
生じた場合，抵抗６ａ〜６ｃの内のオープンしたワイヤ
に対応した抵抗がオープンとなる。When the first connection wires 3a to 3c are opened, the resistance corresponding to the opened wire among the resistors 6a to 6c is opened.
【００２７】従って，デバイスの第１のリード４とワイ
ヤオープン検出用の第２のリード５との間の抵抗値が変
化する。従って，デバイスのリードと検出リード間の抵
抗を測定することにより，ワイヤオープンの有無を検出
することができる。Therefore, the resistance value between the first lead 4 of the device and the second lead 5 for wire open detection changes. Therefore, by measuring the resistance between the device lead and the detection lead, the presence or absence of the wire open can be detected.
【００２８】[0028]
【発明の効果】以上説明したように，本発明によれば，
第１のリードと第１のパッドに，更に，ワイヤオープン
検出用の第２のリードと第２のパッドを設け，複数の第
１のワイヤに対応する第１のパッドから同一抵抗を介し
て接続することにより，ワイヤオープンのＤＣ検出を可
能にしたので，複数のワイヤを使用するパワー半導体装
置のワイヤオープンを検出できる半導体装置と，半導体
装置のオープン検出方法及び検出装置を提供することが
できる。As described above, according to the present invention,
A second lead and a second pad for wire open detection are further provided on the first lead and the first pad, and connected from the first pads corresponding to the plurality of first wires via the same resistor. By doing so, DC detection of wire open is enabled, so that it is possible to provide a semiconductor device capable of detecting wire open of a power semiconductor device using a plurality of wires, and a method and a device for detecting open of a semiconductor device.
【図１】本発明の実施の形態によるワイヤオープン検出
装置を備えたパワー半導体装置の構成を示す図である。FIG. 1 is a diagram showing a configuration of a power semiconductor device including a wire open detection device according to an embodiment of the present invention.
【図２】従来のワイヤオープン検出装置を備えたパワー
半導体装置の一例を示す図である。FIG. 2 is a diagram illustrating an example of a power semiconductor device including a conventional wire open detection device.
１ａ，１ｂ，１ｃ， 第１のパッド（Ｐａｄ１，Ｐａ
ｄ２，Ｐａｄ３） １ｄ 第２のパッド（Ｐａｄ４） ２ａ，２ｂ，２ｃ 第１乃至第３のデバイスセル（Ｍ
ｆ１，Ｍｆ２，Ｍｆ３） ３ａ，３ｂ，３ｃ 第１の結合ワイヤ ３ｄ 第２の結合ワイヤ ４ 第１のリード ５ 第２のリード １０ パッケージ ５０ パッケージ ５１ａ，５１ｂ，５１ｃ パッド（Ｐａｄ１，Ｐａｄ
２，Ｐａｄ３） ５３ａ，５３ｂ，５３ｃ 結合ワイヤ ５４ リード ５５ａ，５５ｂ 電極間金属配線1a, 1b, 1c, first pad (Pad1, Pa
d2, Pad3) 1d Second pad (Pad4) 2a, 2b, 2c First to third device cells (M
f1, Mf2, Mf3) 3a, 3b, 3c First connection wire 3d Second connection wire 4 First lead 5 Second lead 10 Package 50 Package 51a, 51b, 51c Pad (Pad1, Pad)
2, Pad 3) 53a, 53b, 53c Bonding wire 54 Lead 55a, 55b Metal wiring between electrodes
Claims (7)
の第１のパッドとパッケージの単一の第１のリードとの
間に，前記複数の第１のパッドと同数の複数の第１の結
合ワイヤを設けたパワー半導体装置のワイヤオープンを
検出する装置において，更にワイヤオープン検出用の第
２のリードとワイヤオープン検出用の第２のパッドとを
第２の結合ワイヤを介して設け，前記複数の第１のパッ
ドと前記第２のパッドとの間を，前記複数の第１のパッ
ドと同数の抵抗を介して接続し，前記第１のリードと前
記第２のリードとの間の抵抗値を基にワイヤオープン検
出する構造を備えていることを特徴とする半導体装置の
ワイヤオープン検出装置。1. A plurality of first pads having the same number as the plurality of first pads are provided between a plurality of first pads provided corresponding to device cells and a single first lead of a package. In a device for detecting a wire open of a power semiconductor device provided with a connecting wire, a second lead for detecting a wire open and a second pad for detecting a wire open are further provided via a second connecting wire. A plurality of first pads and the second pad are connected via the same number of resistors as the plurality of first pads, and a resistance between the first lead and the second lead is provided. A wire open detection device for a semiconductor device, comprising a structure for detecting a wire open based on a value.
プン検出装置において，前記各抵抗は略同一抵抗値を有
することを特徴とする半導体装置のワイヤオープン検出
装置。2. The wire open detection device for a semiconductor device according to claim 1, wherein said resistors have substantially the same resistance value.
パッケージの単一の第１のリードとの間に，前記複数の
第１のパッドと同数の複数の第１の結合ワイヤを設けた
パワー半導体装置のワイヤオープンを検出する方法にお
いて，更にワイヤオープン検出用の第２のリードとワイ
ヤオープン検出用の第２のパッドとを設け，前記第１の
パッドと前記第２のパッドとの間を，前記第１のパッド
と同数の抵抗を介して接続し，前記第１のリードと前記
第２のリードとの間の抵抗値を基にワイヤオープン検出
することを特徴とする半導体装置のワイヤオープン検出
方法。3. A plurality of first pads of a device cell;
In the method for detecting wire open of a power semiconductor device having the same number of first bonding wires as the plurality of first pads between a single first lead of a package, the method further comprises detecting wire open. And a second pad for wire open detection are provided, and the first pad and the second pad are connected through the same number of resistors as the first pad. A wire open detection method for a semiconductor device, wherein wire open detection is performed based on a resistance value between the first lead and the second lead.
プン検出方法において，前記各抵抗に，略同一抵抗値を
有するものを使用することを特徴とする半導体装置のワ
イヤオープン検出方法。4. The method according to claim 3, wherein each of the resistors has substantially the same resistance value.
パッケージの単一の第１のリードとの間に，前記複数の
第１のパッドと同数の複数の第１の結合ワイヤを設けた
構造を備えたパワー半導体装置において，更にワイヤオ
ープン検出用の第２のリードとワイヤオープン検出用の
第２のパッドとを第２の結合ワイヤを介して設け，前記
複数の第１のパッドと前記第２のパッドとの間を，前記
複数の第１のパッドと同数の抵抗を介して接続し，前記
第１のリードと前記第２のリードとの間の抵抗値を基に
ワイヤオープン検出する構造を備えていることを特徴と
する半導体装置。5. A structure in which the same number of the first bonding wires as the plurality of first pads are provided between the plurality of first pads of the power device and the single first lead of the package. And a second lead for detecting wire open and a second pad for detecting wire open are provided via a second coupling wire, and the plurality of first pads and the second pad are provided. A structure in which two pads are connected to each other via the same number of resistors as the plurality of first pads, and wire open detection is performed based on a resistance value between the first lead and the second lead. A semiconductor device comprising:
記各抵抗は略同一抵抗値を有することを特徴とする半導
体装置。6. The semiconductor device according to claim 5, wherein said resistors have substantially the same resistance value.
て，パワーＭＯＳＦＥＴを構成していることを特徴とす
る半導体装置。7. The semiconductor device according to claim 5, wherein the semiconductor device comprises a power MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9273184A JP3011234B2 (en) | 1997-10-07 | 1997-10-07 | Method and apparatus for detecting wire open in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9273184A JP3011234B2 (en) | 1997-10-07 | 1997-10-07 | Method and apparatus for detecting wire open in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11111785A JPH11111785A (en) | 1999-04-23 |
| JP3011234B2 true JP3011234B2 (en) | 2000-02-21 |
Family
ID=17524280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9273184A Expired - Fee Related JP3011234B2 (en) | 1997-10-07 | 1997-10-07 | Method and apparatus for detecting wire open in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3011234B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3759135B2 (en) | 2003-09-12 | 2006-03-22 | ローム株式会社 | Semiconductor device and electronic device |
| DE102005004608B3 (en) * | 2005-02-01 | 2006-04-20 | Siemens Ag | Method of checking electrical contacts between output pins of power circuits of power circuit device and external node between device and load |
| JP6056299B2 (en) | 2012-09-13 | 2017-01-11 | 富士電機株式会社 | Semiconductor device and wire open defect detection method |
| JP6135690B2 (en) * | 2015-02-06 | 2017-05-31 | トヨタ自動車株式会社 | Semiconductor chip and method for detecting disconnection of wire bonded to semiconductor chip |
| CN110612600B (en) * | 2017-05-19 | 2022-12-27 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
| WO2018225188A1 (en) * | 2017-06-07 | 2018-12-13 | 新電元工業株式会社 | Disconnection determining device and power module |
-
1997
- 1997-10-07 JP JP9273184A patent/JP3011234B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11111785A (en) | 1999-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3011234B2 (en) | Method and apparatus for detecting wire open in semiconductor device | |
| US20120306528A1 (en) | Circuit device having a semiconductor component | |
| JPH098075A (en) | Semiconductor device | |
| JP3157715B2 (en) | Semiconductor integrated circuit | |
| JP4117917B2 (en) | Circuit layout for testing the operation of the power transistor current monitoring circuit | |
| EP0622733B1 (en) | Method and device for testing integrated power devices | |
| JPH0864769A (en) | Integrated circuit | |
| CN101180534B (en) | Circuit assembly for operating a gas sensor array | |
| EP1143254A1 (en) | Earth wiring diagnosis in circuit modules with multiple earth connection, particularly for electronic units on board motor vehicles | |
| US6140821A (en) | Method and system for the recognition of insulation defects | |
| JP7487859B2 (en) | Gas sensor evaluation and control unit | |
| JPH09113566A (en) | Connected state detecting device for semiconductor substrate | |
| JP2001289897A (en) | Wire harness inspecting system | |
| JP2972473B2 (en) | Semiconductor device | |
| JP2532793Y2 (en) | Bridge type sensor | |
| JPH02186661A (en) | Integrated circuit | |
| JPS62111439A (en) | Semiconductor device | |
| JPH05326850A (en) | Semiconductor device | |
| JPH04162677A (en) | Semiconductor device | |
| JPH0538887U (en) | Test pattern for reliability evaluation of semiconductor devices | |
| TWI387767B (en) | Monolithisch integrierte halbleiteranordnung mit einem leistungsbauelement und verfahren zur herstellung einer monolithisch integrierten halbeiteranordnung | |
| JPH09213760A (en) | Evaluation of semiconductor device | |
| JPH09162254A (en) | Reliability test method and device of metal wiring | |
| JPH06295948A (en) | Method and circuit for evaluating semiconductor characteristics | |
| JPS63173976A (en) | Semiconductor test head apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19991110 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |