JP3008442B2 - Receiving circuit of communication control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a communication control device, and more particularly to a reception method of a communication control device of a packet switch.

(Prior art) Conventionally, a communication control device such as a packet switch decomposes a frame and sends out a cell including information and a header to a communication line (packet switching network, ISDN network). The cell is assembled into a frame based on the received header information of the cell.

FIG. 2 is a diagram showing a configuration of a conventional communication system. In FIG. 2, 1a and 1b are communication control devices, 2a and 2b are control units, 3a and 3b are transmission circuits, 4a and 4b are reception circuits, and 5 is a communication line. The case where data is transmitted from the communication control device 1a to the communication control device 1b will be briefly described.

First, under the control of the control unit 2a, the transmission circuit 3a decomposes the frame into cells, and transmits the cells to the communication line 5.

Then, the receiving circuit 4b of the communication control device 1b on the receiving side receives the cell, performs a header check and the like, assembles the cell into a frame, and passes the frame to the control unit 2b.

FIG. 3 is a detailed configuration diagram of a receiving circuit of the communication control device of FIG.

In FIG. 3, 31 is a header latch circuit, 32 is a header check circuit, 33 is an assembly control memory, 34 is a report queue,
35 is a microprocessor and memory, 36 is a buffer, 38
Is an AND gate, 39 is a selector, and 37, 40, 41 are gates.

Hereinafter, the reception method of the conventional communication control device will be set in detail.

In the conventional communication control device, a receiving circuit 4 divides a frame including an address part A, a control part C, and an information part I shown in FIG.
Receives cells that are sent after being decomposed into cells with a PL header added. When latching the headers in the header latch circuit 31, identifying the cell of the ATML header as shown in FIG. 5 Enable (CEF = 1), and the assembly controlled by a timing T ₀₁ memory
Reads 33 and sends the information to buffer 36
Buffering at T _02. At this time, although not shown, a frame check sequence (FCS) is checked. Of the data shown in FIG. 7 read from the assembly control memory 33, the channel state is a reception waiting state (CMD = 00).
If so, the status (STS), cell number (CNO), and number of cell bytes (CBC) of the ADPL header as shown in FIG.
Performs the check and calculation, stores the timing T ₀₃ as FIG. 7 including the FCS data to assemble the control memory 33.
This assembly control memory 33 uses a general-purpose product, and uses a channel number as an address but omits it.

Next and subsequent cells are sequentially received and written to the frame assembly control memory shown in FIG. When the last cell (STS = 01) is received, processing is performed in the same manner as the above cell, and the
Data is written to 33, and data indicating a state in which the next frame (cell) can be received is written. That is, CMD = 00.

Others are not particularly related to the receiving operation, and thus the drawings and detailed description are omitted.

If the report queue (see Fig. 9) is blocked (EF
= 00, FF = 1), the cell (frame) is discarded without buffering in the assembly control memory 33 and the buffer 36. That is, the receiving method of the conventional communication control device is a method that does not perform any flow control or the like.

As an example of a related patent, there is Japanese Patent Application No. 1-215897 previously proposed by the present applicant.

(Problems to be Solved by the Invention) However, when the report queue is blocked, even if a new cell is received, all the cells are discarded. Therefore, in a communication method having an urgent frame or cell,
There is a problem that it is unavoidable to add hardware such as increasing buffers or to complicate protocols such as flow control.

An object of the present invention is to solve such a conventional problem, and to partially rescue the transmission by adopting a method existing between a complete protocol by flow control and a protocol without a protocol for discarding all. It is an object of the present invention to improve the efficiency and to provide a receiving circuit of a communication control device in which an assembly control memory is used as a report queue.

(Means for Solving the Problems) In order to achieve the above object, a receiving circuit of a communication control device of the present invention receives a cell including a header and information, checks the contents of the header, and waits for reception or reception. Header checking means for outputting a channel status indicator bit including a bit indicating a medium status, an assembly control memory for assembling a frame from the channel status indicator bit, a report queue for storing the frame, and one cell of the information of the cell In a receiving circuit of a communication control device having an information buffer capable of storing the same and a receiving circuit controlling means for controlling the information buffer,
The channel status indicator bit has an additional bit to indicate an emergency cell report wait status, and the header check means determines that the report queue is blocked and the channel status indicator bit indicates the reception wait status. In this case, when an emergency cell is received, the channel state indication bit is set to an emergency cell report wait state, and the assembly control memory stores the channel state in the emergency cell report wait state. It is characterized in that an emergency frame is constructed when an indication bit is received.

(Operation) In the present invention, the reception state is indicated by three bits in addition to the one bit added to the CMD bit on the assembly control memory,
Even if the report queue is closed when an emergency cell is received, if the CMD bit in the assembly control memory is in a waiting state, the reception of the cell is accepted, the frame is assembled, and the CMD is assembled.
Wait for bit report.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

Since the overall configuration of the present embodiment is the same as that of FIG. 2, it will be referred to below. In the present embodiment, the configuration of the receiving circuit of the communication control device is different. Are different.

FIG. 1 is a detailed configuration diagram of a receiving circuit of a communication control device showing one embodiment of the present invention.

In FIG. 1, 11 is a header latch circuit, 12 is a header check circuit including emergency cell determination, 13 is an assembling control memory for assembling a frame corresponding to an emergency cell with 3 bits of CMD bit, and 14 is a report queue. , 15 are a microprocessor and a memory, 16 is a buffer, 17, 18, and 21 are AND gates, 19 is a selector, and 20 is a gate. FIG. 11 shows a flowchart of the receiving process in FIG. Hereinafter, the operation of the present embodiment will be described according to the flow of FIG.

First, the frame composed of the address part A, the control part C, and the information part I shown in FIG. 4 is divided into cells having a fixed length and is divided into cells to which headers (ATML headers, ADPL headers) are added and sent. The cell is received (step 1101). When the latches the header by the header latch circuit 11 (step 1102), the cells of the ATML header as indicated by FIG. 5 Enable (CEF = 1) identifies, assembly control memory at a timing T ₀₁
13 reads out (step 1103), the information unit buffers at timing T ₀₂ to the buffer 16 (step 1104). At this time, although not shown, the frame check sequence (FCS) is checked. Assembly control memory 1
In the data read from FIG. 3 and shown in FIG. 8, if the channel state indicates a reception waiting state (CMD = 000) (step
1105-1108), the status (STS), cell number (CNO), and number of cell bytes (CB) in the ADPL header as shown in FIG.
Check and calculate C) (steps 1109 and 1110),
Including FCS data stored at the timing T ₀₃ as Figure 8 to assemble the control memory 13 (step 1111). The assembly control memory 13 uses a general-purpose product, and uses a channel number as an address but omits it.

Next and subsequent cells are sequentially received and assembled into a frame shown in FIG. When the last cell (STS = 01) is received, the same processing as in the above cell is performed, data is written to the assembly control memory 13, and data indicating a state in which the next frame (cell) can be received is written. That is, CMD = 000.

At the same time as writing data to the assembling control memory 13, the empty (EF = 1, FF = 0) of the report queue 14 is checked, and among the data read from the assembling control memory 13, the number of frame bytes (BC) and the block number ( the BN) to report queue 14 stores at the timing T ₀₄ (step 1112).

When the report queue 14 is blocked (EF = 0, FF = 1)
If the command bit of the assembly control memory 13 is CMD = 000, only when the cell reception header check circuit 12 determines that the cell is an emergency cell (F = 1), as shown in FIG.
The cell information CI, the AT field information ATF, and the BN valid BNB = 1 are stored in the assembly control memory 13 instead of the BC.

(Effects of the Invention) As described above, according to the present invention, one bit is added to the CMD bit of the conventional assembly control memory, and the cell can be received regardless of whether the report queue is empty or closed. By employing the hardware simple flow control, the transmission efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a reception circuit of a communication control device showing one embodiment of the present invention, FIG. 2 is a configuration diagram of a communication system, FIG. 3 is a configuration diagram of a reception circuit of a conventional communication control device, FIG. Fig. 5 is a diagram of a frame and a cell, Fig. 5 is a diagram of an ATML header, Fig. 6 is a diagram of an ADPL header, Fig. 7 is a mapping diagram of a conventional assembly control memory, and Fig. 8 is an embodiment of the present invention. FIG. 9 is a mapping diagram of a conventional report queue, FIG. 10 is a mapping diagram of a report queue in an embodiment of the present invention, and FIG. 11 is a flowchart of reception processing according to an embodiment of the present invention. It is. 11: Header latch circuit, 12: Header check circuit, 13: Assembly control memory, 14: Report queue, 15: Microprocessor and memory, 16: Buffer.

Claims (1)

(57) [Claims] 1. A header checking means for receiving a cell containing a header and information, checking the contents of the header, and outputting a channel status indication bit including a bit indicating a reception waiting state or a receiving state, A communication control device comprising: an assembling control memory for assembling a frame from display bits; a report queue for storing the frame; an information buffer capable of storing the information of the cell for one cell; and a receiving circuit control means for controlling these. In the receiving circuit, the channel status indication bit has an additional bit to indicate an emergency cell report waiting state, and the header check means, wherein the report queue is closed and the channel status indication bit is When an emergency cell is received while indicating the reception waiting state, the channel status indication bit is set to “0”. A cell report waiting state, wherein the assembly control memory is configured to assemble an emergency frame when receiving the channel state indication bit in the emergency cell report waiting state. A receiving circuit of the communication control device.