JP3008015B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3008015B2 JP3008015B2 JP8178999A JP17899996A JP3008015B2 JP 3008015 B2 JP3008015 B2 JP 3008015B2 JP 8178999 A JP8178999 A JP 8178999A JP 17899996 A JP17899996 A JP 17899996A JP 3008015 B2 JP3008015 B2 JP 3008015B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- mold
- semiconductor device
- transfer
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、トランスファモー
ルド法により製造される半導体装置およびその製造方法
に関する。The present invention relates to a semiconductor device manufactured by a transfer molding method and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】一般に、半導体装置のパッケージ技術と
してトランスファモールド成形がある。2. Description of the Related Art In general, there is transfer molding as a semiconductor device package technology.
【０００３】このトランスファモールド成形は、たとえ
ば、図６に示すように、リードフレーム１にＩＣチップ
などの半導体素子２を半田３などによってダイボンディ
ングした上で、金属細線４を用いて半導体素子２とリー
ドフレーム１の外部接続端子となるべき部分５との間を
ワイヤボンディングする。In this transfer molding, for example, as shown in FIG. 6, a semiconductor element 2 such as an IC chip is die-bonded to a lead frame 1 with solder 3 or the like, and then the semiconductor element 2 is connected to the semiconductor element 2 using a thin metal wire 4. Wire bonding is performed between the lead frame 1 and a portion 5 to be an external connection terminal.
【０００４】次に、図７に示すように、これをトランス
ファモールド金型６内に配置して、その上型６aと下型
６bとでリードフレーム１を押さえつけて密着させる。[0007] Next, as shown in FIG. 7, the lead frame 1 is placed in a transfer mold 6, and the lead frame 1 is pressed down and brought into close contact with an upper die 6 a and a lower die 6 b.
【０００５】この状態で、次に、エポキシ、シリコン等
の熱硬化性のモールド樹脂７を軟化するまで加熱して可
塑化し、これを図示しないプランジャでトランスファ金
型６の上型６aと下型６bとの間にできたキャビティ８内
に圧入して硬化させる。[0005] In this state, the thermosetting mold resin 7 such as epoxy or silicon is plasticized by heating until it is softened, and the upper mold 6a and the lower mold 6b of the transfer mold 6 are transferred by a plunger (not shown). Is press-fitted into the cavity 8 formed between them and cured.
【０００６】このとき、未充填部分の残すことなく成形
品の中心部までモールド樹脂７がよく回り込んで硬化す
るように、プランジャの押し出し圧力は、数百kg／cm3
程度の圧力で注入される。At this time, the extruding pressure of the plunger is set to several hundred kg / cm 3 so that the mold resin 7 goes around and hardens to the center of the molded product without leaving an unfilled portion.
It is injected at a moderate pressure.
【０００７】また、半導体装置の種類によっては、装置
内部の自己発熱が高くなるものがあるので、モールド樹
脂７内にシリカ等の硬度の高い高熱伝導性の物質を充填
して放熱性を高めている。[0007] Further, depending on the type of the semiconductor device, self-heating inside the device may increase. Therefore, the mold resin 7 is filled with a highly heat-conductive material having high hardness such as silica to improve heat dissipation. I have.
【０００８】[0008]
【発明が解決しようとする課題】ところで、リードフレ
ーム１をトランスファ金型６にセットする場合、リード
フレーム１とトランスファモールド金型６の接触する面
が完全に平坦でないため、図８に示すように比較的内側
に入り込んだところまで隙間９ができる場合がある。When the lead frame 1 is set on the transfer mold 6, the contact surface between the lead frame 1 and the transfer mold 6 is not completely flat, as shown in FIG. In some cases, the gap 9 may be formed as far as it relatively enters the inside.
【０００９】そして、上記のように、プランジャの押し
出し圧力を大きくすると、未充填の部分がなくなって成
形性が向上するものの、トランスファモールド時にこの
隙間９にモールド樹脂７が回り込み、これがいわゆるバ
リとなって残る。As described above, when the plunger push-out pressure is increased, the unfilled portion is eliminated and the moldability is improved. Remain.
【００１０】このようなバリがモールド金型６に付着し
ているときは、この状態で続けてトランスファモールド
を行うとモールド樹脂７内に充填されている上記のシリ
カ等の物質によりトランスファモールド金型６の内面を
摩耗させることになり、この金型６の寿命が短くなる。When such burrs are adhered to the mold 6, if transfer molding is continuously performed in this state, the transfer mold is filled with the material such as silica filled in the mold resin 7. The inner surface of the mold 6 is worn, and the life of the mold 6 is shortened.
【００１１】また、トランスファモールド成形された半
導体装置を半田等を用いて面実装するような場合に、上
記のバリが半導体装置側に付着しているときには、その
バリの部分が電気的接触が不良となるので、接触抵抗の
増大に伴う電力ロスや、素子の発生する熱を半田を介し
て十分に放熱できない等の不都合が起こる。Further, in the case where the transfer-molded semiconductor device is surface-mounted using solder or the like, when the above-mentioned burrs adhere to the semiconductor device side, the burrs have poor electrical contact. Therefore, inconveniences such as a power loss due to an increase in contact resistance and an inability to sufficiently dissipate heat generated by the element via solder occur.
【００１２】このため、従来は、モールド工程後にさら
にバリ取り工程を設けているが、このようなバリ取り工
程を設けることは、余分な手間を要するためランニング
コストの上昇を招く。For this reason, conventionally, a deburring step is conventionally provided after the molding step. However, providing such a deburring step requires extra labor and increases running costs.
【００１３】しかも、シリカ等が添加されたモールド樹
脂７は硬度が高いために、厚みが数十μmを越えるよう
なバリが発生した場合には、上記のバリ取り工程ではこ
れを十分に除去できないことがある。Moreover, since the mold resin 7 to which silica or the like is added has high hardness, when burrs having a thickness exceeding several tens of μm are generated, the burrs cannot be sufficiently removed by the above-described deburring step. Sometimes.
【００１４】本発明は、上記の問題点を解決するために
なされたもので、トランスファモールド成形時のバリ発
生を確実に防止できるようにして、トランスファモール
ド金型の寿命を延ばすとともに、バリ取り工程を省略し
てランニングコストを下げることを課題とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is possible to reliably prevent the occurrence of burrs at the time of transfer molding, thereby extending the life of the transfer mold and removing the burrs. It is an object to reduce the running cost by omitting.
【００１５】[0015]
【課題を解決するための手段】本発明は、上記の課題を
解決するため、リードフレームに半導体素子をマウント
した上でワイヤボンディングしたものをトランスファモ
ールド金型内に配置して樹脂モールドしてなる半導体装
置において、次の構成を採用している。According to the present invention, in order to solve the above-mentioned problems, a semiconductor element is mounted on a lead frame and wire-bonded, and the resultant is arranged in a transfer mold and resin-molded. The following configuration is employed in a semiconductor device.
【００１６】すなわち、請求項１記載に係る発明では、
リードフレームには、トランスファモールド金型と接触
する面でこの金型のキャビティに臨む外周部分に相当す
る箇所に隆起部が、該リードフレームの外周端から平坦
部を介して形成されており、かつ、この隆起部は、リー
ドフレームをパンチング加工する際に、パンチング金型
に設けられた突起によって溝とともに形成されたもので
ある。That is, in the invention according to claim 1,
The lead frame has a raised portion at a position corresponding to an outer peripheral portion facing the cavity of the mold on a surface in contact with the transfer mold , and is flat from the outer peripheral end of the lead frame.
The protrusion is formed together with the groove by a projection provided on a punching die when the lead frame is punched.
【００１７】請求項２記載に係る発明では、請求項１記
載の構成において、リードフレームをトランスファモー
ルド金型内に配置した場合に、上記隆起部が前記トラン
スファモールド金型に押圧されることにより変形してこ
の金型とリードフレーム間への樹脂の侵入を堰止めする
ものとして形成されている。According to the second aspect of the present invention, in the structure of the first aspect, when the lead frame is disposed in the transfer mold, the protrusion is deformed by being pressed by the transfer mold. Then, it is formed to block the intrusion of the resin between the mold and the lead frame.
【００１８】請求項３記載に係る発明では、リードフレ
ームにマウントした半導体素子をトランスファモールド
成形により樹脂モールドする半導体装置の製造方法であ
って、前記リードフレームをパンチング加工により形成
する際に、トランスファモールド金型に接触する面でこ
の金型のキャビティに臨むリードフレームの外周部分に
相当する箇所に、パンチング金型に設けられた突起によ
って溝とともに隆起部を形成する工程と、前記リードフ
レームに半導体素子をマウントした上でワイヤボンディ
ングする工程と、前記リードフレームと前記半導体素子
とをトランスファモールド金型内に配置して樹脂モール
ドする工程とを含んでいる。According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a semiconductor element mounted on a lead frame is resin-molded by transfer molding, wherein the lead frame is formed by punching. Forming a protrusion together with a groove by a projection provided on a punching die at a position corresponding to an outer peripheral portion of the lead frame facing a cavity of the die on a surface in contact with the die; and forming a semiconductor element on the lead frame. And a step of wire bonding after mounting, and a step of disposing the lead frame and the semiconductor element in a transfer mold and performing resin molding.
【００１９】この構成によれば、リードフレームをトラ
ンスファモールド金型にセットしてその上型および下型
でリードフレームを押さえるときに隆起部がつぶれる。
そして、隆起部が押し潰されたところは金型との隙間が
無くなって密着し、モールド樹脂の侵入を堰止めするた
め、それよりも内側にはバリが発生しない。さらには、
パンチング加工の工程で同時に隆起部を形成するので、
新たに工程を追加する必要がなくその分、経済的にな
る。According to this configuration, when the lead frame is set in the transfer mold and the lead frame is pressed by the upper and lower dies, the protruding portion is crushed.
Then, where the raised portion is crushed, there is no gap with the mold, and the bulge is in close contact with the mold. Moreover,
Since a ridge is formed at the same time in the punching process,
There is no need to add a new process, so that it becomes more economical.
【００２０】[0020]
【発明の実施の形態】図１は、本発明の実施形態の半導
体装置において、リードフレームに半導体素子を組み込
んだ状態を示すもので、半導体素子のマウント側と反対
の裏面側から見た平面図、図２は図１のＡ−Ａ線に沿う
断面図であり、図６ないし図８の従来例に対応する部分
には同一の符号を付す。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, showing a state where a semiconductor element is incorporated in a lead frame, as viewed from the back side opposite to the mount side of the semiconductor element. FIG. 2 is a sectional view taken along line AA of FIG. 1, and portions corresponding to those of the conventional example of FIGS. 6 to 8 are denoted by the same reference numerals.
【００２１】図１および図２において、１はリードフレ
ーム、２は半導体素子、３は半田、４は金属細線、５は
リードフレーム１の外部接続端子となるべき部分であ
り、これらの構成は、従来例の場合と同様である。In FIGS. 1 and 2, 1 is a lead frame, 2 is a semiconductor element, 3 is solder, 4 is a thin metal wire, and 5 is a portion to be an external connection terminal of the lead frame 1. This is the same as in the case of the conventional example.
【００２２】この実施形態の特徴は、リードフレーム１
の所要箇所にＶ字状の溝１１が形成されるとともに、そ
の溝１１の形成に伴ってその両側に隆起部１２が形成さ
れていることである。The feature of this embodiment is that the lead frame 1
The V-shaped groove 11 is formed at a required location, and the protrusions 12 are formed on both sides of the groove 11 along with the formation of the groove 11.
【００２３】この溝１１および隆起部１２は、図３に示
すように、リードフレーム１をトランスファモールド金
型６内に配置した場合に、その金型６(本例では下型６
a)と接触する面のキャビティ８に臨む外周部分に相当す
る箇所に、リードフレーム１の外周端から平坦部を介し
て形成される。As shown in FIG. 3, when the lead frame 1 is placed in the transfer mold 6 as shown in FIG.
a) a portion corresponding to the outer peripheral portion facing the cavity 8 on the surface in contact with the a) from the outer peripheral end of the lead frame 1 via a flat portion;
It is formed Te.
【００２４】そして、この溝１１と隆起部１２は、リー
ドフレーム１をパンチング加工する際に同時に形成され
たものである。すなわち、リードフレーム１は、通常、
図４に示すように、金属製の圧延板１４をパンチング金
型１５を用いてパンチング加工することにより成形され
るが、その場合に、パンチング金型１５の所定部分に、
図５(a)に示すように、溝１１形成用の楔形の突起１６
を設けておき、この突起１６をパンチングの際に圧延板
１４に食い込ませることで、溝１１と隆起部１２とが同
時に形成される。このように、従来からのパンチング加
工の工程で隆起部１２を形成することができるので、新
たに工程を追加する必要がなく経済的である。なお、図
５(a)では、溝１１形成用の突起１６を楔形としてＶ字
状の溝１１を形成しているが、図５(b)に示すように、
突起１７を凸状のものとすることも可能である。The grooves 11 and the raised portions 12 are formed at the same time when the lead frame 1 is punched. That is, the lead frame 1 is usually
As shown in FIG. 4, a metal rolled plate 14 is formed by punching using a punching die 15. In this case, a predetermined portion of the punching die 15 is
As shown in FIG. 5A, a wedge-shaped projection 16 for forming the groove 11 is formed.
The grooves 11 and the raised portions 12 are formed at the same time by making the projections 16 bite into the rolling plate 14 during punching. As described above, since the raised portion 12 can be formed by the conventional punching process, there is no need to add a new process, which is economical. In FIG. 5A, the V-shaped groove 11 is formed with the protrusion 16 for forming the groove 11 being wedge-shaped, but as shown in FIG.
It is also possible to make the projection 17 convex.
【００２５】この実施形態の半導体装置を製造する場合
には、上述のように、パンチング加工の際に溝１１およ
び隆起部１２が予め形成されてなるリードフレーム１を
準備し、このリードフレーム１に半導体素子２を半田３
によってダイボンディングする。In manufacturing the semiconductor device of this embodiment, as described above, a lead frame 1 in which a groove 11 and a raised portion 12 are formed in advance during punching is prepared. Solder semiconductor element 2
Die bonding.
【００２６】次に、金属細線４を用いて半導体素子２と
リードフレーム１の外部接続端子となるべき部分５との
間をワイヤボンディングする。Next, wire bonding is performed between the semiconductor element 2 and the portion 5 to be an external connection terminal of the lead frame 1 using the thin metal wire 4.
【００２７】続いて、これをトランスファモールド金型
６内に配置して、その上型６aと下型６bとでリードフレ
ーム１を押さえつけて密着させる。Subsequently, this is placed in the transfer mold 6 and the lead frame 1 is pressed down and brought into close contact with the upper mold 6a and the lower mold 6b.
【００２８】その際、リードフレーム１の隆起部１２
は、図３に示すように、トランスファモールド金型６に
押圧されることにより変形して押し潰されてトランスフ
ァモールド金型６(この例では下型６a)と完全に密着さ
れる。At this time, the raised portion 12 of the lead frame 1 is
As shown in FIG. 3, is deformed and crushed by being pressed by the transfer mold die 6, and is completely adhered to the transfer mold die 6 (the lower die 6a in this example).
【００２９】このため、次に、可塑化されたモールド樹
脂７が図示しないプランジャでトランスファ金型６の上
型６aと下型６bとの間にできたキャビティ８内に圧入さ
れた場合でも、この隆起部１２が押し潰された部分がモ
ールド樹脂の侵入を堰止めするため、それよりも内側に
はバリが発生しない。Therefore, even if the plasticized mold resin 7 is pressed into the cavity 8 formed between the upper mold 6a and the lower mold 6b of the transfer mold 6 by a plunger (not shown), Since the crushed portion of the raised portion 12 blocks the intrusion of the mold resin, no burrs are generated inside the portion.
【００３０】こうして樹脂モールドされた後は、従来の
ようなバリ取り工程を省略して、リードフレーム１の露
出部分を半田めっきし、続いて、リードフレーム１のタ
イバー部分を切断してから、モールド樹脂の部分のマー
キング処理を行って製品検査される。After resin molding, the exposed portion of the lead frame 1 is plated with solder by omitting the conventional deburring step, and then the tie bar portion of the lead frame 1 is cut. The product is inspected by marking the resin part.
【００３１】[0031]
【発明の効果】本発明によれば、リードフレームのパン
チングの際に同時に隆起部を形成することにより、トラ
ンスファモールド成形時のバリ発生を確実に防止するこ
とができる。このため、トランスファモールド金型の寿
命を延ばすとともに、従来のバリ取り工程を省略できる
ためランニングコストを下げることができる。さらに
は、パンチング加工の工程で隆起部を同時に形成するの
で、新たに工程を追加する必要がなく経済的となり、そ
の分でもコストを下げることができる。According to the present invention, burrs can be reliably prevented from being formed during transfer molding by forming a raised portion at the same time as punching a lead frame. Therefore, the life of the transfer mold can be extended, and the running cost can be reduced because the conventional deburring step can be omitted. Furthermore, since the raised portions are simultaneously formed in the punching process, there is no need to add a new process, so that it is economical, and the cost can be reduced accordingly.
【図１】本発明の実施形態の半導体装置において、リー
ドフレームに半導体素子を組み込んだ状態を示すもの
で、半導体素子のマウント側と反対の裏面側から見た平
面図である。FIG. 1 is a plan view showing a state in which a semiconductor element is incorporated in a lead frame in a semiconductor device according to an embodiment of the present invention, as viewed from a back surface side opposite to a mount side of the semiconductor element.
【図２】図１のＡ−Ａ線に沿う断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】図１のものをトランスファモールド金型にセッ
トしたときの断面図である。FIG. 3 is a cross-sectional view when FIG. 1 is set in a transfer mold.
【図４】図１の半導体装置のリードフレーム形成のため
の工程を示す説明図である。FIG. 4 is an explanatory view showing a process for forming a lead frame of the semiconductor device of FIG. 1;
【図５】図１の半導体装置のリードフレーム形成時に同
時に溝を形成する場合のパンチング金型の形状を示す断
面図である。5 is a cross-sectional view showing a shape of a punching die when a groove is formed at the same time as forming a lead frame of the semiconductor device of FIG. 1;
【図６】従来技術において、リードフレームに半導体素
子を組み込んだ状態を示す平面図である。FIG. 6 is a plan view showing a state in which a semiconductor element is incorporated in a lead frame in a conventional technique.
【図７】図６のものをトランスファモールド金型にセッ
トしたときの断面図である。FIG. 7 is a cross-sectional view when FIG. 6 is set in a transfer mold.
【図８】図７の符号Ｂで示す部分を拡大して示す断面図
である。8 is a cross-sectional view showing a portion indicated by reference numeral B in FIG. 7 in an enlarged manner.
【符号の説明】 １…リードフレーム、２…半導体素子、３…ハンダ、４
…金属細線、６…トランスファモールド金型、６a…下
型、６b…上型、７…モールド樹脂、８…キャビティ、
９…隙間、１１…溝、１２…隆起部。[Explanation of Symbols] 1 ... lead frame, 2 ... semiconductor element, 3 ... solder, 4
... Metal wire, 6 ... Transfer mold die, 6a ... Lower die, 6b ... Upper die, 7 ... Mold resin, 8 ... Cavity,
9: gap, 11: groove, 12: ridge.
Claims (3)
した上でワイヤボンディングしたものをトランスファモ
ールド金型内に配置して樹脂モールドしてなる半導体装
置において、 前記リードフレームには、トランスファモールド金型と
接触する面でこの金型のキャビティに臨む外周部分に相
当する箇所に隆起部が、該リードフレームの外周端から
平坦部を介して形成されており、かつ、この隆起部は、
リードフレームをパンチング加工する際に、パンチング
金型に設けられた突起によって溝とともに形成されたも
のであることを特徴とする半導体装置。1. A semiconductor device in which a semiconductor element is mounted on a lead frame and then wire-bonded and placed in a transfer mold and resin-molded, wherein the lead frame is in contact with the transfer mold. A raised portion is located on the surface corresponding to the outer peripheral portion facing the cavity of the mold, from the outer peripheral end of the lead frame.
It is formed via a flat part , and this raised part is
A semiconductor device characterized by being formed together with a groove by a projection provided on a punching die when punching a lead frame.
置した場合に、前記隆起部が前記トランスファモールド
金型に押圧されることにより変形してこの金型とリード
フレーム間への樹脂の侵入を堰止めするものであること
を特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein when the lead frame is disposed in a transfer mold, the protrusion is deformed by being pressed by the transfer mold. A semiconductor device for blocking intrusion of resin between a mold and a lead frame.
子をトランスファモールド成形により樹脂モールドする
半導体装置の製造方法であって、 前記リードフレームをパンチング加工により形成する際
に、トランスファモールド金型に接触する面でこの金型
のキャビティに臨むリードフレームの外周部分に相当す
る箇所に、パンチング金型に設けられた突起によって溝
とともに隆起部を形成する工程と、 前記リードフレームに半導体素子をマウントした上でワ
イヤボンディングする工程と、 前記リードフレームと前記半導体素子とをトランスファ
モールド金型内に配置して樹脂モールドする工程と、 を含むことを特徴とする半導体装置の製造方法。3. A method of manufacturing a semiconductor device in which a semiconductor element mounted on a lead frame is resin-molded by transfer molding, and wherein the lead frame is formed by punching with a surface in contact with a transfer mold. Forming a protrusion together with a groove by a projection provided on a punching mold at a position corresponding to the outer peripheral portion of the lead frame facing the cavity of the mold; and bonding a semiconductor element to the lead frame and then performing wire bonding. And a step of disposing the lead frame and the semiconductor element in a transfer mold and performing resin molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8178999A JP3008015B2 (en) | 1996-07-09 | 1996-07-09 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8178999A JP3008015B2 (en) | 1996-07-09 | 1996-07-09 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1027874A JPH1027874A (en) | 1998-01-27 |
| JP3008015B2 true JP3008015B2 (en) | 2000-02-14 |
Family
ID=16058353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8178999A Expired - Fee Related JP3008015B2 (en) | 1996-07-09 | 1996-07-09 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3008015B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5101093B2 (en) * | 2006-11-30 | 2012-12-19 | 京セラクリスタルデバイス株式会社 | Piezoelectric oscillator and manufacturing method thereof |
-
1996
- 1996-07-09 JP JP8178999A patent/JP3008015B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1027874A (en) | 1998-01-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5004601B2 (en) | Package component manufacturing method and semiconductor device manufacturing method | |
| US6319753B1 (en) | Semiconductor device having lead terminals bent in J-shape | |
| EP1315605B1 (en) | Mold and method for encapsulating an electronic device | |
| US6611047B2 (en) | Semiconductor package with singulation crease | |
| US20020037604A1 (en) | Lead frame, semiconductor package having lead frame, and method of manufacturing semiconductor package | |
| US8174096B2 (en) | Stamped leadframe and method of manufacture thereof | |
| US20080268576A1 (en) | Method of manufacturing a semiconductor device | |
| US7030505B2 (en) | Resin-sealed-type semiconductor device, and production process for producing such semiconductor device | |
| JPH0774195A (en) | Manufacture of resin-sealed semiconductor device | |
| US6893898B2 (en) | Semiconductor device and a method of manufacturing the same | |
| JP2003158234A (en) | Semiconductor device and its manufacturing method | |
| US5508232A (en) | Method of manufacturing a semiconductor device | |
| JPS6244408B2 (en) | ||
| JP3008015B2 (en) | Semiconductor device and manufacturing method thereof | |
| US4592131A (en) | Method for manufacturing resin-sealed semiconductor device | |
| JPH088375A (en) | Semiconductor device, lead frame and mold for manufacturing semiconductor device | |
| JP2580740B2 (en) | Lead frame | |
| US20200020617A1 (en) | Resin encapsulating mold and manufacturing method for semiconductor device | |
| JPH0254665B2 (en) | ||
| JPH0574999A (en) | Semiconductor device and its manufacture | |
| US20170040186A1 (en) | Semiconductor device and method of manufacturing the same | |
| JP3236691B2 (en) | Sealing method and mold for electronic parts | |
| JP2011238963A (en) | Method of manufacturing package component | |
| JP2535358B2 (en) | Manufacturing method of mold part in electronic parts | |
| KR19980073905A (en) | Lead Frame with Synthetic Resin Dam Bar and Manufacturing Method Thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071203 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081203 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091203 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |