JP3002550B2 - Automatic synchronization signal polarity conversion circuit for monitor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor device which receives an image signal and horizontal and vertical synchronization signals from an external device such as a computer and displays an image on a display screen.
In particular, the present invention relates to an automatic synchronization signal polarity conversion circuit of a monitor device that automatically matches the polarity of each synchronization signal input from an external device with the polarity of a synchronization signal used in its own device.

[0002]

2. Description of the Related Art In general, as shown in FIG. 6, a monitor device 1 incorporated in an information processing system has connection terminals 3 to a main unit 2 such as a host computer or an engineering workstation (EWS). They are connected via a connection socket 4 and a signal cable 5. In the monitor device 1, for example, a CRT display tube 6,
A horizontal deflection circuit, a vertical deflection circuit, an image output circuit and the like are housed. Then, an image signal, a horizontal synchronizing signal, and a vertical synchronizing signal are transmitted from the main unit 2 to the monitor device 1. The monitor device 1 drives the horizontal deflection circuit and the vertical deflection circuit with the input horizontal synchronization signal and vertical synchronization signal, and displays an image corresponding to the input image signal on the CRT display tube 6.

By the way, horizontal and vertical synchronizing signals transmitted from the main unit 2 are transmitted by the main unit 2 as shown in FIG.
As shown in (b), there are two types, and there are four types in combination. FIG. 7A shows a negative synchronization signal in which the pulse indicating the synchronization timing has a lower signal level than the other positions, and FIG. 7B shows the signal level in which the pulse indicating the synchronization timing has the signal level lower than the other positions. Is a high positive polarity synchronization signal. Therefore, the horizontal deflection circuit and the vertical deflection circuit incorporated in the monitor device 1 should be configured to operate normally with the synchronization signals of the polarities output from the main device 2.

However, when the manufacturer of the main unit 2 and the manufacturer of the monitor device 1 are different from each other, the polarity of each synchronization signal output from the main unit 2 and the polarization circuit used in each deflection circuit incorporated in the monitor device 1 are used. The polarity of the synchronizing signal may not match.

Conventionally, in order to solve such inconvenience, an inverting circuit for inverting the polarity of a synchronizing signal outputted before the connection terminal 3 of the main unit 2 is incorporated, and the signal is outputted, for example, by operating a dip switch. The polarity of the synchronization signal can be selected, or inside the monitor device 1,
Incorporates an inversion circuit that inverts the polarity of the input synchronization signal,
For example, a method has been put to practical use in which each synchronization signal input by the operation of a changeover switch is made to match the polarity used in each internal deflection circuit.

[0006]

However, as described above, it is quite complicated for the operator to switch the polarity on the main unit 2 and the monitor 1 side. In particular, when it becomes necessary to change the state of a plurality of main units 2 by one monitor unit 1 as necessary and monitor the state,
A polarity switching operation must be performed each time. In particular, when the switching operation is performed on the main unit 2, the dip switch is generally disposed inside the device, and it is difficult to easily perform the switching setting from the outside.

If only one of the main unit 2 and the monitor device 1 has a polarity switching function and the fixed polarity of the other is unknown, the polarity of the other party is checked before the correct polarity is set. Must be set. Therefore, the burden on the operator increases.

The present invention has been made in view of such circumstances, and by providing a circuit for automatically determining the polarity of a synchronization signal input from an external device, the synchronization signal output from the external device is provided. Regardless of the polarity, the synchronization of the monitor device can automatically match the polarity of the synchronization signal used in its own device, eliminating the conventional switching operation and greatly reducing the burden on the operator. An object of the present invention is to provide an automatic signal polarity conversion circuit.

[0009]

In order to solve the above-mentioned problems, an automatic synchronization signal polarity conversion circuit of a monitor device according to the present invention uses an average current value of signal levels of respective synchronization signals inputted from an external device as a reference. An input buffer circuit to be set to a level and a synchronization signal output from the input buffer circuit, a signal level higher than a reference level is set to a high level,
A first binarizing circuit for binarizing a signal level lower than the reference level as a low level and a synchronizing signal output from the input buffer circuit, wherein a signal level lower than the reference level is set to a high level and a signal higher than the reference level is set to a higher level A second binarizing circuit for binarizing the level to a low level, a first averaging circuit for obtaining a signal level proportional to an average signal level of an output signal of the first binarizing circuit, and a second A second averaging circuit for obtaining a signal level proportional to the average signal level of the output signal of the binarization circuit, and a comparison for comparing the magnitude of each signal level obtained by the first and second averaging circuits. Circuit and
A polarity conversion circuit for converting the polarity of each input synchronization signal into the polarity of a synchronization signal used in the monitor device according to the output signal of the comparison circuit.

[0010]

With the automatic synchronizing signal polarity conversion circuit of the monitor device configured as described above, the average current value of each input synchronizing signal is set as the reference level by the input buffer circuit. That is, in each of the horizontal and vertical synchronization signals, the pulse width of the pulse indicating the synchronization timing is much smaller than the time width of the other positions. Therefore, the duty ratio indicated by the ratio of one period to the high level period in the negative polarity synchronization signal shown in FIG. 7A is a very high value exceeding 0.9. On the other hand, the duty ratio of the positive synchronization signal shown in FIG. 7B is a very small value of less than 0.1. Therefore, the reference level of the synchronization signal of the negative polarity is near the upper end of the signal waveform,
The reference level of the synchronization signal of the positive polarity is near the lower end of the signal waveform.

Therefore, if the input synchronization signal has a positive polarity, the first and second binarization circuits output binarized signals having different signal levels. Therefore, when the signal levels of the respective binary signals are averaged, the average level is significantly different between the positive polarity and the negative polarity. Then, by comparing these signal levels, the polarity of the input synchronization signal can be reliably determined. Based on this determination result, the input synchronization signal can be automatically matched with the polarity of the synchronization signal used internally.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an automatic synchronizing signal polarity conversion circuit incorporated in a monitor device. It should be noted that two circuits shown in FIG. 1 are incorporated in an actual monitor, and the polarities of the horizontal synchronization signal and the vertical synchronization signal are automatically converted respectively. It is assumed that each deflection circuit of this monitor device operates with a negative synchronization signal.

The horizontal and vertical synchronizing signals a output from the host computer as an external device are input to the (+) side input terminal of the first buffer amplifier 12 via the input terminal 11. The (−) side input terminal of the first buffer amplifier 12 is grounded. This first buffer amplifier 1
Reference numeral 2 denotes an amplifier having a voltage gain of 1 for converting input impedance to low impedance. The synchronization signal a output from the first buffer amplifier 12 is input to the (+) side input terminal of the second buffer amplifier 14 via a filter 13 including a capacitor 13a and a resistor 13b having one end grounded. The second buffer amplifier 14 is an amplifier with a voltage gain of 1 and a (−) input terminal grounded. The filter 13 and the second buffer amplifier 14 constitute an input buffer circuit.

The synchronizing signal b output from the input buffer circuit is input to the (+) input terminal of the first binarization circuit 15a and the (-) input of the second binarization circuit 15b. Input to terminal. The (−) input terminal of the first binarization circuit 15a and the (+) input terminal of the second binarization circuit 15b are commonly grounded. The first and second binarization circuits 15a. 15b has the same configuration, and outputs a high-level signal such as 5 V from the output terminal when the input signal level of the (+) input terminal is higher than the signal level of the (-) input terminal. Conversely, when the input signal level of the (+) side input terminal is lower than the signal level of the (−) side input terminal, a low level signal such as 0 V is output from the output terminal.

The output signal c of the first binarizing circuit 15a is input to a first averaging circuit 16a. The first averaging circuit 16a includes two resistors 17a, 1
8a, a diode 19a for preventing backflow inserted between the resistors 17a and 18a, and a capacitor 20a connected in parallel with the resistor 18a. A resistor 18a and a capacitor 2 each having one side grounded
The terminal voltage of 0a is input to the (+) side input terminal of the comparison circuit 21 as the output signal e. Also, the resistance 1 on the ground side
The resistance value of 8a is set to a value that is considerably larger than the resistance value of the input-side resistor 17a.

The first averaging circuit 16a having such a configuration is used.
, A charging circuit is constituted by the resistor 17a and the capacitor 29a, and thus functions as a kind of low-pass filter. Therefore, a signal e having a signal level corresponding to the average signal level of the input signal c whose signal level changes periodically is output.

The output signal d of the second binarizing circuit 15b is input to a second averaging circuit 16b. The second averaging circuit 16b has the same configuration as the first averaging circuit 16a, and includes two resistors 17b and 18b, a diode 19b, and a capacitor 20b. Then, a signal f having a signal level corresponding to the average signal level of the output signal d of the second binarization circuit 15b is sent to the (−) side input terminal of the comparison circuit 21.

The comparison circuit 21 compares the magnitudes of the output signals e and f and outputs a polarity determination signal g. That is, when the signal level of the output signal e is higher than the signal level of the output signal f, the polarity determination signal g becomes a high level, indicating that the input synchronization signal a has a negative polarity. Conversely, the output signal e
Is lower than the signal level of the output signal f, the polarity determination signal g becomes low level, indicating that the input synchronization signal a has a positive polarity.

The polarity determination signal g output from the comparison circuit 21 is input to the polarity conversion circuit 22 as a switching control signal for the changeover switch 22a of the polarity conversion circuit 22.
That is, when the polarity determination signal g is at the high level, the changeover switch 22a is switched and connected to the terminal b, and when the polarity determination signal g is at the low level, the changeover switch 22a is switched and connected to the terminal a. The synchronization signal a output from the first buffer amplifier 12 is input to the filter 13 and also input to the polarity conversion circuit 22,
The signal is input to one terminal a of the changeover switch 22a via the terminal b. Further, the synchronization signal a is used as it is in the changeover switch 22a.
Is input to the other terminal b. And a changeover switch 2
2a from the common terminal c via the output terminal 23
Is output.

The operation of the thus-configured automatic synchronization signal polarity conversion circuit will be described with reference to FIGS.

FIG. 2 shows a case where a synchronization signal a of negative polarity is input. The average signal level of the negative synchronizing signal a is located near the upper end of the waveform as shown. Therefore, the reference level indicated by 0 V of the output signal b of the input buffer circuit composed of the filter 13 and the second buffer amplifier is located near the upper end of the waveform. as a result,
The output signal c of the first binarization circuit 15a has a signal level of 5V except for the pulse position indicating the synchronization timing, and the output signal d of the second binarization circuit 15b has a signal level other than the pulse position indicating the synchronization timing. The signal level becomes 0V.

The output signal e of the first averaging circuit 16a is 1
There is a continuous signal level close to 5V over the entire period of the cycle. Conversely, the output signal f of the second averaging circuit 16b is 1
The signal level becomes a continuous signal level close to 0 V over the entire period of the cycle. Therefore, the output signal e of the first averaging circuit 16a is always changed to the second averaging circuit 16 over the entire period of one cycle.
b becomes larger than the output signal f. As a result, the comparison circuit 2
1 continuously sends a high-level polarity determination signal g to the polarity conversion circuit 22. Thus, the changeover switch 22a is connected to the terminal b. Therefore, the negative synchronization signal a input from the external device is output via the output terminal 23 as it is.

Conversely, the operation of each unit when the positive synchronization signal a is input will be described with reference to the time chart of FIG. The average signal level of the signal level of the synchronization signal a of the positive polarity is located near the lower end of the waveform as shown in the figure. Therefore, the reference level indicated by 0 V of the output signal b of the input buffer circuit is located near the lower end of the waveform. As a result, the output signal c of the first binarization circuit 15a has a signal level of 0V except for the pulse position indicating the synchronization timing, and
The output signal d of the binarization circuit 15b has a signal level of 5V except for the pulse position indicating the synchronization timing. Therefore, the output signal e of the first averaging circuit 16a is always smaller than the output signal f of the second averaging circuit 16b over the entire period of one cycle.

As a result, the comparison circuit 21 continuously sends the low-level polarity determination signal g to the polarity conversion circuit 22.
Thus, the changeover switch 22a is connected to the terminal a. Therefore, the signal level of the negative polarity synchronization signal a input from the external device is inverted by the inverter 22 b, converted into a negative polarity synchronization signal h, and output from the output terminal 23.

As described above, even if the synchronization signal a input to the monitor device has either the positive polarity or the negative polarity, the polarity of the synchronization signal used inside the monitor device is automatically adjusted. Is matched to Therefore, the operator does not need to check the polarities of the synchronization signals of the main unit and the monitor device and perform a switching operation for matching the polarities of both the synchronization signals. As a result, the work efficiency of the connection work of the monitor device to the main unit can be greatly improved. In addition, there is no possibility that synchronization signals having different polarities are erroneously connected to each other.

Further, by providing an input buffer circuit including the filter 13 and the second buffer amplifier 14, the entire signal level (amplitude) including the pulse height indicating the synchronization timing in the input synchronization signal a can be reduced. Even if the value is small, the average level of the synchronization signal a can be reliably set to a reference level such as 0V.

If the synchronizing signal used inside the monitor device has a positive polarity, the changeover switch 22a may be set to the terminal a by the high-level polarity determination signal g.

FIG. 4 is a block diagram showing a schematic configuration of an automatic synchronization signal polarity conversion circuit of a monitor device according to another embodiment of the present invention. 1 are given the same reference numerals. Therefore, the detailed description of the overlapping part will be omitted.

In the circuit of this embodiment, the first averaging circuit 25a for obtaining a signal level proportional to the average signal level of the output signal c of the first binarizing circuit 15a includes a sawtooth wave generating circuit 26a and a sample signal. Hold (S / H) circuit 27
a. Note that the second averaging circuit 25b for obtaining a signal level proportional to the average signal level of the output signal d of the second binarizing circuit 15b is also the first averaging circuit 25
It comprises a sawtooth wave generating circuit 26b and a sample and hold (S / H) circuit 27b having the same configuration as that of FIG.

The sawtooth wave generating circuit 26a outputs a signal whose signal level continuously increases with time as long as a high level signal is applied to the reset terminal R.
Output from When the signal level of the reset terminal R changes to a low level, the signal level of the output signal is changed to 0V.
To control. Therefore, the sawtooth wave generating circuit 26a
As shown in FIG. 5, a sawtooth waveform that continuously increases to about 5 V from the falling time of the pulse indicating the synchronization timing in one cycle of the output signal c to the falling time of the pulse of the next synchronization timing as shown in FIG. And outputs the signal i.

The sample and hold circuit 27a has a first
The signal level of the output signal i of the sawtooth wave generation circuit 26a is held in response to the fall timing of the output signal c of the binarization circuit 15a from the high level to the low level, and held until the next fall timing I do. Therefore, an output signal k having a constant signal level of about 5 V is sent from the sample and hold circuit 27a to the next comparison circuit 21.

The second binarizing circuit 15b inputted to the sawtooth wave generating circuit 26b constituting the second averaging circuit 25b
As shown in FIG. 5, only the duration of the pulse indicating the synchronization timing is the high-level period. Therefore, an output signal j having a sawtooth waveform is obtained only during this short high-level period. Therefore, the maximum signal level of the output signal j depends on the duty ratio of the input synchronizing signal, but it is usually about 10 V or less, so that it is about 0.5V. The sample-and-hold circuit 27b is connected to the second binarization circuit 1
In response to the falling timing of the output signal c of 5b from the high level to the low level, the signal level of the output signal j of the sawtooth wave generation circuit 26b is held and held until the next falling timing. Therefore, an output signal m having a constant signal level of about 0.5 V is sent from the sample and hold circuit 27b to the next comparison circuit 21.

The output signal k from the first averaging circuit 25a
Is not lower than the signal level of the output signal m from the second averaging circuit 25b.
The polarity determination signal g from 1 to a high level
Sent to

Therefore, the negative synchronizing signal a input from the external device is output through the output terminal 23 as it is.

When a positive synchronizing signal a is input from an external device, a low-level polarity determination signal g is sent from the comparison circuit 21 to the polarity conversion circuit 22. As a result, the polarity of the negative polarity synchronizing signal a input from the external device is converted and output from the output terminal as the negative polarity synchronizing signal h. Therefore, it is possible to obtain substantially the same effect as the embodiment of FIG.

The present invention is not limited to the embodiment described above. In the embodiment, the case where the present invention is applied to a monitor device incorporating a CRT display tube has been described. However, for example, a monitor device that displays an image on a liquid crystal display as in the case of displaying on a CRT display tube. A monitor device using a liquid crystal display in which an interface circuit for converting each synchronization signal into a control signal indicating a display position of data to be displayed on the liquid crystal display may be incorporated.

[0038]

As described above, according to the automatic synchronization signal polarity conversion circuit of the present invention, the determination circuit for automatically determining the polarity of the synchronization signal input from the external device is provided.
Therefore, regardless of the polarity of the synchronization signal output from the external device, the polarity can be automatically matched to the polarity of the synchronization signal used in the own device, and the conventional switching operation can be eliminated, and the operator Can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a synchronization signal polarity automatic conversion circuit of a monitor device according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the circuit of the embodiment.

FIG. 3 is a time chart showing the operation of the circuit of the embodiment.

FIG. 4 is a circuit diagram showing a schematic configuration of a synchronization signal polarity automatic conversion circuit of a monitor device according to another embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the circuit of the embodiment.

FIG. 6 is a diagram showing a connection relationship between a general main body device and a monitor device.

FIG. 7 is a signal waveform diagram showing types of general synchronization signals.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Monitoring device, 12 ... 1st buffer amplifier, 13 ...
Filter, 14 ... second buffer amplifier, 15a ... first
15b... Second binarization circuit, 16a, 2
5a: first averaging circuit, 16b, 25b: second averaging circuit, 21: comparison circuit, 22: polarity conversion circuit.

Claims (1)

(57) [Claims] 1. A synchronization signal polarity automatic conversion circuit of a monitor device for displaying an image by receiving an image signal and vertical and horizontal synchronization signals from an external device, the signal level of the synchronization signal input from the external device. An input buffer circuit (13, 14) for setting the average current value of the reference buffer to a reference level; and a synchronizing signal output from the input buffer circuit, wherein a signal level higher than the reference level is set to a high level, and a signal lower than the reference level A first binarizing circuit (15a) for binarizing a level to a low level; and a synchronizing signal output from the input buffer circuit, wherein a signal level lower than the reference level is set to a high level and a higher level is set to a higher level than the reference level. A second binarizing circuit (15b) for binarizing the signal level to a low level
And a first averaging circuit (16a, 2a) for obtaining a signal level proportional to the average signal level of the output signal of the first binarizing circuit.
5a) and a second averaging circuit (1) for obtaining a signal level proportional to the average signal level of the output signal of the second binarizing circuit.
6b, 25b), a comparison circuit (21) for comparing the magnitude of each signal level obtained by the first and second averaging circuits, and each of the input signals according to an output signal of the comparison circuit. A polarity conversion circuit (22) for converting the polarity of the synchronization signal into the polarity of the synchronization signal used in the monitoring device.