JP2998837B2 - Microwave frequency doubler - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave band (including a millimeter wave band) amplifier using a field effect transistor (hereinafter, referred to as an FET) such as a MES type or HEMT as an amplifier. Things.

[0002]

2. Description of the Related Art A frequency multiplier using an FET generally employs a configuration in which an FET whose source is grounded is operated near pinch-off, and a harmonic component contained in a drain current is picked up. Set the FET to R near pinch-off.
When the F operation is performed, the drain current waveform of the FET is close to a half-wave rectified waveform, and contains many integer multiples of the input frequency, particularly, even-order harmonic components. If the second harmonic is taken out of this and unnecessary unnecessary harmonics and other harmonics are suppressed, it is possible to function as a doubler amplifier. When frequency multiplication in the microwave band is required, a GaAs compound device operable at several tens of GHz is used for the FET. In such a multiplier used in the microwave band, there is a strong demand for improvement of the multiplication gain and reduction in size and weight of the device.

Hereinafter, a conventional microwave frequency doubler amplifier will be described with reference to the drawings. FIG. 14 is a circuit diagram showing a configuration of a microwave multiplier (hereinafter, referred to as a first conventional example) proposed in Japanese Patent Application Laid-Open No. 62-179205. As shown in FIG. 14, the source 7 of the FET 30 is grounded, the input impedance matching circuit 35 is connected between the gate terminal 8 and the input terminal 1, and the fundamental wave is connected between the drain terminal 9 and the output terminal 2. A blocking circuit 41 is connected. The input impedance matching circuit 35 is a stub t
1 and t2 and the length and width of the matching lines L1 and L2 are selected so that matching can be achieved with respect to the input frequency. The output-side fundamental wave blocking circuit 41 includes a matching line L
4 and L5 and a fundamental wave reflection line 13, and at an a point separated by a length of the matching line L4 from the drain end, an open end selected so as to have a quarter wavelength with respect to the fundamental wave. The stub and the fundamental wave reflection line 13 are connected. The fundamental wave reflecting line 13 appears to be short-circuited to the fundamental wave and open to the second harmonic at the connection point a, so that the fundamental wave is suppressed and a desired second harmonic is output. . At this time, the input impedance of the FET as seen from the fundamental wave largely depends on the position of the short-circuit point a on the drain side. Therefore, it is necessary to appropriately select the length of the transmission line up to the stub connection so as to obtain a good multiplication gain.

[0004] In connection with the first conventional example described above, Don
ald G. Thomas et al. , IEEE T
rans. On Microwave Theory
and Technologies, Vol. 44, no.
12, Dec. 1996, "Optimization.
of Active Microwave Freq
uency Multiplier Performa
nce Utilizing Harmonic Te
In "rminating Impedanes", in addition to terminating the fundamental wave with the short circuit while matching the second harmonic in the output circuit, terminating the second harmonic with the short circuit while matching the fundamental wave in the input circuit. It is reported that this improves the multiplication gain.

FIG. 15 is a circuit diagram showing a configuration of a microwave doubler (hereinafter, referred to as a second conventional example) disclosed in Japanese Utility Model Laid-Open No. 2-126414. As shown in FIG. , FET source 7 is grounded and input terminal 1
The input impedance control circuit 36 composed of the matching lines L1, L2, L3, the second harmonic reflection line 12, and the stub t1 is connected between the drain terminal 9 and the output terminal 2. The output impedance matching circuit 42 including the wave reflection line 13, the stub t3, and the matching lines L4 and L5 is connected. The fundamental wave reflecting line 13 connected immediately after the drain end 9 is a stub having an open end having a length of 1/4 wavelength of the fundamental wave. On the input side, a matching line L1 of approximately 0.1 to 0.27 wavelength or approximately 0.6 to 0.77 wavelength of the fundamental wave is provided at the gate end 8, and then 1 / A double-wave reflection line 12 having an open end and having a length of four wavelengths is connected. In this second conventional example, the processing of the fundamental wave in the output circuit is short-circuited at the drain end, and furthermore, the input circuit is reduced to 1/4 at the second harmonic.
An open-end stub with a wavelength is provided as a second-harmonic reflection line,
The distance between the second harmonic short-circuit point b to which the stub is connected and the gate end is properly selected to improve the second harmonic output.

[0006]

In the above-mentioned first conventional example, a stub having a 1/4 wavelength end of the fundamental wave is provided as a fundamental wave blocking circuit of the output circuit at a position separated by a certain length from the drain end. Also, in the second conventional example, as the second harmonic reflection line of the input circuit, the wavelength of the fundamental wave is approximately 0.1 to 0.27 wavelength or approximately 0.6 to 0.6 wavelength from the gate end. Since the open stub of the 1/4 wavelength of the second harmonic is connected to the place separated by the 0.77 wavelength line, the matching line is inserted between the stub and the drain or gate end. The whole area becomes large.

Further, in recent FETs, the elements are multi-finger for high output, so that the capacitance between the gate and the source is increased and the input impedance of the transistor is reduced. Therefore, if a second-harmonic reflection line is provided from the gate end via a transmission line, the reflection coefficient seen by the second-harmonic at the gate end is deteriorated due to the loss of the transmission line, and the input impedance of the second harmonic is reduced. As a result, it was difficult to set the optimum value, and it was difficult to obtain a large reflection coefficient near the short circuit for the impedance of the second harmonic at the gate end, and it was not possible to improve the multiplication gain. Therefore, the problem to be solved by the present invention is to firstly make it possible to reduce the size of the multiplier amplifier, and secondly to make it possible to further improve the multiplication gain of the multiplier amplifier. It is in.

[0008]

According to the present invention, there is provided a field effect transistor having a source grounded and performing a non-linear operation in a microwave band, and a gate connected to the field effect transistor. Connected to the gate terminal of the field-effect transistor, and the input impedance of the field-effect transistor and the fundamental frequency of 2
An input impedance matching circuit including a double-wave impedance control circuit capable of forming a resonance circuit for a double frequency or a frequency in the vicinity thereof, a fundamental wave input impedance matching circuit for performing impedance matching on a fundamental wave, and the electric field effect A short-circuit means connected to the drain side of the transistor and connected to the drain end of the field-effect transistor for the fundamental frequency;
And an output impedance matching circuit including a second harmonic output impedance matching circuit with respect to the second harmonic.

According to another aspect of the present invention, there is provided a field effect transistor having a grounded source and performing a non-linear operation in a microwave band, and a gate connected to the field effect transistor. And an input capable of forming a resonance circuit for a frequency at or near twice the fundamental frequency together with the input impedance of the field-effect transistor, and matching the input impedance of the fundamental wave. An impedance matching circuit, a short-circuit means connected to the drain side of the field-effect transistor, connected to a drain end of the field-effect transistor, for a fundamental frequency, and a double-wave output impedance matching circuit for a second harmonic of the fundamental wave And an output impedance matching circuit including Microwave frequency multiplication amplifier, is provided.

[0010]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention. Connected between the input terminal In and the FET 300 is an input impedance matching circuit 100 composed of a fundamental wave input impedance matching circuit 400 and a second harmonic impedance control circuit 500 having one end connected to the gate terminal A of the FET 300. One end is connected between the FET 300 and the output terminal Out.
Fundamental wave short-circuit means 6 connected to the drain end of ET300
00 and an output impedance matching circuit 200 composed of a second harmonic output impedance matching circuit 700. FIG. 2 is a block diagram for explaining a second embodiment of the present invention. The difference from the first embodiment shown in FIG.
Input impedance matching circuit 100 connected between
Is that the fundamental wave input impedance matching circuit 800 with the second harmonic impedance control means is provided.

A fundamental wave input impedance matching circuit 400
Is composed of a transmission line and a line (stub) whose one end is open.
Or composed of inductor and capacitor
can do. Second harmonic impedance control circuit 50
An impedance of zero is twice the frequency of the fundamental wave or its frequency.
Near the input of the FET 300 at the setting bias.
It is controlled to cause resonance with impedance. Concrete
Specifically, the impedance of the second harmonic impedance control circuit 500 is
-Dance ZS (2f₀ ) Is for forward gate bias
Letting the gate-source capacitance of the FET be Cgsf, ZS
(2f₀ ) = J / (2π × 2f)₀ × Cgsf)
It is. Alternatively, the second harmonic input of the FET at the setting bias
Impedance Zin (2f ₀ ) Complex conjugate impedance
Zin * (2f₀ 0 + j × 0 →
Re @ Zin * (2f₀ )｝ + J × 0 → Zin * (2f
₀ ) → 0 + j × Im ｛Zin * (2f₀ )｝ → 0 + j ×
It is set within the range surrounded by 0. In addition, the second wave imp
The dance control circuit 500 is a wave having a frequency twice the fundamental wave.
It has an electrical length longer than 1/4 wavelength
By open tracks (stubs) or twice
Has an electrical length longer than half the wavelength of the wave frequency
One end of the line or inductor element is connected to the line or inductor element.
Capacitor connected to the ductor element and the other end is grounded
It is composed of 2nd harmonic impedance in Fig. 2
Input impedance matching circuit 80
0 is the function of the fundamental wave input impedance matching circuit 400
And the function of the second harmonic impedance control circuit 500.
Circuit, for example, input terminal In and FET
Transmission line connected in series with the gate end A of the
Is the inductor element and the transmission line or inductor element.
Capacitor connected between the connection point of the terminals and the ground point
And can be configured by:

The FET 300 is an ME using a GaAs substrate.
Although an SFET is used, a HEMT using a GaAs substrate or another compound semiconductor substrate may be used. Also,
The multiplier according to the present invention forms input and output impedance matching circuits 100 and 200 on an insulating substrate,
Although it can be advantageously configured by mounting the FET pellet, the input and output impedance matching circuits 100 and 200 can be formed on the compound semiconductor substrate on which the FET 300 is formed, and the multiplier can be monolithically configured.

The fundamental wave frequency short-circuit means 600 is a line having one quarter wavelength of the wavelength corresponding to the fundamental wave frequency and having the other end open, or an inductor element (or line).
And a capacitor having one end connected to the inductor element (or line) and the other end grounded. The second harmonic output impedance matching circuit 700 is connected to the drain terminal B of the FET 300.
A transmission line connected in series between the transmission line and the output terminal Out, and a line (stub) having one end connected to the connection point between the transmission lines and the other end opened, or an inductor element and a capacitor. Can be.

[Operation] In the microwave multiplier amplifier of the present invention shown in FIG.
, The second harmonic impedance control circuit 500
The output impedance matching circuit 200 is provided in the vicinity of the gate end of the T.
Is provided immediately after the drain end of the FET. As a result, the matching line between the conventional gate end and the second harmonic reflection circuit is omitted, and the matching line between the drain end and the fundamental wave reflection circuit is omitted, and the circuit can be downsized. Becomes

In the microwave multiplying amplifier according to the present invention,
The input impedance matching circuit 100 is controlled by a second harmonic impedance control circuit 500 provided at the gate end.
The input side impedance at the gate end of the ET with respect to the second harmonic of the fundamental frequency is controlled so as to form a resonance circuit at the second harmonic with the input impedance of the FET. By this control, the second of the gate voltage waveform caused by the non-linearity of the gate capacitance of the FET included in the multiplier amplifier.
This modulation increases the second harmonic component, and this modulation further increases the second harmonic component contained in the drain current. As a result, the second harmonic output to the drain terminal increases, and the multiplication gain to the second harmonic with respect to the input of the fundamental frequency is dramatically improved. Further, the fundamental wave is short-circuited at the drain end by the fundamental wave short-circuit means connected immediately after the drain end, and the output of the fundamental wave is suppressed.

Further, in the frequency multiplier of another embodiment of the present invention shown in FIG. 2, the input impedance matching circuit 100 is provided with the double wave impedance control means without using the double wave input impedance control circuit as described above. By appropriately configuring the fundamental wave input impedance matching circuit 800, an operation similar to that of the frequency multiplier shown in FIG. 1 can be obtained.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 3 is a circuit diagram of a first embodiment of the present invention. In FIG. 3, the second prior art example (FIG. 15)
Is different from the input impedance matching circuit 2
A second harmonic impedance control circuit is connected near the gate end of the FET, and the input side second harmonic impedance at the gate end is set within a predetermined range. The point is that it is constituted by an open-end stub having a longer electrical length.

In summary, the microwave frequency doubler according to the first embodiment of the present invention is an FET with the source 7 grounded.
30; an input impedance matching circuit 37 connected to the gate side of the FET; and an output impedance matching circuit 43 connected to the drain side of the FET. The input signal is doubled and output. The input terminal 1
DC cut capacitors 10 and 11 are connected between the input impedance matching circuit 37 and the output impedance matching circuit 43 and the output terminal 2. The gate bias voltage is applied to the FET 30 from the gate bias voltage supply terminal 3 via the choke coil 4, and the drain bias voltage is applied to the FET 30 from the gate bias voltage supply terminal 5 via the choke coil 6 (DC cut). The capacitors 10 and 11, the bias voltage supply terminals 3 and 5, and the choke coils 4 and 6 are common to all the embodiments, and the description thereof is omitted in other embodiments.

The input impedance matching circuit 37 includes a second harmonic impedance control circuit 31 for setting the input impedance for the second harmonic of the fundamental wave within a predetermined range.
Further, impedance matching of the fundamental wave is performed by the stub t1 and the matching lines L1 and L2. The second harmonic impedance control circuit 31 is connected to the gate terminal 8 of the FET. The output impedance matching circuit 43 includes the output fundamental wave short-circuiting means 32 for short-circuiting the fundamental wave to the ground point. Further, the stub t3 and the matching lines L4 and L5 perform impedance matching of the second harmonic. The output fundamental wave short circuit 32 is connected to the FET 30
Is connected to the drain end 9.

The second harmonic impedance control circuit 31
The stub 14 has an electrical length longer than １ ／ wavelength of the wavelength corresponding to the harmonic frequency and has the other end open. Thereby, the second harmonic component at the gate end can be increased, and the multiplication gain can be improved. The stub 15 constituting the output fundamental wave short-circuit means 32 has a length of 1/4 of the wavelength of the fundamental wave frequency and the other end is open. Since the stub 15 appears short-circuited to the fundamental wave at the drain end and open to the second harmonic, the fundamental wave is suppressed and the second harmonic is output.

The FET 30 is, for example, a GaAs MESFET.
Is used to set the bias to 1/15 or less of the saturation current, and perform class AB or class B operation. The input impedance matching circuit 37 and the output impedance matching circuit 43 are formed on a dielectric substrate, and these input / output impedance matching circuits are connected to the FETs by bonding wires. The gate end 8 and the drain end 9 are connection points on the input / output impedance matching circuit side of the bonding wire.

In the prior art described in the above-cited paper, the second harmonic is terminated under the short-circuit condition (the phase is 180 °) in the input impedance matching circuit. On the other hand, in the doubler amplifier of the present invention, the double-wave impedance of the double-wave impedance control circuit in the input impedance matching circuit is set to a condition that forms a resonance circuit with the input impedance of the FET 30 and the double-wave. In a doubler amplifier using an FET, harmonic balance analysis was performed using a non-linear FET model in order to clarify the effect of the input impedance of the second harmonic at the gate end of the FET on the multiplication characteristics. The FET used for the analysis typically has a total gate width W
g = 2.4 mm, saturation current = 1 A, and gate-source breakdown voltage = 25 V. Assuming a drain voltage of 8 V and a fundamental frequency of 2.5 GHz, a second harmonic (= 5 GHz)
The input impedance for z) was changed over the entire region on the Smith chart with Z ₀ = 50Ω. At this time, the output fundamental wave is short-circuited, and the input fundamental wave impedance Zin (f
₀ ) and output second harmonic impedance Zout (2f
₀ ) was fixed to the optimum value shown in FIG.

The Smith chart shown in FIG.
9 is an analysis result showing the relationship between the input side impedance and the multiplication gain for the second harmonic at the gate end when Bm is constant. The multiplication gain greatly changes depending on the value of the input-side double-wave impedance (phase angle and reflection coefficient) at the gate end, and the input-side double-wave impedance is shown in FIG.
+ J × 0) → (5.1 + j × 0) → (5.1 + j × 1)
It can be seen that good multiplication gain can be obtained by setting within the area surrounded by (5.1) → (0 + j × 15.1) → (0 + j × 0). For example, in the present embodiment, the second harmonic impedance control circuit 31 is set to 0.2 at the second harmonic wavelength.
By constructing the open-end stub having a length of 5 to 0.3 wavelength, the second-order impedance on the gate end input side can be reduced as shown in FIG.
Can be set in the area indicated by the oblique line.

In the chart of FIG. 9, (5.
1 + j15.1) is a point having an almost complex conjugate relationship with the input impedance of the FET with respect to the second harmonic. Therefore, the input impedance of the FET with respect to the second harmonic is Zi
n (2f ₀ ) and its conjugate complex impedance as Zin *
When (2f ₀ ) is set, the range on the Smith chart where a good multiplication gain can be obtained can be defined by the hatched portion in FIG. That is, the double-wave impedance at the connection point of the FET gate end of the input impedance matching circuit included in the multiplier amplifier is 0 + j × 0 → Re ｛Zin *
(2f ₀ )｝ + j × 0 → Zin * (2f ₀ ) → 0 + j ×
Im {Zin * (2f ₀ )} → set within a range surrounded by 0 + j × 0.

FIG. 11 shows the change in the multiplication gain when the phase is changed on the circumference of the reflection coefficient 1 with respect to the input-side second-order impedance at the gate end. In particular, the input double-wave impedance for obtaining the maximum multiplication gain is not a short-circuit condition (phase angle = 180 °), and the reflection phase angle is 156 °.
Met. It has been found that the input-side second-harmonic impedance condition ZS (2f ₀ ) at which the multiplication gain is maximum has the following relationship with the gate-source capacitance Cgsf at the time of forward gate bias of the FET. ZS (2f ₀ ) = j / (2π × 2f ₀ × Cgsf) (1) That is, the input-side double-wave impedance at the gate end of the FET included in the multiplier is determined by the forward gate bias of the FET. By setting the condition to resonate with the gate-source capacitance, the multiplication gain can be dramatically improved.
In the FET used in the above analysis, the gate-source capacitance Cgsf at the time of forward gate bias is 2.
9 pF.

FIG. 12 is a graph showing a voltage waveform at the gate terminal and a current / voltage waveform at the drain terminal for the multiplier (A) in which the input-side second-order impedance is set to resonate with Cgsf. FIG. 13 shows a voltage waveform at the gate terminal and a current / voltage waveform at the drain terminal for the multiplier (B) in which the input-side second-order impedance is short-circuited. Specifically, the multiplier amplifier (A) uses an open-end stub having a wavelength of the second harmonic and a length of 0.29 wavelength as a second-harmonic impedance control circuit to obtain a phase angle of the second-harmonic impedance on the input side. Was set to 156 °. The doubler amplifier (B) short-circuits the input-side double-wave impedance (phase angle = 180 °) using an open-end stub having a wavelength of the double-wave and a length of 0.25 wavelength as a double-wave reflection line. ). (A) corresponds to an embodiment of the present invention, and (B) corresponds to a conventional multiplier. In both doubled amplifiers, the fundamental wave was short-circuited on the output side, and the input fundamental wave impedance and the output double wave impedance were set to the optimum values shown in FIG.

The input frequency is 2.5 GHz and the input power is constant at 13 dBm. At this time, the multiplication gain from 2.5 GHz to 5.0 GHz was 9.3 dB in the multiplication amplifier (B), but was 13.1 in the multiplication amplifier (A).
It has improved dramatically with dB. The mechanism for improving the multiplication gain can be explained as follows. As shown in FIG. 13, the reflection phase of the second harmonic at the input side is set to 180 °
Although the second harmonic component is not seen in the gate voltage waveform of the multiplied amplifier (B), the reflection phase of the second harmonic at the input side is set to 156 ° as shown in FIG. Many second harmonic components are generated in the gate voltage waveform of the multiplier amplifier (A) of the present invention. The second harmonic of the gate voltage waveform is caused by the non-linearity of the gate-source capacitance of the FET included in the multiplier. In particular, the reflection phase of the second harmonic is matched with the gate-source capacitance. It is considered that many second harmonic components have occurred. Gate voltage waveform 2
As the second harmonic component increases, the second harmonic component included in the drain current increases. As a result, the second harmonic output to the drain terminal increases, and the multiplication gain to the second harmonic with respect to the input of the fundamental frequency is improved.

[Second Embodiment] FIG. 4 is a circuit diagram of a frequency multiplier according to a second embodiment of the present invention. While the input-side second-harmonic phase control circuit (the second-harmonic impedance control circuit 31) of the first embodiment is configured by an open-end stub,
In the frequency multiplier of this embodiment, a double-wave impedance control circuit of a short-circuited stub at the tip is employed. That is, in the present embodiment, the FET 30 having the source 7 grounded and the FET 30
And an output impedance matching circuit 43 connected to the drain side of the FET, and a second harmonic impedance control circuit 3 of the input impedance matching circuit 38.
3 is configured using a tip short-circuit stub.

The input impedance matching circuit 38 includes a second-wave impedance control circuit 33 for setting the gate-end input impedance for the second harmonic of the fundamental frequency to a range in which the second-wave input impedance of the FET 30 and the resonance circuit are formed. In addition, the input impedance of the fundamental wave is matched by the stub t1 and the matching lines L1 and L2. The second harmonic impedance control circuit 33 is connected to the gate terminal 8 of the FET 30.
Connected to. Since the output impedance matching circuit 43 is configured in the same manner as in the first embodiment, a detailed description thereof will be omitted. 2nd harmonic impedance control circuit 3
Reference numeral 3 denotes a series circuit of a stub 16 having an electrical length longer than a half wavelength corresponding to the second harmonic frequency and a capacitor 17 for grounding the stub 16. 2
The electrical length and line width of the line included in the harmonic impedance control circuit are defined so as to fall within the range of the oblique line in FIG. 10 or to satisfy the above equation (1) for the second harmonic frequency.

For example, the second-harmonic impedance control circuit 33 in the second embodiment is different from the FET used in describing the first embodiment in that the second-harmonic impedance control circuit 33 is more than a half wavelength of the second harmonic. It is composed of a short-circuited stub including a long line having a length of 0.5 to 0.6 wavelength. Thus, the impedance of the second harmonic on the input side at the gate end of the FET included in the multiplier is shown in FIG. 9 (0Ω +
j × 0Ω) → (5.1Ω + j × 0Ω) → (5.1Ω + j
× 15.1Ω) → (0Ω + j × 15.1Ω) → (0Ω +
j × 0Ω).
Also in the frequency multiplier of the present embodiment, the input-side second-harmonic impedance is set so as to fall within the range of the oblique line in FIG. 10 or to satisfy the above-mentioned formula (1). The effect of can be obtained.

[Third Embodiment] FIG. 5 is a circuit diagram of a frequency multiplier according to a third embodiment of the present invention. In the frequency multiplier of this embodiment, an LC series resonance circuit is adopted as the input-side second harmonic phase control circuit, instead of the open-end stub of the first embodiment or the short-circuited stub of the second embodiment. ,
As the output fundamental wave short circuit means, the first embodiment or the second embodiment
In place of the open end stub having a length of 1/4 wavelength of the fundamental wave in the embodiment, an LC series resonance circuit of the fundamental wave is employed. In summary, the microwave frequency doubler amplifier according to the third embodiment of the present invention comprises an FET having the source 7 grounded, an input impedance matching circuit 39 connected to the gate of the FET, and a FET connected to the drain of the FET. And an output impedance matching circuit 44 connected thereto, and doubles the frequency of the input signal to output.

The input impedance matching circuit 39 includes a second-harmonic impedance control circuit 34 for setting the input impedance at the gate terminal 8 for the second harmonic of the fundamental frequency within a predetermined range. The impedance matching for the fundamental wave is performed by the use inductor 24. The second harmonic impedance control circuit 34
It is connected to the gate terminal 8 of the FET 30. The output impedance matching circuit 44 includes the output fundamental short circuit 32 connected to the drain end and grounding the fundamental wave at the drain end,
The matching capacitor 23 and the matching inductor 25 match the second-order impedance on the output side.

The second harmonic impedance control circuit 34 is an LC series resonance circuit composed of the inductor element 18 and the capacitor 19 having one end connected to the inductor element 18 and the other end grounded. The inductance value of the LC series resonator and the capacitance value of the capacitor are set so as to fall within the range of the oblique line in FIG. 10 or to satisfy the above equation (1) for the second harmonic frequency. The output fundamental wave short-circuit means 32 is an LC series resonance circuit including the inductor element 20 and the capacitor 21 having one end connected to the inductor element 20 and the other end grounded. The inductance of the LC series resonator and the capacitance value of the capacitor are determined so as to satisfy the series resonance condition with respect to the fundamental frequency, whereby the fundamental wave is short-circuited to the ground point at the drain end and suppressed. Instead of the inductor element 18 of the second-harmonic impedance control circuit 34 and the inductor element 20 of the output fundamental wave short-circuit means 32, a line having an appropriate line length can be used. The matching capacitor 2
A stub may be used instead of 2 and 23, and a matching line may be used instead of the matching inductor. Also in the multiplier of this embodiment, the first-order double-sided impedance at the gate end is set so as to fall within the range of the oblique line in FIG. 10 or to satisfy the above equation (1). The same effect as the example can be obtained.

Fourth Embodiment FIG. 6 is a circuit diagram of a multiplier according to a fourth embodiment of the present invention. The input impedance matching circuit of the multiplier of this embodiment uses two or more stages of LC circuits without using the second harmonic impedance control circuit to achieve impedance matching of the fundamental wave and to set the input double harmonic impedance within a predetermined range. Set within. In summary, the microwave frequency doubler amplifier according to the fourth embodiment of the present invention includes an FET 30 having the source 7 grounded, an input impedance matching circuit 40 connected to the gate of the FET, and a drain connected to the FET. And an output impedance matching circuit 43 for doubling the frequency of the input signal and outputting it. The input impedance matching circuit 43 includes matching lines L1, L2, L3 connected in three stages.
And matching capacitors 26 and 27 connected between the connection point between the lines and the ground. The line lengths of the matching lines L1, L2, L3 and the matching capacitors 2
6 and 27 are appropriately set so that the input impedance of the fundamental wave is matched, and the input impedance at the gate end of the second harmonic is within the range of the hatched portion in FIG. The above equation (1) is satisfied.

The output impedance matching circuit 43 includes an output fundamental wave short-circuiting means 32 connected to the drain terminal 9 for short-circuiting a fundamental wave to a ground point at the drain terminal, and further includes a stub t3 and matching lines L4 and L5. The output impedance of the second harmonic is matched. The output fundamental wave short-circuit means 32 is constituted by a stub having a quarter wavelength of the wavelength corresponding to the fundamental wave frequency and having the other end opened. Since this stub appears short-circuited to the fundamental wave at the drain end and opened to the second harmonic, the fundamental wave is suppressed and the second harmonic passes. Also in the multiplier of this embodiment, the input side 2 as viewed from the gate end.
By setting the harmonic impedance so as to fall within the range of the oblique line in FIG. 10 or to satisfy the above equation (1), the same effect as in the first embodiment can be obtained. The same effect can be obtained even if the above conditions are satisfied by replacing the matching lines L1, L2, L3 with inductor elements.

[0036]

As described above, in the microwave frequency doubler according to the present invention, the impedance at the second harmonic viewed from the gate end of the input impedance matching circuit is FE.
Since it is controlled so as to resonate with the input impedance of T and the second harmonic, the second of the gate voltage waveform resulting from the non-linearity of the gate capacitance of the FET included in the multiplier amplifier.
The higher harmonic component can be increased, and the second harmonic component included in the drain current can be increased.
As a result, the second harmonic voltage appearing at the drain end can be increased, and the gain for multiplying the input of the fundamental frequency to the second harmonic can be dramatically improved.

In the input impedance matching circuit, the second-harmonic impedance control circuit or a circuit having the function is directly connected to the gate terminal of the FET, and the fundamental wave short-circuit means of the output impedance matching circuit is connected to the drain terminal of the FET. The matching line provided between the gate end and the second-harmonic reflection circuit, which is directly connected and exists in the conventional multiplication circuit, is omitted, and the drain end and the fundamental wave reflection circuit are omitted. Since the matching line between them is omitted, the size of the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a first embodiment of the present invention.

FIG. 3 is a circuit diagram of a first embodiment of the present invention.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a fourth embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation of the first embodiment of the present invention, showing the optimum values of the impedances of the input fundamental wave, the output double wave, and the output fundamental wave in the microwave multiplier amplifier of this embodiment. is there.

FIG. 8 is an analysis result showing a relationship between an input-side second-wave impedance and a multiplication gain of a microwave multiplication amplifier.

FIG. 9 is a Smith chart illustrating a preferred setting region of an input-side double-wave impedance at a gate end of an FET included in the microwave multiplier according to the present invention, for explaining the operation of the first embodiment of the present invention; is there.

FIG. 10 shows F included in the microwave multiplier amplifier of the present invention.
FIG. 7 is a Smith chart showing a preferable setting region of an input-side second-order impedance at a gate end of the ET.

FIG. 11 is an analysis result showing a relationship between an input-side second-wave impedance angle and a multiplication gain of a microwave multiplication amplifier.

FIG. 12 is a view for explaining the operation of the first embodiment of the present invention;
FIG. 4 is a diagram showing a gate terminal voltage waveform, a drain terminal current waveform, and a drain terminal voltage waveform of ET.

FIG. 13 is a diagram showing a gate-end voltage waveform, a drain-end current waveform, and a drain-end voltage waveform of an FET included in the conventional microwave multiplier amplifier (B).

FIG. 14 is a circuit diagram of a first conventional example.

FIG. 15 is a circuit diagram of a second conventional example.

[Explanation of symbols]

tl, t2, t3 Stub L1, L2, L3, L4, L5, L6 Matching line 1 Input terminal 2 Output terminal 3 Gate bias voltage supply terminal 4, 6 Choke coil 5 Drain bias voltage supply terminal 7 Source 8 Gate end 9 Drain Ends 10, 11 DC cut capacitor 12 Second harmonic reflection line 13 Fundamental wave reflection line 14, 15, 16 Stub 17, 19, 21 Capacitor 18, 20 Inductor element 22, 23, 26, 27 Matching capacitor 24, 25 Matching inductor 30 FET 31, 33, 34 Second harmonic impedance control circuit 32 Output fundamental wave short circuit means 35, 36, 37, 38, 39, 40 Input impedance matching circuit 41 Fundamental wave blocking circuit 42, 43 Output impedance matching circuit 100 Input impedance matching circuit 200 output Impedance matching circuit 300 FET 400 fundamental input impedance matching circuit 500 double wave impedance control circuit 600 fundamental shorting means 700 second harmonic output impedance matching circuit 800 double wave impedance control unit with the fundamental input impedance matching circuit

Claims (7)

(57) [Claims] 1. A field-effect transistor having a source grounded and performing a non-linear operation in a microwave band, and a field-effect transistor connected to a gate end of the field-effect transistor connected to a gate of the field-effect transistor. An input impedance matching circuit including a double-wave impedance control circuit capable of forming a resonance circuit for a frequency at or near twice the fundamental frequency together with the input impedance of the transistor, and a fundamental-wave input impedance matching circuit; Connected to the drain side of the field effect transistor,
A microwave having a short-circuit means for a fundamental frequency connected to a drain end of the field-effect transistor and an output impedance matching circuit including a second-wave output impedance matching circuit for impedance matching for a second harmonic of the fundamental wave. Frequency multiplier amplifier. 2. A field-effect transistor having a source grounded and performing a non-linear operation in a microwave band; and an input impedance of the field-effect transistor connected to the gate side of the field-effect transistor, which is twice the fundamental frequency. With an impedance capable of forming a resonance circuit for a frequency of or near the same, an input impedance matching circuit capable of matching the input impedance of the fundamental wave, and connected to the drain side of the field effect transistor,
A microwave having a short-circuit means for a fundamental frequency connected to a drain end of the field-effect transistor and an output impedance matching circuit including a second-wave output impedance matching circuit for impedance matching for a second harmonic of the fundamental wave. Frequency multiplier amplifier. 3. The input impedance matching circuit or the second-harmonic impedance control circuit includes a second-harmonic impedance at a gate terminal connection point, a conjugate complex impedance of a second-harmonic input impedance of the FET at a set bias, and Zin *. As (2f ₀ ), 0 + j × 0 → R
e {Zin * (2f ₀ )} + j × 0 → Zin * (2f
₀ ) → 0 + j × Im {Zin * (2f ₀ )} → 0 + j ×
3. The microwave frequency doubler according to claim 1, wherein the microwave frequency multiplier is set within a range surrounded by zero. 4. The input impedance matching circuit or
The second harmonic impedance control circuit is connected to the gate end.
Input second harmonic impedance ZS (2f ₀ ), Before
The gate of the field effect transistor at the time of forward gate bias is
Condition ZS (2f
₀ ) = J / (2π × 2f)₀ × Cgsf)
The microwave according to claim 1 or 2, wherein
Frequency multiplier amplifier. 5. The double-wave impedance control circuit,
2. The microwave frequency doubling according to claim 1, wherein the line has an electrical length longer than a quarter wavelength of the wavelength corresponding to the second harmonic frequency, and is constituted by a line whose other end is open. amplifier. 6. The double wave impedance control circuit according to claim 1,
An inductor element or a line having an electrical length longer than half the wavelength corresponding to the second harmonic frequency, and a capacitor having one end connected to the inductor element or the line and the other end grounded. 2. The microwave frequency doubler amplifier according to claim 1, wherein: 7. An input impedance matching circuit comprising: a plurality of series-connected matching lines or inductor elements; and a matching line connected between a connection point between the matching lines or inductor elements and a ground point. 3. The microwave frequency doubler according to claim 2, further comprising a capacitor.