JP2992394B2 - Multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control unit for controlling communication between a plurality of processing units and a communication control system between the processing units using the control unit.

[0002]

2. Description of the Related Art Conventionally, as described in Japanese Patent Application Laid-Open No. 57-6933, there is an invention on a processing method of a communication control device when an abnormal state occurs in communication between processing devices. In the above-described conventional technology, a processing device status register is installed for each processor connected to the communication control device, and the processing device status register stores whether an abnormality has occurred between the communication control device and the processor, When a data transfer command is issued, the start value or the data transfer process is controlled based on the value of the register. This prior art does not consider the control efficiency in the normal state of communication between processing devices.

Conventionally, when communication is performed between a plurality of processing apparatuses, a transmission source processing apparatus inquires of a plurality of other processing apparatuses whether or not reception is possible, and performs processing that can be received. Transmitting to the device.

[0004]

According to the above-mentioned prior art, the processing apparatus of the transmission source inquires of a plurality of other processing apparatuses whether or not reception is possible. Also, when the number of terminals connected to the processing device increases and the processing device has a large capacity, there is a problem that inquiries are complicated and the processing capability is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multiprocessor system capable of improving the efficiency of communication control between processing devices and performing sufficient control for large-capacity communication between processing devices.

[0006]

In order to achieve the above object, a plurality of processors for controlling communication, a transmission line connecting the processors, and a terminal or another relay device corresponding to each of the plurality of processors. In a multiprocessor system having a processing device connected to a processor for transmitting and receiving data, and a plurality of buffers for storing data corresponding to each processor and the processing device, a common processor capable of reading and writing from each processor It has a memory part,
The common memory unit has an empty buffer information area indicating whether each buffer is empty or not empty, corresponding to each of the plurality of buffers. By registering whether each buffer is free or not in the free buffer information area and referring to the free buffer information area at the time of transmission,
It has means for securing a buffer at the transmission destination.

The common memory unit has a reception-possible processing device registration area indicating whether or not a processing device can receive data from another processing device for each processing device. Register whether or not it is possible to receive data from another processing device in the receivable processing device registration area, and select the destination processing device by referring to the receivable processing device registration area when transmitting. Means can be provided.

Further, the common memory unit further includes a receivable processing device registration area for duplicating the receivable processing device registration area, and one receivable processing device registration area is used for registering a receiving processor. The other copyable receivable processing device registration area is used for rewriting of the transmitting processor at the time of transmission, and the processor refers to the copyable receivable processing device registration area at the time of transmission, and Select the processing unit,
Means may be provided for rewriting the registration area of the reception-possible processing device for duplication so as not to be receivable. The processor refers to the registration area of the reception-possible processing device for duplication at the time of transmission, and if all the registration areas of the reception-possible processing device for duplication are unreceivable, the reception-possible processing for registration of the processor on the receiving side. It has means for instructing to copy the contents of the device registration area.

[0009]

Each processor registers whether or not it is possible to receive data from another processing device in the receivable processing device registration area of the common memory unit, and registers the data in the free buffer information area of the common memory unit. Whether or not each buffer of the own device is empty or not is registered in a corresponding location.

At the time of transmission, each processor selects a destination processing device by referring to a copy-ready receivable processing device registration area, and secures a destination buffer by referring to an empty buffer information area. However, it is possible to rewrite the reception-possible processing device registration area for duplication to be unreceivable.

Further, when the processor refers to the registration area for registering the reception-capable processing apparatus for duplication, if the registration area for registration of the reception-possible processing apparatus for duplication is completely unreceivable, the processor for registration of the reception-side processor can receive the registration. Instructs to copy the contents of the processable device registration area.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of the present invention, wherein reference numeral 1a denotes an inter-processing device communication control unit (hereinafter simply referred to as a control unit). The multiprocessor system shown in this embodiment can be used for, for example, a central processing system of a digital exchange. In the control unit 1a, the common memory 1b
(CM) and multiple microprocessors (PC1d, 1e, 1
f, 1g) are connected by a common bus 1c. The common memory CM1b can read and write from each microprocessor. In the common memory CM1b, a reception enable processing device registration register R used as a common resource is stored.
EW and empty buffer information register BRF. When the common memory CM1b is a RAM or the like, a receivable processing device registration area and an empty buffer information area may be provided. Each register will be described later. Each microprocessor has a corresponding processing unit (SP1h,
1i, 1j, 1k) are connected by 1 or 2 or more. That is, each microprocessor connected to each processing device controls communication on the bus. Further, each microprocessor can have a buffer for temporarily storing data for data transfer, a transmission register, a reception register, and a transfer end display register. Controls communication over a common bus. In addition, the buffer may be provided outside each microprocessor or inside the processing device, instead of inside each microprocessor. The buffer can read and write data transmitted and received from the processing device, and has a plurality of areas. The microprocessor can instruct the buffer to send or receive to the bus. A bus arbiter that controls the bus is connected to the common bus 1c. When transmitting data on the bus, each microprocessor starts transmission after obtaining permission from a bus arbiter that controls communication on the bus. The common memory CM1b may be included in the bus arbiter. Further, terminals such as a telephone, a facsimile, and a data terminal, other relay devices, exchanges, and the like are connected to each processing device via a line, and the processing device performs line control. In this configuration, each processing device can communicate with each other under the control and processing of the corresponding microprocessor, and can refer to and rewrite the register in the corresponding microprocessor.

FIG. 2 shows a procedure of communication control in the control unit having the configuration shown in FIG. In the case where the processing device 1i shown in FIG. 1 performs transmission and the processing device 1k performs reception, the procedure of communication control of the microprocessor in the control unit corresponding to each processing device will be described with reference to FIG. explain. The configuration of each register in the processing device in transmission and reception and the configuration of the register in the common memory CM will be described with reference to FIGS.

In FIG. 2, the leftmost part shows the processing operation of the microprocessor 1e (hereinafter referred to as the transmission microprocessor) corresponding to the transmission processing unit 1i, the middle part shows the register on the common memory CM, The right part shows the processing operation of the microprocessor 1g (hereinafter referred to as the reception microprocessor) corresponding to the reception processing device 1k.

The microprocessor has a reception register and a buffer. This configuration is shown in FIG.
(B), FIG. 3 (c) and FIG. 4 (a).

FIG. 3B shows a configuration example of the reception control word RCW. In FIG. 3B, a one-word reception control word (RCW) is provided in a specific area of a memory in a microprocessor in correspondence with a reception buffer, and the processing device sets a reception source memory start address RMA in the reception control word RCW as: Set the start address of the receive buffer. In the reception source memory start address RMA, the start address of each area of the reception buffer is set in advance. The RFLG indicates whether the reception buffer area specified by the reception source memory start address RMA is empty (buffer empty = 0) or is full (buffer full = 1). Is set to 0, and is rewritten to 1 when data transfer is received.

FIG. 3C shows a configuration example of the reception buffer. The microprocessor uses the source processor subsystem number SPN as reception control information when receiving data.
After writing the destination processor subsystem number DPN and the number of transfer words WC at the head of the reception buffer, the RFLG of the reception control word RCW is rewritten to 1. The processing device detects the arrival of data with reference to the reception control word RCW.

FIG. 4A shows a transfer end display register TEF.
Is shown. In FIG. 4A, a transfer end display register TEF assigns one bit to each area of the reception buffer in the microprocessor, and indicates whether the buffer area is ready for reception (or receiving) or reception is completed. It is a register shown. The receiving process in this case is
After the transfer data is received by the receiving microprocessor from the transmission destination microprocessor, the data is transferred to the processing device or sent to the line. The area of the reception buffer corresponds to the reception control word RCW shown in FIG. When the data transfer is completed, the processor sets the corresponding bit to 0,
When transfer processing is possible, the receiving microprocessor sets 1 in the receiving supplementary processing.

The registers on the common memory CM are shown in FIG.
And FIG. 4 (b).

FIG. 6 shows the configuration of the receivable processor registration register REW on the common memory CM. Common memory C
The receivable processing device registration register REW on M corresponds to each microprocessor, and which microprocessor corresponds to the bit position of the register is set in advance for all microprocessors. If the reception is possible, the receiving microprocessor sets a bit to 1 at a position corresponding to the own device in the reception enable processing device registration register REW. The receivable state refers to a state in which the microprocessor and the processing device start up and can communicate. In FIG. 6, the reception enable processing device registration register REW
Reference numeral 1 denotes a register dedicated to registration from the receiving microprocessor, and a register for registering receivable processing device REW2 duplicates the register for registering receivable processing device REW1 and is dedicated to access from the transmitting microprocessor. In the initial state, all the bits of the reception enable processing device registration register REW1 and the reception enable processing device registration register REW2 are set to 0, and the corresponding bit is set to 1 by registration from the receiving microprocessor. FIG. 6 shows an example in which two reception processing devices corresponding to the two bits from the right of the reception enabled device registration register REW1 are registered. Reception enable processing device registration register REW
When all the bits of 2 are 0, the contents of the receivable processing device registration register REW1 are copied to the receivable processing device registration register REW2 by transmission processing upon access from the transmission microprocessor. After that, in the transmission process, a search is made for a bit that is 1 using the reception enable processing device registration register REW2, and after the reception processing device is selected, the bit corresponding to the selected reception processing device is updated to 0. A method of using the two receivable processing device registration registers REW will be described later.

FIG. 4B shows a configuration example of the empty buffer information register BRF on the common memory CM. The empty buffer information register BRF is a register indicating whether the buffer is empty or closed according to the buffer of the reception processing device. When the reception processing of each reception processing device performs a reception process, when the buffer is empty, 0 is stored in the bit corresponding to the buffer. During use, 1 is written to the bit corresponding to the buffer.

First, the processing operation of the receiving microprocessor will be described.

In FIG. 2, when the receiving microprocessor starts up and becomes a receivable processing device, the receiving microprocessor registers the receivable processing device registration register REW on the common memory CM for use as a common resource. Is registered as a receivable processing device. Next, the receiving microprocessor checks the transfer end display register TEF in the microprocessor as a process for searching whether or not there is a free buffer. The receiving microprocessor searches the transfer end display register TEF and reads out the reception control word RCW indicating the head address of the reception buffer area corresponding to the bit in which the transfer processing end is set to 0. The receiving microprocessor sets the bit of the transfer end indication register TEF to 1 to indicate that the transfer is possible. Further, the corresponding bit of the empty buffer information register BRF on the common memory CM indicates that the buffer is empty.

As described above, each microprocessor periodically executes the empty buffer supplementary processing until the reception is started from the transmission processing.

Next, the processing operation of the transmitting microprocessor will be described.

The microprocessor has a transmission register and a buffer. FIG. 3A shows the configuration of this register.

FIG. 3A shows a configuration example of a transmission request display word and a transmission request control word in the transmission buffer. A 1-word transmission request display word (SRW) is provided in a specific area of a memory section in the microprocessor, and when a communication request occurs, the processing device sets presence / absence of a transmission request corresponding to bits in the word. Further, a transmission request control word (SCW) is provided corresponding to the bit of the transmission request indication word (SRW). here,
Source processor subsystem number (processing unit SP
N), the source memory start address (SMA), the destination processor subsystem number (DPN), and the number of words to be transferred (WC) are provided, and when there is a transmission, the control device writes control information. Destination processor subsystem number DPN
Has a DFLG portion indicating whether or not there is a designation of a transmission destination. If there is a designation, 0 is set; otherwise, 1 is set. If specified, transmission is performed based on the destination processor subsystem number DPN. If there is no designation, a destination processor can be arbitrarily selected. The number of transfer words (WC) indicates how many transfer data are present in word units. In the example of FIG. 3A, two transmission requests exist on the transmission request display word (1
, There is a request, and if it is 0, there is no request), and its control information is set in transmission request control words # 0 and # 1, respectively. In the case where it is not necessary to specify a transmission destination in performing the load distribution processing (the transmission may be performed to an arbitrary subsystem), the DFL of the transmission destination processor subsystem number DPN may be used.
Set 1 to G. (If DFLG = 0, the designation of the destination processor subsystem number DPN is valid.)

A communication request generated from each processing device is detected on the microprocessor side according to the following procedure, and data transfer is executed.

When each processing device receives a transmission request from the line side, it sets the presence or absence of a transmission request in a transmission request display word (SRW) and sets control information in a transmission request control word (SCW).

Next, the transmission microprocessor reads the transmission request display word SRW and detects the transmission request. SF
It is assumed that there is a transmission request when LG = 1 and there is no transmission request when SFLG = 0. If there is a transmission request,
The transmission microprocessor controls the corresponding transmission request control word S
The destination processor subsystem number DPN of the CW and the information of the receivable processor registration register REW on the common memory CM are read. If there is a transmission destination processor subsystem number DPN, it is determined whether or not the corresponding processing device can receive data by referring to the receivable processing device registration register REW. Destination processor subsystem number DP
If there is no N, the receivable processing device registration register REW
To select a receivable processing device.
After selecting the reception processing device, the transmission microprocessor sets 1 to secure a buffer in the corresponding bit of the empty buffer information register BRF. Next, based on the designation of the source memory start address SMA and the number of words WC to be transferred, data transfer is performed to the secured destination empty buffer area. The transmission microprocessor adds the bit number of the empty buffer information register BRF to the transfer data. The receiving microprocessor determines the receiving control word RCW from the bit number.
The area of the reception buffer is designated with reference to the reception source memory start address RMA in the table. Alternatively, the transmitting microprocessor directly refers to the receiving source memory start address RMA in the receiving control word RCW in the receiving microprocessor,
It may be transferred. When the transfer is completed, a start instruction is issued to the receiving microprocessor so that the receiving microprocessor causes the receiving processing device to perform the receiving process. The transmission process can periodically execute the transmission request detection process until the data arrival notification by the reception process returns.

In the receiving process, when the receiving microprocessor is activated for the receiving processing device to perform the receiving process, the receiving microprocessor transfers the data in the buffer to the corresponding processing device, or It is sent to the line as it is. After the end of the transfer, the processor sets the corresponding bit of the transfer end display register TEF to 0. Further, after notifying the transmitting microprocessor of the data arrival, the receiving microprocessor returns to the above-mentioned periodic empty buffer supplementary processing, and checks the transfer end display register TEF again.

In the transmission process, upon receiving the data arrival notification from the receiving microprocessor, the transmission completion notification is sent to the processing device, and then the process returns to the transmission request detection process described above.

As described above, by independently performing the transmission processing and the reception processing in each microprocessor, the processing of each microprocessor can be performed in parallel, and efficient communication can be performed. For example, the transmission process can be performed at the same time as the process of supplementing the empty buffer periodically during reception.

The above is the operation of the inter-processing device communication control in the present embodiment. The processing operation for realizing the equal allocation of the processing device communication in the present embodiment will be described below by referring to the bit change of the register used. This will be described in detail with reference to FIG.

FIG. 5 shows a procedure for selecting a receiving microprocessor in the communication control processing operation. In FIG. 5, REW1 and REW2 are reception enable processing device registration registers REW shown on the common memory CM in FIG. 2, have bits corresponding to each reception processing device, and operate the reception enable processing device by processing of the reception microprocessor. 1, 0 indicates the reception impossible processing device. In FIG. 5, when the microprocessor itself is capable of receiving, the microprocessor sets 1 to a corresponding bit of the receivable processing device registration register REW1. Reception enable processing device registration register R
When EW2 is all 0 and there is an instruction by a transmission request from the transmitting microprocessor, the receivable processing device registration register REW1 is stored in the receivable processing device registration register REW2.
Copy the contents of When the transmitting microprocessor accesses the receivable processing device registration register REW2, a T & S instruction (Test and Set) for performing exclusive processing is used. That is, while one transmission microprocessor accesses the reception enable processing device registration register REW2 and is transferring data, access from another transmission microprocessor is excluded. After the data transfer is completed, the transmission microprocessor sets the reception enable processing device registration register REW2 to 0. The receivable processing device registration register REW2 is released to enable access to the receivable processing device registration register REW2 for transmission processing of another transmission microprocessor. Also, the receivable processing device registration register REW
When all the bits of 2 become 0, if there is an instruction again by the transmission request from the transmission microprocessor, the contents of the reception enabled processing device registration register REW1 are copied to the reception enabled processing device registration register REW2. Since the receivable processing device registration register REW1 can be accessed, the receiving microprocessor can set a bit when the receiving device itself starts up and becomes receivable.

By performing these processings by each transmitting microprocessor, each microprocessor can perform the processing in parallel, and a system that guarantees exclusivity can be constructed.

Further, after the registration of the reception processing device, the reception microprocessor registration register RE by the transmission microprocessor.
The access to W2 has a characteristic that, when the transmission destination is not determined, the search is performed in order from the youngest (0th bit) of REW2, and the first detected bit of 1 state is updated to 0 state. Let As a result, the transmission microprocessor sequentially selects the registered reception processing devices from those corresponding to the youngest number (0th bit) of the reception enabled device registration register REW2.

In this embodiment, the following effects can be obtained by providing the receivable processing device registration register REW2. The data of the initially registered reception processing device (reception-possible processing device registration register REW1) is copied to the reception-possible processing device registration register REW2 by transmission processing, and all registered reception processing devices are used (reception). The re-registration of the reception processing device is not performed until all the bits of the processable device registration register REW2 become 0). When the reception enable processing device registration register REW2 is not provided, the registration contents of the reception enable processing device registration register REW1 are updated by the registration request of the reception processing device. If this is done, the reception processing device corresponding to the bit closest to the youngest (0th bit) is preferentially selected, and uniformity is not guaranteed in the selection of the reception processing device. In the present embodiment, by the above-described series of processing, concentration of reception processing device selection is avoided, and uniformity in reception processing device selection can be guaranteed.

In this series of processing, an empty buffer is
It is also effective when assigning to the transmission microprocessor. In the empty buffer information register BRF shown in FIG. 2, by using the register exclusively for registration and the register exclusively for selection and performing access from the transmission microprocessor by T & S, double selection of empty buffers and concentration of selection into one empty buffer Can be avoided, and efficient communication processing can be performed.

That is, by using the present invention, the control unit can efficiently distribute the load, and the communication efficiency between the processing devices can be improved.

As described above, according to the present embodiment, parallel processing can be performed, and when a plurality of transmission microprocessors select a reception processing device and an empty buffer, exclusivity and uniformity are guaranteed. Thereby, communication efficiency can be improved.

[0043]

According to the present embodiment, in a multiprocessor system, it is possible to improve the efficiency of communication control between processing devices and perform sufficient control for communication between large-capacity processing devices.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a communication control unit between processing apparatuses according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an embodiment of a communication control procedure between processing devices in the present invention.

FIG. 3 is an explanatory diagram showing an example of the configuration of a register used in communication control between processing devices according to the present invention.

FIG. 4 is an explanatory diagram showing an example of a configuration of a register used in communication control between processing devices in the present invention.

FIG. 5 is an explanatory diagram showing an embodiment of receiving processor selection in the present invention.

FIG. 6 is an explanatory diagram showing an example of the configuration of a register used in communication control between processing devices according to the present invention.

[Explanation of symbols]

1a: communication control device between processing devices, 1b: common memory, 1
c: bus, 1d, 1e, 1f, 1g: microprocessor, 1h, 1i, 1j, 1k: processing device.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-257356 (JP, A) JP-A-60-3051 (JP, A) JP-A-3-22067 (JP, A) JP-A-1- 177658 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 13/00 G06F 15/163

Claims (3)

(57) [Claims] 1. A plurality of processors for controlling communication, a transmission line connecting the processors, and a processing device for transmitting and receiving data by connecting to a terminal or another relay device corresponding to each of the plurality of processors. A multi-processor system having a plurality of buffers for storing data corresponding to each of the processors and the processing devices, wherein the multi-processor system has a common memory unit that can read and write from each processor; If a processing unit receives data from another processing unit,
Each processing unit determines whether it is possible to receive data
Area for registering a receivable processing device,
And a receivable processing device registration area for duplicating the device registration area.
The registration area for registration, and the registration area for other copyable reception processing devices
For rewriting of the receiving processor, the processor sets the receivable processing device registration area for the registration.
Area can receive data from other processing devices.
Register whether or not there is
Refer to the processing device registration area and select the source processing device.
To write the receivable processing device registration area to unreceivable.
A multiprocessor system comprising means for switching . 2. The multiprocessor system according to claim 1,
In Temu, the processor, upon transmission, with reference to the receivable processing apparatus registration area for the replication, in the case of all receivable processing apparatus registration area for steel plurality unreceivable is the registration of the receiver-side processor A means for instructing to copy the contents of a receivable processing device registration area for a multiprocessor system. 3. The method according to claim 1, wherein
In the multiprocessor system of the present invention, the common memory section corresponds to each of a plurality of buffers.
Free buffer indicating whether each buffer is free or not
And a processor information area , wherein the processor is provided corresponding to the processor.
Each buffer in the free buffer information area of the buffer
There is registered or not empty or empty, at the time of transmission, sky-out buffer
The buffer of the transmission destination by referring to the
A multi-function device further comprising means for securing
Processor system.