JP2986045B2 - Method and apparatus for power management in a video subsystem - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to computer system power management, and more particularly, to the power management of portable and non-portable computer video subsystems.

[0002]

BACKGROUND OF THE INVENTION The demand for modern video subsystems is continually increasing. Pixel frequency continues to increase with the number of functions performed by the video subsystem. As pixel frequency and functionality increase, power requirements and power consumption also increase. However, previous design changes that accommodate the increasing pixel frequency and functionality of the video subsystem have long left concerns about power waste without optimizing power savings. Although such concerns are associated with non-portable computers, they are even more acute in the portable computer market where computers consume battery power.
Extending battery life has become a major concern for users.

[0003] Computer graphics systems exist in many forms. A typical system is the workstation 10 shown in FIG. The system bus 12 includes a CPU 14, a read-only memory (ROM)
16, a random access memory 18, a disk drive 20, a user interface 22 such as a keyboard and mouse, and a video subsystem 24 are connected. The video subsystem also includes a display
Also known as an adapter. Display device 26
Are connected to the video subsystem 24. Since such graphics systems are known to those skilled in the art, no details regarding their operation are required.

The video subsystem 24 includes a graphics controller 28 and a dual port including a RAM portion 31 and a serial access memory portion 32 (SAM), as shown in the expanded block diagram of FIG.・ Video random access memory 30 (V
RAM) and a parallel-to-serial conversion circuit palette digital-to-analog converter 34 (SPDAC). Graphics controller 28 controls the transfer of data from RAM portion 31 of VRAM 30 to SAM portion 32 on line 33 and VRAM update port 35. The serial data is sent from the RAM 31 to the SAM 32 and the SAM
From port 36 is sent to SPDAC 34 on line 38. Line 40 represents the programming interface to SPDAC controlled by controller. The basic operation of such a video subsystem is well known in the art.

[0005]

It is especially the video subsystem 24 and the SPDACs 34 that are in saturation that their power consumption must be reduced. The power consumption of a typical SPDAC chip implemented by CMOS technology includes both AC (alternating current) and DC (direct current) components.

As is known in the art, AC
Power consumption is directly proportional to operating frequency. Therefore, power consumption increases as the operating frequency increases. As is known to those skilled in the art, the power consumption in CMOS technology is the product of the steady-state power (ie, when the frequency is 0), the proportional constant, the circuit capacity, the square of the operating voltage, and the operating frequency. Approximate by the combination with Some of these power consumption components can be considered for reducing power consumption. For example, changing from 5 volts to 3 volt technology can reduce operating voltages. Capacitance can also be reduced by improving the design or switching off unused circuits. In addition, steady-state power can be reduced by improving the design of the CMOS circuit or by switching off when not in use. Design changes involve expensive replacement of hardware. Thus, while improved designs may become practical in the future, the problem of power consumption must be solved based on existing systems. The same can be said for the change of the operating voltage.

[0007] Prior art solutions to the problem of video subsystem excess power consumption include static power management.
This type of solution only provides power savings when the video subsystem is not running. For example, many SPDA
C is a standby type when the analog power is shut off (STA
NDBY type) mode of operation, but the pixel clock remains active so that data can be input at any time. A running clock wastes digital power unnecessarily. Some SPDACs are also dormant (SLEE) when analog and digital power interruptions occur.
P-type) operation mode. However, power savings
Implemented only while not in use. Static power management techniques cannot easily handle power savings during normal video subsystem operation.

[0008] Under these circumstances, there is a need for practical power management of existing video subsystems that does not replace existing hardware and can save power during normal operation.

[0009]

SUMMARY OF THE INVENTION In summary, by providing a method or apparatus for turning off subsystem circuits when not needed or used, the present invention provides a method without replacing existing hardware. Satisfies the need for practical power management of existing video subsystems, which can save power during normal operation.

In a first embodiment of the present invention, there is provided a method and apparatus for dynamic power saving during a display blanking operation. Therefore, a blanking signal (blanking signal) is monitored. In response to the detection of the blanking signal, the CMOS digital circuit of the functional device in the video subsystem that is not used during the blanking is
It is cut off together with the C analog circuit. When the blanking signal is no longer detected, the functional unit and the DAC analog circuit are turned back on.

In a second embodiment of the present invention, a method for functional power saving based on a system operating mode at the time of use is disclosed. In certain modes of operation, certain video subsystem functional units may not be used. Thus, any video subsystem functional unit not used in a given mode of operation can be shut down by shutting down the clock to its digital circuits.

In a third embodiment of the present invention, a power saving method and apparatus for a computer system that may be connected to either a monochrome or color display is disclosed. A display signal is generated to indicate which type is currently. Monochrome
In response to a display signal indicating that the display is currently in use, all but one of the digital-to-analog converter (DAC) circuits are shut off.

A liquid crystal display (LCD) and a liquid crystal display controller (LCD) for driving the LCD
C) and S for driving an external CRT display
Portable computer systems with PDACs can achieve further power savings according to a fourth embodiment of the present invention. When LCDC drives LCD, SP not used while LCD is driven
The DAC and all other video subsystem functional units can be shut down. Similarly, the LCDC can be shut off while the subsystem is driving an external CRT display.

In a fifth embodiment of the invention, a portable computer system that can operate in a SUSPEND state where no processing occurs and no display data is presented on the display achieves even more power savings. . Therefore, a signal indicating that the vehicle is about to enter the suspension state is monitored. Such SUSPEN
In response to the detection of the D signal, functional units in the video subsystem that are not used during the suspend state are shut down. In response to the system input, the video subsystem functional unit turns back on.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments of the invention and the drawings.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The video subsystem envisioned by the present invention includes a parallel-to-serial converter palette digital-to-analog converter (SPDAC). SPDACs have several sub-circuits, including digital CMOS circuits. In this specification, these sub-circuits are referred to as “functional devices”. The digital circuit of each functional device operates according to a clock signal. SPDACs also include several digital-to-analog converters (DACs). Each DAC includes digital and analog circuits having a constant current reference associated therewith.

The video subsystem of the present invention also includes:
It includes a blanking period known to those skilled in the art as a time interval during which pixel data is not presented on the display. The blanking time interval occupies between 25% and 40% of the total display time and takes two forms. Horizontal blanking occurs when the electron beam reaches the end of a display line and is returned to the beginning of the next display line.
During this beam reset time, the phosphor is still energized so that the user does not see a blank screen. Vertical blanking occurs when the beam reaches the bottom of the screen and is returned to the top. As with horizontal blanking, the user does not see the actual blank screen. Video subsystem power management in accordance with the present invention includes both forms of blanking. Thus, in this specification, reference to "during blanking" includes both horizontal and vertical blanking.

As is known by those skilled in the art, D sends an analog signal representing a pixel color to a display.
The output of AC is zero during blanking. This zero output is achieved in two ways. The digital DAC circuit is zeroed (ie, inputs data consisting of zeros) and then shut off while retaining the zero data, thereby keeping the DAC analog output at zero. Another way is to shut off the analog DAC circuit,
No data is output from the DAC regardless of the contents of the DAC digital circuit. Thus, blanking zero output is achieved by either digital DAC zeroing and blocking, or analog DAC blocking, or preferably both. By achieving zero DAC in this way, significant power savings are also realized.

In a first embodiment of the present invention, a method is provided for reducing the power consumption of a video subsystem, such as video subsystem 24 shown in FIG.
The blanking signal is generated by controller 28 during blanking. The generation of the blanking signal is known to those skilled in the art. The first implementation of the present invention begins with monitoring such a blanking signal. In response to the finding of the blanking signal, power to sub-circuits in the video subsystem not used during blanking is turned off. When the blanking signal is no longer detected, power to the secondary circuit is restored.

By turning off the clock signals required for the digital circuits to operate, the sub-circuits (ie, functional units), including the CMOS digital circuits, are turned off. Similarly, by turning on the clock signal, the digital circuit is turned back on. Digital-to-analog converters on video subsystems that present analog display data to a display often have a constant current reference associated with the analog circuitry therein. With the constant current reference turned off, the DAC analog circuit
Consumes little power. Thus, in the environment of using the DAC analog circuit in the first embodiment, the power interruption to the analog circuit is realized by turning off the constant current reference associated therewith. By turning on the constant current reference, power to the DAC analog circuit is restored. A specific example of a circuit that implements the first implementation method is shown in FIGS. 5 and 6, and will be described in detail herein.

Blanking is 25% of total display time
And 40%, the power management method of the first embodiment can save substantially the same amount of power. The clocks for all digital circuits not used during blanking and the constant current references for the analog circuits of each DAC are turned off during blanking. Clock and current reference cut-off turns off associated circuitry during blanking,
Save power effectively.

The method of the first embodiment of the present invention is also applicable to a portable computer equipped with a liquid crystal display (LCD) and capable of displaying simultaneously on the LCD and an external CRT display. Such portable computers also perform blanking so that the LCD and the external CRT display are synchronized. L to control LCD
The CD controller has digital circuitry that can be shut off during blanking, similar to the video subsystem digital circuitry in non-portable computer systems.

In a second embodiment of the present invention, a method is provided for reducing power consumption of a video subsystem based on an operation mode. Clock signals to a given functional unit can be blocked independently of other functional unit clock signals. In its simplest form, video
The subsystem is equipped with two functional units and can operate in two different operating modes according to the invention. In the first operation mode, the first functional device is used, but the second functional device is not used. In the second operation mode, the second functional device is used, but the first functional device is not used. Therefore, the current mode of operation must be monitored. In response to operation of the first mode of operation, the clock to the first functional unit is turned on and the clock to the second functional unit is turned off. Similarly,
In response to operation of the second mode of operation, the clock to the second functional device is turned on and the clock to the first functional device is turned off.

The second embodiment of the present invention will be described below. FIG. 3 is a block diagram representation of a commercially available SPDAC 35 that can be used as an example in the video subsystem 24 of FIG. The parallel-to-serial conversion circuit 42 is a SAM
Take data from port 36 and convert it to a stream of one pixel wide information. Text / attribute logic circuit 44
Is a logical mechanism for retrieving text fonts and their attributes. Multiplexer 46 is connected to direct serial data path 43 on line 45 or text / attribute logic 4.
4 allows the output signal to reach the Palette Static RAM (PSRAM) 50 based on the mode control 60. Direct color logic circuit (DIRC
The OL 48 bypasses the PSRAM 50 and performs color control directly without passing through the color lookup table (that is, the PSRAM 50). Sprite logic 52 controls the graphics cursor on the display. The multiplexer 56 includes a DIRCOL 48, a PSRAM5
Enable the output signal of a zero or sprite logic 52 to reach DAC macro 58 based on DAC input select 54. The DAC macro 58 has three DAs.
C, that is, DACs that produce analog pixel display signals representing red, green, and blue, respectively. The operation of SPDAC 35 will already be understood by those skilled in the art based on the above description.

The programming interface 40 of FIG. 2 includes the mode control 60 and the external clock signal on line 62 and the voltage controlled oscillator 64 in FIG.
And the clock control 66 on line 68 and the internal clock. It will be appreciated that a clock control signal on line 68 is provided for each functional unit clock in SPDAC 35 (not shown). Clock control 66 only provides for programming of the functional device clock. SPDA
C35 includes several sub-circuits implemented in digital circuits. Sub-circuits including digital circuits are referred to as “functional devices”. The functional units of the SPDAC 35 include a parallel / serial conversion circuit 42, a PSRAM 50, a DIRCOL 48, a text / attribute logic (TATR) 44, and a sprite logic (SPRLO) 52. SPDAC
35 and most SPDACs operate in several different modes. For example, SPDAC 35 is used for other SPs.
Like the DAC, it has a text mode and two graphics modes. Not all functional units are used in any given mode. Thus, by turning off the clock during a given mode, unused functional devices can be shut down, providing significant digital power savings.

In the text mode, the parallel / serial conversion circuit 42, PSRAM 50 and TATR 44 are operating, but DIROL 48 and SPRLO 52 are not operating. Thus, while operating in text mode, D
IRCOL 48 and SPRLO 52 can be shut off, that is, their clocks can be turned off. Although not typical, it will be appreciated that SPRLO 52 may operate in text mode.

Similarly, in the first graphics mode, the mode parallel / serial conversion circuit 42 and the PSRAM 50 operate. DIRCOL48, TATR44 and SP
RLO 52 can be shut off. In the second graphics mode, the parallel / serial conversion circuit 42 and DIRCOL 48 operate, while the PSRAM 50, TATR 44 and SP
RLO 52 can be shut off. It will be appreciated that SPRLO 52 may operate in any graphics mode.

In a third embodiment of the invention, the computer system includes a color display or a monochrome display. Power savings are possible if a monochrome display is used and the video subsystem can support either a color or monochrome display. If the video subsystem supports a color display, several DACs, each supporting each base color, will typically be included. For example, many video subsystems have three DACs that generate analog pixel display signals representing red, green, and blue, respectively. When a monochrome screen is used, only one DAC needs to be active.

A third embodiment of the invention begins by generating a display signal indicating whether a color display or a monochrome display is being used in the computer system. Whether a color display or a monochrome display is used in the computer system, for example,
It will be appreciated that the identification can be by system software or by the user entering the type of display used. The presence of such a display signal indicates that a monochrome display is being used in the system, and the absence of such a display signal indicates that a color display is being used. Preferred for the invention. The display signal is monitored for that, and in response to the display signal indicating that a monochrome display is connected, the power of all but one DAC is turned off.

As mentioned above, the DACs in the video subsystem of the present invention include both digital and analog types of circuits. Thus, when a monochrome display is connected, both digital and analog circuits are shut off for maximum power savings. Unused DACs
The clock to the digital circuitry within is turned off to turn off the digital circuitry. Similarly, the constant current reference for the analog circuit in each unused DAC is shut off to shut off that analog circuit. A specific example of a circuit that implements the third embodiment of the present invention is shown in FIGS.
And described in detail later in this specification.

In a fourth embodiment of the present invention, a method for reducing power consumption of a video subsystem in a portable computer system is presented. The portable computer system includes a liquid crystal display (LCD) and an LCD controller (LCDC) for driving the LCD. Relatively large portable
Computers are often used inside and outside the office.
These portables are powered by AC (alternating current) power in the office and may connect to an external CRT display. Such portable computer systems include SPDACs that drive external CRT displays. When an LCD is used, SPDACs and other video subsystem functional units used to drive the external CRT display need not operate because the LCD takes digital data but not analog data. Similarly, when the computer drives an external CRT display, the LCDC need not operate.

This fourth implementation is presented here. FIG. 4 is a general block diagram of the SPDAC 70. Video data from the VRAM serial port (SPRAM port 36 in FIG. 2) goes to a serializer 72 on line 74. The output signal of the parallel-to-serial conversion circuit 72 is output from a palette SRAM (PSRAM) 7 on line 78.
Sent to 6. Palette update control 78
The RAM 76 is controlled. DACs 80, 82 and 84
Is the PSRAM on lines 86, 88 and 90, respectively.
It receives 76 digital outputs. A plurality of input shift registers (MISR) 92 receive output signals from PSRAM 76. The MISR 92 is a functional device used for fault diagnosis. The palette update control 78 and MISR 92 are controlled on a programming interface 94 (line 40 in FIG. 2). LCD98
Is shown in FIG. If the external CRT display 100 is being driven, the LCDC 96 need not operate. Similarly, L
If the CD 98 is driven, the SPDAC 70
There is no need to work.

The method of the fourth embodiment starts by generating a display signal indicating that driving of either an LCD or an external CRT display is required. As in the third implementation, which type of display is being driven can be interpreted, for example, by system software or by user input.
Will be appreciated. It is preferred for the present invention that the display signal indicates that an LCD drive is required. The absence of the display signal indicates that the driving of the external CRT display is required. All functional units and other sub-circuits of the video subsystem that are not used during normal operation of the portable computer system (i.e., the functional units used to drive the external CRT display) are driven by the LCD. Blocked in response to a display signal indicating that it is being sought.

The LCDC 96, palette update control 78, PSRAM 76 and MISR 92 are functional units. Although DACs 80, 82 and 84 are functional devices, they also include analog circuitry with a constant current reference associated therewith. As in the first embodiment, the functional device is shut off by turning off the clock,
By closing the constant current reference, an analog circuit having an associated constant current reference can be shut off. In this way, the LCDC 96 can be shut off when the display signal indicates that driving of the external CRT display is required. If the display signal indicates that driving of the LCD 98 is required, all functional devices and analog circuits having a constant current reference used to drive the external CRT display can be shut off. In the environment of FIG. 4, functional devices including DACs 80, 82 and 84, PSRAM 76, palette update control 78 and MISR 92 are shut off. In addition, the analog circuits in DACs 80, 82 and 84 are similarly shut off. It will be appreciated that circuits similar to those shown in FIGS. 5 and 6 can be used to implement the fourth embodiment.

Many portable computer systems have the ability to enter a suspended state during which no processing occurs, as is known to those skilled in the art.
During the suspend state, the LCD or other external CRT display is blank.

In a fifth embodiment of the present invention, a SUSPEND signal is generated indicating that it is about to enter a suspended state. Therefore, the SUSPEND signal is monitored,
In response, all functional units in the video subsystem are turned off. Upon input to the computer, power to functional units within the video subsystem is restored. As in the previous implementation method, the functional device is turned off by turning off the clock, and is turned on by turning on the clock.

Although not typically part of the SPDAC chip, the portable computer system's CRT controller (CRTC) is part of the video subsystem 24 commonly found in the controller 28, and Benefit from power management. The SPDAC chip is the clock signal source to the CRTC functional device because the CRTC clock has a time interval that is typically a multiple of the pixel clock interval. When the portable computer enters the suspend state, there is no reason to activate any functional devices associated with the video display. Thus, SPDAC during the suspend state
The clock signal source can be turned off and the CRTC can be shut off.

FIG. 5 shows an SPDA that can be used, for example, for power management in accordance with the first and third embodiments of the present invention.
It is a block diagram display of C and a logic circuit. According to a first implementation, power savings are possible if the DAC is turned off synchronously with the applied timing of the display (ie, during blanking). According to a third implementation, all but one DAC is shut down in response to the monochrome display used in the system, and power savings is achieved.

Each of the DACs 102, 104 and 106 has a high speed digital front end that decodes the applied digital pixel data from the pixel data pipeline 134 and controls the DAC analog output. Some SPs
In a DAC chip, the DAC also has a number of input shift registers (MISRs) associated with it. Typically, MISR is used for functional fault diagnosis and operates at high speed. DACs and MISRs operate at high pixel frequencies to achieve high speeds. As mentioned above, digital CMOS power consumption is proportional to operating frequency. Thus, shutting off the DAC and MISR digital circuits during blanking provides a proportional amount of digital power savings as those circuits account for 25% to 40% of the total display time. DAC 102, 1
By cutting off the pixel clock signal on line 108, to 04 and 106, digital blocking is achieved.

In order to optimize the overall power savings during blanking, digital DAC shutdown (ie, functional unit shutdown) may be implemented in conjunction with analog DAC shutdown according to the first implementation method. preferable. Logic sub circuit 110
Is one way to achieve digital DAC blocking.

A DAC analog disable (DAD) signal on line 112 disables DAC constant current references 114, 116 and 118. An apparatus for disabling the use of the constant current reference is described below. When the DAD signal is present, the pixel clock signal to the digital portion of the DAC must be synchronized to achieve the digital DAC block in synchronization with the analog DAC block. An inverse MONO signal is provided on line 120 to the logical AND device 122 to indicate that there is a color display in the system. The inverted output signal of the logical OR device 124 is given to the logical AND device 122. Furthermore, a pixel clock signal is provided to logical AND device 122 on line 126. The logical AND device 128 has as its inputs the pixel clock signal on line 108 and the logical OR device 12
4 with the reverse output. Blanking pipeline delay circuit 1
30 simply delays the blanking signal on line 132 to synchronize with the pixel data pipeline output signal 134 on line 136 to DACs 102, 104 and 106 on line 136. The delayed blanking signal is applied to the logical OR device 124 on line 138.
To the logical AND device 140 and the DACs 102, 104 and 106.

Logical AND device 140 also has as input a non-delayed blanking signal on line 142. The inverted output signal of the logical AND device 140 is
Will be sent to The logical AND device 144 also has a pixel clock signal on line 108 as an input signal. The output signal of the logical AND device 144 is
The upper pixel data pipeline 134 serves as a clock for the functional units. DAC 102, 10
4 and 106 are output on lines 14 and 106, respectively.
8, 150 and 152 to the display 47.

The digital portion of DAC 104 is line 1
There is a pixel clock signal line on line 08 and DAC1 only when both the DAD-free signal (reference current on) and the non-delayed BLANK signal (while blanking is disabled) are recognized.
The digital portion of 04 operates (ie, a clock signal is applied to it). This is the same for the DACs 102 and 106, except that in this case,
For the digital part to work (ie line 15
4 (to receive the clock signal on 4), there must be an inverse MONO signal. In this way, the DAC 10
Only 2 and 106 work for color displays. After the DAC converts the last active pixel of the display operation, the clocks to DACs 102, 104 and 106 are turned off to save digital power and are turned on again when the first active pixel of the next display operation is returned. You.

The digital power savings afforded by DAC and MISR cutoff (if equipped) during blanking during blanking can be extended to include all functional units of SPDAC. However, SPDAC functional devices other than DACs will encounter blanking at different time intervals as they physically extend beyond the pixel data pipeline 134. Although it is possible to perform the blanking cutoff step-by-step beyond the pixel data pipeline, it adds more complex circuitry than a less complex, unstaged blanking cutoff The power that can be saved by this is relatively small.

The last active pixel in the display operation is the pixel data
After being passed to DACs 102, 104 and 106 through pipeline 134, the pixel data on line 146
The clock for pipeline 134 is turned off.
The blanking signal is delayed through blanking pipeline 130 to coincide with the last active pixel timing. When the first active pixel of the next display operation enters the pixel data pipeline 134 on line 155, ie, coincides with the end of the blanking signal 132, the clock for the pixel data pipeline is turned on. You.

The DAC analog circuit of SPDAC has a constant reference current that maintains the DAC so that it can respond quickly in the active state. SPDACs often have the ability to interrupt their DAC constant current reference. With this capability, significant savings in analog power are achieved.

DA according to the first and third embodiments of the present invention
C analog power management achieves power savings by controlling the DAC analog reference current. In a first implementation, the reference current is interrupted during blanking, and in a third implementation, when a monochrome display is connected to the system, all but one reference current are interrupted. Is done. A typical display has a function known as a blanking operation. During this blanking, a zero output equivalent to the output signal when the reference current is closed is provided to the DAC. Statistically eliminates blanking from 25% of display time to 4
It is known to account for between 0%. If the constant current reference to the DAC is turned off during all blanking, a corresponding amount of DAC analog power can be saved. It will be appreciated that the constant current reference can be interrupted by either a positive or negative shutoff signal, depending on the design.

However, as is known to those skilled in the art, depending on the order of some pixel operations, the DAC takes time to recover from a large change in the applied reference current. Considering the required recovery time, after the last active pixel in the display operation has left the DAC, the DAC reference current is turned off and the first active pixel in the next display operation is the pixel data to compensate for the DAC recovery time. Can be turned on when entering the pipeline.

FIG. 6 shows an S which can be used as an example for power management according to the first and third embodiments of the present invention.
FIG. 2 is a block diagram display of a PDAC and a logic circuit. FIG.
Is compared with the SPDAC 35 of FIG. 3, the pixel data pipeline (PDAP) 134
2, TATR 44, multiplexer 46, DIRCOL
48, a PSRAM 50, a SPRLO 52, a DAC input select 54, and a multiplexer 56. In short, the PDAP 134 is (the DACs 102 and 104 in FIG. 5).
And SPDAC (shown as and 106). Each DAC has a constant reference current (114, 116 and 118, respectively) associated with it. Blanking pipeline delay circuit (BLIP) 13
0 is line 1 to synchronize with DPAP134 output signal
It simply delays the blanking signal on 32.

The logical OR device 158 receives as its input
It has a blanking signal on line 132 and a delayed blanking signal on line 160 from blanking pipeline delay circuit 130. The output signal of logical AND device 158 is sent to logical OR device 162 on line 164. Logical O
The other input to R device 162 is D on line 112
AD signal. As described above, the DAD signal is
Indicates that the analog circuits 102, 104, 106 should be disabled. The output signal of the logical OR device 162 is sent to a constant current reference 116 on line 166,
Acts as a cutoff signal to the constant current reference 116. Logical O
The output signal of R unit 162 is also sent to logical OR unit 168 on line 170. MON indicating that a monochrome screen is present on the computer system
The O signal also causes the logical OR device 168 on line 172 to
Will be sent to The output signal of logic OR device 168 is sent to constant current references 114 and 118 on line 174 and acts as its shut off signal. Thus, DAD
When a signal is present and when a monochrome display is connected to the computer system, the constant current references 114 and 118 are shut off during blanking.
It will be appreciated that the DAD and MONO signals can be generated as output signals of registers that are loaded with values of 1 or 0, for example, by the controller 28 or CPU power management software.

A method and apparatus for power management of both analog and digital circuits of a video subsystem has been described above. Power management is possible according to the invention in both portable and non-portable types of computers, as in display devices. In order to achieve maximum power savings, it is preferred that all of the power management implementation methods described herein be implemented in the best possible combination.

[0052]

According to the present invention, the power consumption of the portable computer can be significantly reduced, and the power consumption or battery cost can be reduced, and the number of times of battery replacement can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a workstation.

FIG. 2 is a block diagram of the video subsystem of FIG.

FIG. 3 is a block diagram of a commercially available parallel-to-serial converter palette-to-digital-to-analog converter that serves to illustrate a second embodiment of the present invention.

FIG. 4 is a general block diagram of a parallel-to-serial conversion circuit palette-to-digital-to-analog converter and a liquid crystal display controller useful for explaining a fourth embodiment of the invention.

FIG. 5 is a partial block diagram of a video subsystem with exemplary circuitry for performing digital circuit breaks during blanking if a monochrome display is used.

FIG. 6 is a partial block diagram of a video subsystem with exemplary circuitry for performing DAC analog circuit breaks during blanking if a monochrome display is used.

[Explanation of symbols]

10 Workstation 24 Video Subsystem 26, 100, 147 Display 28 Graphics Controller 30 VRAM 34, 70 Parallel-to-Serial Converter Palette Digidal Analog Converter (SPDAC) 80, 82, 84, 102, 104, 106 Digital・ Analog converter (DAC) 42 Parallel / serial converter 44 Text / attribute logic circuit 60 Mode control 48 Direct color logic circuit (Direct) 50 Palette static RAM 52 Sprite logic circuit 66 Clock control 58 DAC macro 54 DAC input select 98 Liquid crystal display (LCD) 96 LCD controller 78 Palette update circuit 92 MISR 134 Pixel data pipeline 130 Blanking pipeline delay 120 MONO signal 132 blanking signal 108 pixel clock 146 pixel data pipeline clock 112 DAC analog disable signal 172 MONO signal

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kathryn Elizabeth Ricardo Hunts Romji Porters Bridge Street, UK 20 (72) Inventor Richard Joseph Grup, Milton Stewart Lane, Vermont, United States 21 (56) References JP JP-A-3-84585 (JP, A) JP-A-3-174585 (JP, A) JP-A-2-105568 (JP, A) JP-A-1-100588 (JP, A) A) Hikaru Hira 3-12296 (JP, U) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 1/26-1/32

Claims (7)

(57) [Claims] A video subsystem having a plurality of sub-circuits and a display, wherein a blanking signal is generated by the video subsystem during a blanking operation in which pixel data is not displayed; A method for dynamically saving power consumption of a computer system, wherein the erase signal includes a start signal and an end signal, wherein the step of monitoring the blanking start signal includes the steps of: Turning off power to each of the plurality of sub-circuits not used during the blanking in response to a start signal; monitoring a blanking end signal; Restoring power to each of said plurality of sub-circuits not used during said blanking in response to dynamically reducing power consumption of a computer system comprising: Method. 2. The power supply of claim 1, wherein said plurality of sub-circuits include a functional device comprising a digital circuit operating in accordance with a clock signal and a digital-to-analog converter having a constant current reference associated with said sub-circuits. 2. The method of claim 1, wherein the steps include preventing the clock signal from reaching the digital circuit and setting the constant current reference to off.
The described power saving method. 3. A video display system comprising a color display or a monochrome display, wherein the video subsystem includes a plurality of digital-to-analog converters (DACs), wherein each of the plurality of DACs produces an analog signal representing a particular color. Computer characterized by being generated
A method for reducing power consumption in a video subsystem in a system, the method comprising: generating a display signal indicating whether a color display or a monochrome display is connected to the computer system; Monitoring the display signal indicating that a display is connected to the computer system; and responding to the display signal indicating that a monochrome display is connected to the computer system; Turning off all but one of the DACs; and a method for conserving power in a video subsystem in the computer system comprising: 4. The video subsystem includes a plurality of sub-devices, each of which performs one or more unnecessary functions during one or more blanking operations. A blanking signal having one or more blanking operations, wherein a blanking signal is generated during the blanking operation, wherein the blanking signal has a start and end signal of the blanking operation. Computer with subsystem and display
An apparatus for dynamically reducing power consumption in a system, comprising: means for monitoring a blanking start signal; and responsive to the blanking start signal, power to each of the plurality of sub-circuits. Means for turning off, means for monitoring the blanking end signal, and means for restoring power to each of the plurality of sub-circuits in response to the blanking end signal. A device that dynamically reduces power consumption in computer systems. 5. A video display system comprising a color or monochrome display, wherein the video subsystem includes a plurality of digital-to-analog converters (DACs), wherein each of the plurality of DACs produces an analog signal representing a particular color. Computer characterized by being generated
An apparatus for reducing power consumption of a video subsystem in a system, comprising: means for generating a display signal indicating whether a color display or a monochrome display is connected to the computer system; Means for monitoring the display signal indicating that a display is connected to the computer system; and responding to the display signal indicating that a monochrome display is connected to the computer system, Means for turning off all but one of the DACs; and an apparatus for reducing power consumption of a video subsystem in a computer system comprising: 6. Pixel data wherein pixel data is provided for an output signal to a display and each of a plurality of DACs.
A pipeline is included in the video subsystem, each of the plurality of DACs includes a digital circuit operative in accordance with a pixel clock signal, and an analog circuit has a constant current reference associated therewith for a color display. An analog signal representing a specific color is a plurality of D signals.
A blanking pipeline produced by each of the ACs and wherein the blanking signal is delayed to be synchronized with the output signal of the pixel data pipeline and is included in the subsystem; Is the plurality of D
An apparatus for dynamically reducing power consumption in a video subsystem in a computer system, the output signal to each of the ACs, the apparatus including an inverse output signal, wherein the first input signal is Multiple D
A logic O having a DAC analog disable signal (DAD) signal for disabling the analog circuit in each of the ACs, and the delayed blanking signal delayed as a second input signal;
An R device, the pixel clock signal as a first input signal, the inverse output signal from the logical OR device as a second input signal, and both the DAD signal and the delayed blanking signal are present. A logic AND device having an output signal to each of the plurality of DACs for sending a clock signal to the digital circuit if not, and a device for dynamically reducing power consumption in a video subsystem in a computer system. 7. Pixel data wherein pixel data is prepared for an output signal to a display and each of a plurality of DACs.
A pipeline is included in the video subsystem, each of the plurality of DACs includes an analog circuit having a constant current reference associated therewith, and an analog signal representing a particular color for a color display is provided by the plurality of DACs.
C, wherein the blanking pipeline is included in the subsystem and the blanking signal is delayed so that the blanking signal is synchronized with the output signal of the pixel data pipeline. But the multiple DAs
C. An apparatus for dynamically reducing power consumption in a video subsystem in a computer system, the output signal to each of the C., including an output signal, wherein the input signal is an input signal. A logical AND device having a line erase signal and the delayed blanking signal as a second input; the output signal of the logical AND device as a first input signal; and the plurality of DACs as a second input signal. A signal for disabling each of the analog circuits, and an output signal to each of the constant current references associated with each of the plurality of DACs for turning off each of the current references during blanking. And a device for dynamically reducing power consumption in a video subsystem in a computer system comprising: