JP2983556B2 - Background level detection circuit of document reading device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a method and a circuit for detecting the background level of a document by a line sensor (one-dimensional image sensor) in a document reading apparatus of OA equipment such as a facsimile. It is.

(Prior Art) A peak hold circuit is used to read the background level of a document by a document reading device such as a facsimile. In the case of the halftone mode, the white level of the roller portion, the white level of the thick plate, or the white level at the beginning of the document is detected as the background level for each document and stored in the peak hold circuit.

In the case of the binary mode, there is also provided a peak hold circuit provided with a discharge circuit for causing a constant time constant to discharge, in consideration of a case where the background changes in the middle of a document. The discharge circuit changes the background level stored in the storage capacitor.

(Problem to be Solved by the Invention) In the method of storing the background level only in the storage capacitor of the peak hold circuit, the background level cannot be held for a long time due to a leak current due to a parasitic resistance of the semiconductor element. Therefore, for example, during transmission by facsimile, the line may be stopped for a long time (minutes) due to the congestion of the line. However, when the transmission is restarted, the background level stored in the storage capacitor changes due to a leak. As a result, the original cannot be read correctly.

In addition, especially in the case of the halftone mode, for example, when transmitting a photograph, when only the black level is concentrated, when the transmission is restarted,
Even if the background level is detected again, the correct background level cannot be detected.

An object of the present invention is to provide a background level detection circuit capable of securing a background level even when a document such as a photograph or the like in which black levels may be concentrated for a long time is transmitted or when transmission is stopped. It is intended for.

(Means for Solving the Problems) In the present invention, the output of the peak hold circuit is detected by a so-called tracking A / D converter, and the photograph transmission is stopped when the black level is continuous or during the original transmission. In some cases,
The background level is generated by the D / A converter built in the tracking A / D converter.

The background level detection circuit of the present invention has a discharge circuit, a peak hold circuit that can continuously follow a change in the background level of a document, and a D / A conversion that generates a predetermined divided voltage from a preset reference voltage. A window comparator for comparing the magnitude of the output of the peak hold circuit with the output of the D / A converter; and an up / down converter for digitally setting the D / A converter in accordance with the output of the window converter.
A down-counter, a selection switch circuit for selecting the peak hold circuit output in the case of the binary mode, and selecting the D / A converter output in the case of the halftone mode, and outputting the output to the subsequent circuit as a background level; The output of the up / down counter is detected when the output of the up / down counter is at the maximum value and the up / down counter is held even when the up signal is input. In the case of the halftone mode, the output of the up / down counter is other than the maximum value. And a control circuit for enabling the up / down counter to take only the up and hold states.

The window converter determines whether the level to follow is higher or lower than the current level, and the up / down counter and the D / A converter are combined,
Follows the output level of the analog peak hold circuit. The output level of the analog peak hold circuit drops in the area where there is no white level due to the discharge circuit.Even if there is some white level, the level drops even when the transmission stops for a time longer than the discharge time constant. Wake up.
However, in the present invention, in the case of halftone, up / down
The counter disables the down signal and follows the rise of the analog peak hold circuit output, and does not follow the fall, so even if an area without any white level continues or transmission stops, the The key can be read correctly.

FIG. 1 shows a background level detection circuit according to an embodiment.

30 is a peak hold circuit having a discharge circuit and capable of continuously following changes in the background level of the document, 31 is a D / A converter that generates a predetermined divided voltage from a preset reference voltage, 33
Is a window converter for comparing the output of the peak hold circuit 30 with the output of the D / A converter 31, and 32 is an up / down converter for digitally setting the D / A converter 31 in accordance with the output of the window converter 33. It is a counter.
The up / down counter 32 always receives a clock (CLK), and is controlled by an up signal, a down signal, and a halftone signal (HALF) from the window comparator 33. 34 is the output of the peak hold circuit 30 and D /
A selection switch circuit that selects one of the outputs of the A converter 31 and outputs it as a background level to a subsequent circuit.

 FIG. 2 shows a specific example of the peak hold circuit 30.

A sampling switch 35 connects the input terminal A to the non-inverting input terminal of the comparator 36. comparator
The output terminal 36 is connected to a non-inverting input terminal of a buffer amplifier 38 via a rectifier diode 37. A storage capacitor 40 is connected to the non-inverting input terminal of the buffer amplifier 38, and a series circuit of a discharge resistor 39 and a discharge switch 41 and a reset switch 42 are connected in parallel with the storage capacitor 40. The output terminal B of the buffer amplifier 38 is a buffer amplifier
It is connected back to the inverting input terminals of the comparator 38 and the comparator 36.

Table 1 shows the relationship between each switch and the operation mode of the peak hold circuit shown in FIG.

FIG. 3 shows a specific example of the window comparator 33.

The input terminal C is a terminal for inputting an output (Vdac) from the D / A converter 31. The constant current source 43, the resistors 44 and 45, and the constant current source 4
It is connected to the connection point between the resistors 44 and 45 of the series circuit of No. 6.
The connection point between the constant current source 43 and the resistor 44 is connected to the inverting input terminal of the comparator 47, and the connection point between the resistor 45 and the constant current source 46 is connected to the inverting input terminal of the comparator 48. The output Vph of the peak hold circuit 30 is input to the non-inverting input terminals of the comparators 47 and 48 via the input terminal D. The output terminals of the comparators 47 and 48 are connected to an AND gate 49, and the output E of the AND gate 49 becomes a signal for causing the up / down counter 32 to perform an up operation. The output terminals of the comparators 47 and 48 are also connected to the NOR gate 50, and the output F of the NOR gate 50 becomes a signal for causing the up / down counter 32 to perform the down operation.

In the window comparator shown in FIG. 3, if the currents of the constant current sources 43 and 46 are I and the resistances of the resistors 44 and 45 are R, the high-level threshold level of this window comparator is Vdac + IR. The lower threshold level is Vdac-IR. comparator
47 and 48 are the peak hold circuit output V input from terminal D
ph is compared with each threshold level, and an up signal or a down signal is output from terminals E and F via gates 49 and 50.

Table 2 shows the outputs of the comparators 47 and 48, the signal levels of the terminals E and F, and the operation of the up / down counter 32.

Next, the operation of the embodiment will be described with reference to FIGS. 1, 2, 3, and 4. FIG.

When a document is transmitted by facsimile or the like, in the binary mode, the reset switch 42 is turned off from the reset state, the sampling switch 35 and the discharge switch 41 are turned on, and reading of the document is started. The roller portion, the thick plate portion, or the beginning of the document is read, the background level is detected, stored in the storage capacitor 40, and discharged through the discharge resistor 39. As a result, it continuously follows changes in the background level.

In the selection switch circuit 34, the peak hold circuit 30
Is turned on, and the D / A converter 31 is turned off.

In Figure 4, now, the output level of the D / A converter 31 and J, there a high level side threshold level G, and the low-level side threshold level and K, the output Vph for example Vph ₁ of the peak hold circuit 30 For example, from Table 2, the window comparator 33
A signal for operating the down counter 32 to be up is output, and the D / A converter 31 is set so that Vph ₁ falls between the levels G and K.
Output level J is increased. Conversely, if the output Vph of the peak hold circuit 30 is, for example, at Vph ₂ , the window comparator 33 increases /
A signal for causing the down counter 32 to perform a down operation is output, and the D / A converter 31 is operated so that Vph ₂ falls between levels G and K.
Output level J is lowered. Peak hold circuit
If the output Vph of 30 is between levels G and K, such as Vph ₀ , the signal from up / down counter 32 will be in a state of neither up nor down.

In the case of the halftone mode, for example, in the case of photo transmission, a halftone signal (HALF) is generated. As a result, the selection switch circuit 34 is switched, and the peak hold circuit
The 30 side turns off, the D / A converter 31 side turns on, and the D / A
The output level of converter 31 is output as the background level.

If the portion for detecting the background level has a stain or the like, a higher white level is detected as the reading of the document actually proceeds. In such a case, the up / down counter needs to count up. Otherwise, the whole manuscript will be whitish.

On the other hand, when shading correction is performed, correction data is created based on the white level of the rollers, the white level of the thick plate, or the white level at the beginning of the document, and the white level when an actual document is read is corrected. If the data is created in a dirty portion, the maximum output level of the D / A converter 31 may be exceeded.

In preparation for such an abnormality, the background level detection circuit detects the output value of the up / down counter 32 to prevent overflow of the up / down counter 32, and the output value reaches the maximum value. Sets the up / down counter 32 to the hold state even when the up signal is input, and sets only the up and hold states when the digital value is other than the maximum value in the halftone mode.
The setting method of the D / A converter 31 that controls the up / down counter 32 is effective.

FIG. 5 shows an example of a control circuit of such an up / down counter 32.

In FIG. 5, a signal CP1 corresponding to the output (high-side output) of the comparator 47 of the window comparator shown in FIG.
Signal CP corresponding to the output (low side output) of comparator 48
2 are input to the NOR gate 51 via the respective inverters, and the output of the NOR gate 51 is input to the D-type flip-flop 52. The output of the flip-flop 52 is input to the up / down input terminal of the up / down counter 32. Here, an 8-bit output up / down counter is shown as an example of the up / down counter 32.

In order to detect the maximum value of the output of the up / down counter 32, the output of the up / down counter 32 has two NAs.
Input to ND gates 53 and 54, output of NAND gates 53 and 54 is NO
Input to R gate 55, output of NOR gate 55 is NAND gate
It is input to one of 56 input terminals. CP2 is input to the other input terminal of the NAND gate 56.

HALF is a signal indicating the halftone mode or the binary mode, and is input to the NOR gate 57 together with CP2. The output of the NOR gate 57 is input to one input terminal of the NAND gate 58 via the inverter, and CP1 is input to the other input terminal of the NAND gate 58. NAND gate 56 and NAND gate 5
The output of 8 is input to a NAND gate 59, and the output of the NAND gate 59 is input to a D-type flip-flop 60. The output of the flip-flop 60 is input to the carry input terminal of the up / down counter 32. When the input signal of the carry input terminal is "0", it goes up / down,
When it is "1", it is in the hold state.

Flip-flops 52 and 60 and up / down counter 3
2 is supplied with a clock signal.

 The operation of the control circuit of FIG. 5 is shown in Table 3.

In Table 3, if HALF = 1, halftone mode, HALF
If = 0, the mode is the binary mode. dac is up / down
This indicates whether or not the output of the counter 32 is the maximum value (FF). If dac = 1, the state is FF, that is, the maximum value. The next operation mode of the up / down counter 32 will be set as MODE.

It can be seen from Table 3 that in the case of the halftone mode, there is only an up or hold state.

(Effect of the Invention) According to the present invention, a peak hold circuit having a discharge circuit and capable of continuously following a change in the background level of a document, and a D / A converter for generating a predetermined divided voltage from a preset reference voltage , A window comparator for comparing the magnitude of the output of the peak hold circuit with the output of the D / A converter, and an up / down counter for digitally setting the D / A converter in accordance with the output of the window converter And in the case of binary mode, the peak hold circuit output,
In the case of halftone mode, select the D / A converter output,
A selection switch circuit for outputting a background level to a subsequent circuit; and detecting the output of the up / down counter, setting the up / down counter to a hold state even when an up signal is input when the output is a maximum value, In the case of the mode, a control circuit is provided to enable the up / down counter to take only the up and hold states when the output of the up / down counter is other than the maximum value. For example, even when a document having a possibility of concentration of black level is transmitted for a long time, the document can be read at the correct background level.

In the case of the binary mode, the output of the analog type peak hold circuit which can follow the change of the background is more suitable, and the background level detection circuit of the present invention which can switch between the analog type and the digital type is an effective means.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment, FIG. 2 is a circuit diagram showing a specific example of a peak hold circuit in FIG.
5 is a circuit diagram showing a specific example of the window comparator in FIG. 1, FIG. 4 is a diagram showing the operation of the embodiment, and FIG.
FIG. 10 is a circuit diagram showing an up / down counter control circuit according to another embodiment. 30 …… Peak hold circuit, 31 …… D / A converter, 32 ……
Up / down counter, 33 ... window comparator, 34 ... selection switch circuit.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60 G06T 1/00

Claims (1)

(57) [Claims] 1. A peak hold circuit having a discharge circuit capable of continuously following a change in the background level of a document, and generating a predetermined divided voltage from a preset reference voltage.
A D / A converter, a window converter for comparing the magnitude of the output of the peak hold circuit with the output of the D / A converter, and an up / down converter for digitally setting the D / A converter according to the output of the window converter. And a selection switch circuit for selecting the output of the D / A converter in the case of the binary mode and the output of the D / A converter in the case of the halftone mode, and outputting to the subsequent circuit as the background level. The output of the up / down counter is detected, and when the output is the maximum value, the up / down counter is held even when the up signal is input. In the case of the halftone mode, the output of the up / down counter is the maximum value. A control circuit for enabling the up / down counter to take only up and hold states at other times. circuit.