JP2982509B2 - Image reduction processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reduction processing method, and more particularly to an image reduction processing method for performing image reduction processing in a facsimile apparatus.

[0002]

2. Description of the Related Art In a conventional image reduction method, one pixel row to be thinned out is periodically determined according to a reduction ratio, and a pixel row to be thinned out is simply thinned out irrespective of pixel information of the pixel row or surrounding pixel information. Had been reduced.

[0003]

In the above-described conventional image reduction processing method, one thinning-out control pixel row is periodically determined according to a reduction magnification, and the pixel row or its surrounding pixel information is completely independent. Since the reduction process is performed by simply thinning out the thinning-out control pixel columns, there is a disadvantage that image information of the thinning-out target pixel columns is lost, and individual image information cannot be reproduced for surrounding pixels such as ruled lines and thin lines. Was. Therefore, there is a problem in that the ruled line is broken, blurred, or broken by performing the reduction process.

[0004]

According to the image reduction processing method of the present invention, two lines to be thinned out of image data obtained by binarizing image information of white information and black information are set as thinned pixel columns, and One of the pixel rows is thinned out so that the pixels in the pixel row are not isolated from the surrounding image information.

Means for storing the input image data in a plurality of line memories to generate and output the thinned-out pixel rows and the reference pixel rows; and outputting a predetermined first specific pattern to the pixels of the line memory. A means for detecting and selecting one of the thinned-out pixel rows from the row, a means for outputting four pixels in the main scanning direction of the selected thinned-out pixel row in parallel, and a second preset Means for detecting a specific pattern from the outputs of the four pixels and selecting and outputting thinned pixels.

[0006]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

In this embodiment, image data Din obtained by binarizing image information of white information and black information is stored in a plurality of line memories L.
A line memory 11 that is stored in M1 to M3 and is generated and output as thinned pixel rows b and c and reference pixel rows a and d, and a first specific pattern set in advance is detected from the pixel rows of the line memory 11. A first pattern matching circuit 12 and a first selector circuit 14 for selecting and outputting one of the thinned-out pixel rows b or c, and four pixels m, 4 in the main scanning direction of the selected thinned-out pixel row b or c. A delay circuit 21 that outputs n, p, and q in parallel, and a preset second specific pattern are detected from outputs of m, n, p, and q for four pixels, and thinned pixels n or p are selected and output. The circuit includes a second pattern matching circuit 22 and a second selector circuit 24.

Next, the operation of this embodiment will be described. Generally, image information used for facsimile communication or the like represents white information and black information by electric signals 0 and 1, and an image on a two-dimensional plane is horizontally (main scanning direction) and sequentially vertical (sub scanning direction). And scan and transmit. This input image data Din is stored in a line memory (LM1, LM2, LM3).
11 to generate and output pixel lines a to d for four lines adjacent in the sub-scanning direction.

Here, if a is an i-th pixel column, b is the i-1st line, c is the i-2th line, and d is i-3.
This is the pixel column of the line. Here, b and c are input to the first selector circuit (DS1) 14 as a thinning-out control pixel row, and a, b, c, and d are input to the first pattern matching circuit (PM1) 12, and a specific pattern is input. In the case of (set in advance), the pixel selection signal h is instructed to the selector circuit 14 to switch which pixel of the thinned-out pixel row b or c is selected.

The vertical reduction circuit (VRC) 13 converts the enable signal (ENB) e for each line from the enable signal (ENB) e for each line to the pixel switching signal g only in the section of the line before the thinned line by the reduction magnification.
Is output to the (PM) 12, and in the (PM 1) 12, the pixel column b is fixed so as to be selected by the pixel selection signal in other than this section.

In (VRC) 13, a new enable signal u is output by masking the enable signal corresponding to the thinned line. The pixel row m obtained from the above result (DS1) 14 normally outputs the pixel row b, and thins out only the line before the thinning line from the pixel rows b and c in the sub-scanning direction selected in pixel units. The reduced pixel is output.

Similarly, the pixel row m output from the (DS1) 14 is input to a pixel delay circuit (D1, D2, D3) 21 to generate four pixels m, n, p, q in the main scanning direction. Output. n, p are input to the second selector circuit (DS2) 24 as thinning target pixels, and the second
The pixel selection signal s is changed to (DS2) when the pattern matching circuit (PM2) 22 has a specific pattern (preset).
2) Output to 24 to switch between n and p pixels to be selected.

Here, the pixel transfer clock (CLK) f is output by a horizontal reduction circuit (HRC) 23 by masking the clock of the thinned-out pixel according to the reduction magnification and outputting a pixel transfer clock x, and only in the section of the pixel preceding the thinned-out pixel. The pixel switching signal r is instructed to the (PM2) 22 and the (PM2) 22 is fixed so that the pixel n is selected by the pixel line selection signal s except for this section. The pixel data output Dout (= t) obtained from the above result (DS2) 24 normally outputs the pixel n, and outputs only the pixel selected from the pixels n and p before the thinned pixel. (Thinning processing in the main scanning direction) Next, the pattern matching circuits (PM1, PM2) 13,
23 and the operation will be described with reference to FIG. PM1,
If the pixels input to PM2 are the i-th to i-3rd pixels, there are 16 combinations. Here, the pixels to be decimated are the pixels of i-1 and i-2, and either one of them is decimated and is lost.

At this time, if the logical value of the pixel to be thinned and one of its adjacent pixels have the same logical value, it is determined that the pixel can be thinned. If the logical values of both the adjacent pixels are different, it is determined that the pixel cannot be thinned. By doing so, the pixels that can be thinned out become shaded portions.

Since the logical values of the sixth and eleventh pixels change for each pixel, a logical lack of a pixel occurs regardless of which one is thinned. In other cases, even if one of the thinning-out possible pixels is thinned out, the logical information of the pixel remains and the resolution can be secured. Therefore, except for a very rare pixel pattern in which the logic changes for each pixel, by switching the thinning-out possible pixels according to the pixel pattern, it is possible to reduce the size without causing a thin line such as a ruled line or a loss of characters.

In the case where either the pixel i-1 or the pixel i-2 to be decimated may be decimated, in order to reduce the jitter of discontinuity of the pixel row caused by switching the decimated pixel, the previous screen is decimated as much as possible. It is desirable to thin out the same pixel column as the pixels.

[0017]

As described above, according to the present invention, the thinning-out pixels are selectively switched from the two thinning-out control pixel columns so that the logical information of the pixels is not lost as much as possible from the pixel pattern around the thinning-out pixels. As a result, there is an effect that loss of thin lines such as ruled lines and crushing of fine characters can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing a pixel pattern for explaining the operation of the embodiment.

[Explanation of symbols]

 11 LM1-3 (line memory) 12 PM1 (first pattern matching circuit) 13 VRC (vertical reduction circuit) 14 DS1 (first selector circuit) 21 D1-D3 (pixel delay circuit) 22 PM2 (second Pattern matching circuit) 23 HRC (horizontal reduction circuit) 24 DS2 (second selector circuit) a input pixel column (i line) b input pixel column (i-1 line) c input pixel column (i-2 line) d Input pixel column (i-3 line) e Input enable signal f Input pixel transfer clock g Pixel switching signal (sub-scanning direction) h Pixel line selection signal (sub-scanning direction) m Sub-scanning reduced pixel column (input i-th pixel) n Input pixel (i-1st pixel) p Input pixel (i-2nd pixel) q Input pixel (i-3rd pixel) r Pixel switching signal (main scanning direction) s Pixel selection signal ( (Main scanning direction) t Reduced pixel output u Output enable signal x Output pixel transfer clock

Claims (1)

(57) [Claims] 1. A thinning-out pixel line for two lines to be thinned out of image data in which image information of white information and black information are binarized, and pixels of the thinned-out pixel line are arranged with respect to the surrounding image information. This is a reduction processing of an image in which one of the pixel columns is thinned out so as not to become an isolated pixel, and a plurality of the input image data are
The thinned pixel column and the reference pixel stored in the line memory
Means for generating and outputting as a sequence, and a first preset
When a specific pattern is detected from the pixel row of the line memory,
Means for selecting and outputting one of the thinned pixel columns,
4 pixels in the main scanning direction of the thinned pixel column are output in parallel.
Means for performing the second specific pattern set in advance
A method of detecting from the output of four pixels and selecting and outputting a thinned pixel.
Image reduction processing method characterized by having a stage.