JP2979849B2 - Diversity receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diversity receiver of a post-detection selective diversity reception system for performing optimum reception by switching a demodulation output.

[0002]

2. Description of the Related Art Land mobile communication systems such as automobile telephones are currently provided with an analog FM system. However, introduction of a digital system has recently been considered in order to increase capacity and improve secrecy. For example, transmission speed 42k
A car telephone system with digital modulation of bps is planned. In such mobile communication, it is important to ensure communication quality. For example, when an automobile equipped with a mobile communication device travels in an urban area,
The propagation path of the radio wave becomes a multiplex propagation path due to the influence of a building or the like, the received signal is subjected to fading, and the communication quality is significantly deteriorated.

In the conventional analog FM system, a diversity reception system after detection has been adopted as a method for obtaining good communication quality.

Here, the diversity receiving system is a receiving system in which a plurality of receiving antennas are provided, and a signal received by any one of the receiving antennas is selected and output. This selection is made, for example, according to the level of the reception level (see Japanese Patent Application Laid-Open No. 61-30137). That is, since signals are generally received by a plurality of receiving antennas via different multiplex propagation paths, the receiving level differs for each receiving antenna. Since it can be considered that the higher the reception level, the better the signal related to transmission can be reproduced, the reception signal related to the reception antenna with the highest reception level is adopted.
The post-detection selective diversity reception system is a system in which a plurality of reception antennas and demodulators are provided and a demodulation output is selectively output. This method has better communication quality because output switching at high frequency is not performed, and C
/ N is reduced, and communication quality is improved.

However, in the case of communication using digital modulation, if the delay time of the multiplex wave cannot be ignored with respect to the 1-bit length T of the transmission information, the bit error rate increases.

As shown in FIG. 16, there is a significant difference in the bit error rate between the case where the diversity reception method is not used and the case where the transmission speed is large (T = small, τ / T = large). The effect of the improvement is reduced.

To solve such a problem, a receiving system having a smaller delay time τ may be selected. For this reason, the present applicant has proposed a diversity receiver having the following configuration (Japanese Patent Application No. Hei 2-9973).
No. 5). FIG. 17 shows the configuration of the diversity receiver according to the prior proposal.

FIG. 1 shows n (n: integer) reception systems 10-i (i = 1, 2,..., N).
Each receiving system 10-i has a receiving antenna 12-
i, a down-converter 14-i, a demodulation unit 16-i, and a code discrimination unit 18-i are sequentially connected. The code discriminating unit 18-i is connected to the changeover switch 20.

That is, for example, 1000 MH transmitted from a transmitter (base station) through different multiplex propagation paths.
Radio waves of about z are received by the receiving antennas 12-i, respectively, and are demodulated by the demodulator 16-i via the down converter 14-i.
i. In demodulation section 16-i, the received signal is demodulated and output to code discrimination section 18-i.
The code determination unit 18-i determines a code related to transmission based on the demodulated output of the demodulation unit 16-i, and outputs a code (string) obtained as a result of the determination.

The output of the code discriminating section 18-i is input to the changeover switch 20, and one of them is selected / switched and output to the subsequent stage.

Each of the receiving systems 10-i includes a clock recovery unit 22-i. Clock recovery unit 22
-I reproduces a clock based on the demodulated output of the demodulator 16-i and supplies the reproduced clock to the code discriminator 18-i.

An integrating unit 24-i is connected to the clock reproducing unit 22-i, and the integrating unit 24-i is connected to the comparing unit 26 and the changeover switch 20 in this order.

The detection of the amount of time fluctuation and the switching based on the result, which are the characteristic functions of the present proposal, are realized by the clock reproducing unit 22-i, the integrating unit 24-i, the comparing unit 26, and the changeover switch 20.

FIG. 18 shows the configuration of the clock recovery section 22-i in the prior proposal.

The clock reproducing unit 22-i shown in FIG.
Are a code discriminating unit 28-i, an edge detecting unit 30-i, a phase comparator (PD) 36-i, an EOR 38-i, and an AND 46.
-I, an up / down counter 40-i, a pulse addition / removal circuit 42-i, a frequency divider 34-i, and a same sign continuous detection unit 48-i.

That is, the demodulated output of the demodulator 16-i is:
"0" is determined by the threshold value in the code determination unit 28-i.
"1" is determined, and then the edge is detected by the edge detection unit 30-i. The output of the edge detector 30-i is P
D36-i.

The output terminal of the PD 36-i is connected to the EOR 38-i, and the output terminal of the EOR 38-i is connected to the count enable / disable input of the up / down counter 40-i via the AND 46-i. Up / down counter 40-i
Is a pulse adding / removing circuit 42-i and a frequency divider 34-i.
Are sequentially connected. The reproduced clock output from the frequency divider 34-i is supplied to the PD 36-i, the EOR 38-i, and the up / down counter 40-i.

That is, the output of the edge detector 30-i is compared in phase with the reproduced clock in the PD 36-i, and the EOR 38-i calculates the exclusive OR of the phase comparison result with the reproduced clock. EOR38-
i is an element for ripple cancellation, and its output includes a time fluctuation (jitter) of the demodulated output with respect to the reproduced clock in the vicinity time when the code (data) indicated by the demodulated output fluctuates.

On the other hand, the output of the code discrimination unit 28-i is connected to the same code continuation detection unit 48-i, and the output of the same code continuation detection unit 48-i is connected to the AND 46-i. That is, the same-code continuation detecting unit 48-i uses
The current data is compared with the data at the immediately preceding timing, and "1" is output when there is a difference.

The output of the same code continuation detecting section 48-i is A
ND46-i. The AND 46-i calculates the logical product of the output of the same-code continuation detecting unit 48-i and the output of the EOR 38-i.

Here, the output of the EOR 38-i includes the time fluctuation as described above, and is logically ANDed with the output of the same code continuation detecting unit 48-i which becomes "1" in accordance with a change in data. As a result, a time fluctuation that becomes apparent with a change in data is detected, and the time fluctuation amount is output as a time fluctuation amount pulse indicating the duration of the “1” value.

This time fluctuation amount pulse is several tens to 100 μm.
s pulse width, and an integration unit 2 with a time constant of about ms
2-i.

The integrator 22-i is composed of a CR integration circuit, integrates the time fluctuation amount pulse, and outputs a voltage proportional to the time fluctuation amount. The comparing section 26 compares the output of the integrating section 22-i with a voltage. The changeover switch 20
Sign determination unit 1 corresponding to integration unit 22-i related to lowest voltage
8-i is selected, and the output code (column) is output.

Therefore, in the previously proposed example, the amount of time fluctuation is obtained by using the output of the EOR 38-i for ripple cancellation, and the receiving system having the least amount of time fluctuation and the least influence of fading is obtained according to the result. 10-i can be selected and code output. Such an operation does not require transmission with a special signal added, etc.
Can run simultaneously with service.

Further, the receiving device can be simply configured, for example, the integration section 24-i can be realized with a simple configuration as a CR integration circuit.

[0026]

However, in the prior proposal, since the PD output is integrated and used, there is a problem that a malfunction of the comparison unit and a malfunction of the changeover switch may occur. That is, EOR and A from PD
The time fluctuation amount pulse output via the ND is a pulse train having a pulse width of about several tens to 100 μs. When this pulse is integrated by an integrating section having a time constant of about several ms, it may be buried in the internal noise of the integrating section. As a result, an analog voltage corresponding to the number of pulses may not be obtained.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and realizes more accurate switching of a receiving system while using a pulse with a time fluctuation amount, and realizes intersymbol interference due to a delayed wave. Is more preferably eliminated.

[0028]

In order to achieve the above object, according to the present invention, a switching means for switching a receiving system includes a counter for counting the number of time fluctuation amount pulses, and based on the counting result of the counter. The output from the receiving system having a small number of pulses is selectively output.

Further, the present invention is characterized in that a means for changing the gate time of the counter according to the vehicle speed is mounted on the vehicle.

A third aspect of the present invention is characterized in that a gate is provided which takes out only a pulse generated near the center of the reproduction clock cycle from the time fluctuation amount pulse and supplies it to the counter.

[0031]

According to the present invention, the number of time fluctuation pulse is counted by the counter. Here, as shown in FIG. 1, the larger the delay time τ in digital modulation, the larger P
The number of time fluctuation amount pulses (number of PD output pulses) output from D increases, and as shown in FIG. 2, the better the C / N, the smaller the number of PD output pulses. As the delay time τ is shorter and the C / N is better, the bit error rate is lower. Therefore, as shown in FIG. 3, the smaller the number of PD output pulses, the lower the bit error rate. Therefore, by switching the receiving system based on the result of counting by the counter, the influence of the delayed wave is eliminated as in the previous proposal using the integrated value,
Deterioration of the bit error rate due to deterioration of C / N is also prevented at the same time. Further, since the counting operation by the counter is hardly affected by noise or the like, the switching accuracy of the receiving system is improved. 1 to 3 show data under a specific modulation method and transmission rate, but the same tendency holds for wireless communication by digital modulation.

In the present invention, the gate time of the counter is changed according to the vehicle speed. In general, the fading cycle changes according to the vehicle speed. Therefore, the switching of the receiving system is performed according to the vehicle speed, so that the response to the fading cycle change due to the vehicle speed change is improved, and the switching accuracy of the receiving system is further improved. .

According to the third aspect, a pulse generated near the center of the reproduction clock cycle is extracted from the time fluctuation amount pulse supplied to the counter. The counter counts only this pulse. Since a pulse generated near the center of the reproduction clock cycle is output when a relatively large amount of jitter occurs, counting pulses that affect bit errors is performed by counting the pulses (pulses that have little effect on bit errors). Is excluded), and the accuracy of estimating the bit error rate is improved.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. The same members as those in the previously proposed configuration shown in FIGS. 17 and 18 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 4 shows the configuration of a diversity receiver according to one embodiment of the present invention. As shown in this figure, in the present embodiment, the integrator 24-i (i = 1,
2,... N), a counter 50-i is provided, and a counter 50-i is provided in accordance with a vehicle speed pulse from the vehicle speed sensor 52.
The gate time is switched.

In this embodiment, a time fluctuation pulse is input to the counter 50-i from the clock recovery unit 22-i having a configuration as shown in FIG. 18, and the counter 50-i determines the number of time fluctuation pulses. Is counted. The comparison unit 26 determines, based on the counting result by the counter 50-i,
Receiving system 10-i with the smallest number of time fluctuation pulse
Switch 20 so as to select.

In this manner, by selecting the receiving system 10-i by counting the number of time fluctuation amount pulses, the influence of internal noise and the like can be eliminated, and the receiving system can be switched with higher accuracy than the previously proposed configuration. Operation is realized. That is, several ms
Unlike the case where the integration is performed by the integration unit 24-i having a time constant of about the same level, the optimum reception system 10-i can be selected and switched more accurately without being buried in noise or the like.

In addition, according to this embodiment, it is possible to select the receiving system 10-i having the best C / N while eliminating the interference of the delayed wave. This is based on the principle described above with reference to FIGS.

In this embodiment, the vehicle speed sensor 52
It is used to respond more quickly to changes in the fading cycle due to changes in vehicle speed. FIG. 5 shows receiving system 1
The fading cycle and the switching timing when the number n of 0-i is 2 are shown. As shown in FIG.
The switching cycle of the receiving system 10-i is approximately one half of the fading cycle. In this case, as shown in FIG. 6, when the gate time tg (time from reset to reset) of the counter 50-i is longer than the fading cycle, the response speed of switching of the receiving system 10-i to fading decreases. The effect of diversity is reduced. Since the fading cycle changes in accordance with the change in the vehicle speed v, if the gate time tg of the counter 50-i is fixed, the state shown in FIG.

In this embodiment, a vehicle speed pulse representing the vehicle speed is input from the vehicle speed sensor 52, and the gate time tg of the counter 50-i is changed according to the vehicle speed pulse. Specifically, 1 / of the switching cycle of the receiving system 10-i.
4, the gate time tg is variably set by the following equation.

Tg = 1 / 8f _D = λ / 8v where f _D is the reciprocal of the fading period (fading frequency), and λ is the wavelength of the carrier.

In this way, even when the fading period changes due to the change in the vehicle speed v, the receiving system 10-i can be switched at the optimum timing by following the change quickly, and the influence of the fading can be reduced. By excluding it, the effect of diversity can be secured.

Note that such a change in followability according to the vehicle speed v may be applied to the previously proposed configuration shown in FIG. In this case, as shown in FIG. 7, the vehicle speed pulse is input to the integrator 24-i, and the integrator 24-i is reset so that the integration time constant becomes λ / 8v as in the above embodiment. Further, the configuration of the present invention is not limited to a mobile phone system or the like, but can be applied to a low-speed digital mobile communication system such as a 9.6 kbps teleterminal.

FIG. 8 shows the configuration of a diversity receiver according to a second embodiment of the present invention. The configuration shown in this figure is a configuration in which gates 54-1, 54-2,..., 54-n are added to the configuration of the embodiment shown in FIG.

The gate 54-i is connected to the clock recovery unit 22-
i and the counter 50-i. Gate 5
4-i has a function of removing a pulse having little effect on a bit error from the time fluctuation amount pulse output from the clock recovery unit 22-1. Time fluctuation pulse P _PD
Includes a large pulse P _j effect on small pulse and bit errors affect the bit error, the. Gate 54-
As shown in FIG. 9, i is opened at a timing near the center of one cycle of the reproduction clock, and a pulse having little effect on bit errors contained in the time fluctuation amount pulse _PPD is counted by the counter 5.
0-i is not supplied. In FIG.
Gate 54-i is open during T / 4. Thus P _PD included in the gate represents a large jitter, the bit error is likely to occur, believed P _PD in the gate represents a small jitter is small possibility that bit errors occur .

Therefore, according to this embodiment, the pulse having little influence on the bit error is not related to the counting operation in the counter 50-i. As a result, the bit error rate when the bit error rate is relatively good The effect of improving the estimation accuracy of is obtained.

That is, as shown in FIGS. 1 and 2, when the delay time τ is relatively small or the C / N is relatively good, the number of outputs of the PD 36-i hardly changes. Specifically, in the region of τ <1.0 μs in FIG. 1 and the region of C / N> 30 dB in FIG.
6-i hardly changes, and the time fluctuation amount pulse P _PD in the corresponding region where the bit error rate is <10 ^−2.
The number of changes hardly. Therefore, the bit error rate <1
In the range of 0 ^-2 , it is difficult to estimate the bit error rate in the configuration of the first embodiment.

In this embodiment, since the pulse having little influence on the bit error does not contribute to the counting operation of the counter 50-i for estimating the bit error rate, the accuracy of estimating the bit error rate is improved. For example, as shown in FIGS. 10 and 11, the number of pulses P _j is counted by the counter 50-i has a linear relationship with respect to the delay time τ and C / N, 12 As shown in the above, the number of pulses P _j and the bit error rate have a clear positive correlation. Therefore, even in a region where the interference of the delay wave is small and the bit error rate is low, it is possible to preferably perform the estimation of the bit error rate and appropriately switch the reception system 10-i.

In this embodiment, the gate 54
-I is the opening timing T / 4. This may be set to another value. For example, as shown as timings 1 to 3 in FIG. 13, the gate timing can be varied within the range of 1 bit length T.

FIG. 14 shows the relationship among the delay time τ, the pulse P _j , and the bit error rate (BER) at each of the timings 1 to 3 shown in FIG. As shown in this figure, it can be seen that the shortest time 1 among the three types of time when the gate 54-i opens is the timing at which the bit error rate estimation can be performed most suitably. Specifically, the bit error rate B. to the number of pulses P _j E. FIG. Timing 1 in which R increases with a smaller gradient corresponds to the bit error rate B.R. E. FIG. Preferred for estimating R.

FIG. 15 shows the time change of the number of pulses P _j and the time change of the bit error pulse. The bit error pulse is a pulse indicating occurrence of a bit error.
As apparent from the figure, pulse P _j and the bit error pulses is substantially the same pulse, it can be seen that it is possible to take out a pulse P _j regarded as bit error pulses.

Further, according to the present embodiment, even in a low-speed digital mobile communication system (for example, a 9.6 kbps teleterminal or the like), the performance becomes higher than that of the conventional selective diversity reception method after reception power comparison detection. Replacement with the device according to the example is possible.

[0053]

As described above, according to the present invention, the number of time fluctuation pulses is counted and a receiving system having a small number of pulses is selected, so that interference of delayed waves is small and C / N is good. A suitable receiving system. As a result, the performance is improved as compared with the selection diversity method after reception power comparison detection, and the interference of the delayed wave can be reduced. In addition, more accurate reception system switching can be realized by eliminating the influence of noise and the like. In addition, it is possible to monitor the result of counting the number of pulses of the time fluctuation amount, whereby it is possible to know the communication line quality and use it for, for example, a reference signal for zone switching.

According to the second aspect, since the gate time is changed and set according to the vehicle speed, it is possible to sequentially respond to the change of the fading cycle due to the change of the vehicle speed, and it is possible to realize more suitable switching of the receiving system.

According to the third aspect of the present invention, a pulse having a small effect on a bit error is removed from the time fluctuation pulse to execute the coefficient operation of the counter. The accuracy of the estimation can be improved, and the application range of the present invention is widened.

[Brief description of the drawings]

FIG. 1 is a diagram showing a delay time vs. phase detector output pulse number characteristic in the case of BPSK delay detection, 512 kbps, fading frequency = 40 Hz, and C / N = 20 dB.

FIG. 2 shows C for BPSK delay detection and 512 kbps.
FIG. 6 is a diagram illustrating a / N vs. phase detector output pulse number characteristic.

FIG. 3 is a diagram showing the number of phase detector output pulses versus bit error rate characteristics in the case of BPSK differential detection, 512 kbps, fading frequency = 40 Hz, and C / N = 20 dB.

FIG. 4 is a block diagram illustrating a configuration of a diversity receiving apparatus according to one embodiment of the present invention.

FIG. 5 is a diagram illustrating a relationship between a fading cycle and a switching timing of a reception system.

FIG. 6 is a diagram illustrating a problem when the gate time of the counter or the time constant of the integration unit is longer than the fading cycle.

FIG. 7 is a block diagram illustrating a configuration of a diversity receiver according to a reference example in which a vehicle speed sensor is added to the configuration of the previously proposed configuration.

FIG. 8 is a block diagram illustrating a configuration of a diversity receiver according to a second embodiment of the present invention.

FIG. 9 is a diagram showing gate timing in this embodiment.

FIG. 10 shows delay time τ vs. pulse P _j in this embodiment.
FIG. 7 is a diagram showing characteristics of the number of occurrences of the slash.

11 is a diagram showing the characteristics of the generation number of C / N versus pulse P _j in this example.

FIG. 12 is a diagram showing the number of generated pulses P _j versus bit error rate characteristics in this embodiment.

FIG. 13 is a diagram showing three types of timing that can be adopted in this embodiment.

14 shows a delay time τ at timings 1 to 3, the number of pulses P _j , and a bit error rate B. FIG. E. FIG. It is a figure which shows the relationship of R.

FIG. 15 is a diagram showing a relationship between a pulse P _j and a bit error pulse.

FIG. 16 is a diagram illustrating a difference in bit error rate depending on the presence or absence of diversity.

FIG. 17 is a block diagram showing a configuration of a diversity receiving device proposed by the present applicant earlier.

FIG. 18 is a block diagram showing a configuration of a clock recovery unit disclosed in the prior proposal.

[Explanation of symbols]

 , 10-n receiving system 22-1, 22-2,..., 22-n clock reproducing unit 26 comparing unit 50-1, 50-2,... 50-n counter 52 vehicle speed sensor 54- 1,54-2, ... 54-n gate

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04B 7/00 H04B 7/02-7/12 H04B 7/24-7/26 113 H04L 1/00-1/24 H04Q 7/00-7/04

Claims (3)

(57) [Claims] 1. A plurality of reception systems for receiving and demodulating radio waves, and a phase of a demodulation output edge of a corresponding reception system is compared with a reproduced clock, and a result of the phase comparison is output as a time fluctuation pulse. Detecting means, and switching means for selectively outputting the output from the receiving system having the smallest delay time of the received radio wave based on the time fluctuation amount pulse,
A diversity receiving apparatus comprising: a switching means having a counter for counting the number of time fluctuation pulses, and selectively outputting an output from a receiving system having a small number of pulses based on the counting result of the counter. apparatus. 2. The diversity receiving apparatus according to claim 1, further comprising means for changing a gate time of a counter according to a vehicle speed, said diversity receiving apparatus being mounted on a vehicle. 3. The diversity receiving apparatus according to claim 1, further comprising a gate for taking out only a pulse generated near the center of the reproduction clock cycle from the time fluctuation amount pulse and supplying the pulse to a counter.