JP2978643B2 - Clock divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock frequency dividing circuit, and more particularly to a system using a digital circuit.

[0002]

2. Description of the Related Art A conventional clock frequency dividing circuit is shown in FIG. As shown in FIG. 6, a clock is input to the input terminal I. This signal is counted by the down counter C. In this down counter C, the value written decreases by one each time the input signal rises, and the output terminal O goes high when the value becomes zero. By using this output as a write signal for the down counter C, the value of the frequency division ratio setting register R is written to the down counter C, and counting is started again. By performing this operation continuously, the frequency of the clock input to the input terminal I is reduced to 1 /
The configuration was such that the frequency of R was output from the output terminal O.

[0003]

In this conventional clock frequency dividing circuit, frequency division other than 1 / n (n: natural number) cannot be performed.

Therefore, in a system such as a personal computer that requires a plurality of clocks, a plurality of clocks such as a system clock, a clock for clock, a communication clock, and a display clock are used, so that separate oscillation circuits are required. .

An object of the present invention is to provide a clock frequency dividing circuit in which a circuit is constituted by one oscillation circuit.

[0006]

In order to achieve the above object, a clock frequency dividing circuit according to the present invention comprises an input terminal and an input terminal.
The first output signal is activated at the Nth clock of the
And the second output signal is activated at the (N + 1) th clock.
An active counter, the first output signal and the
Output one of the second output signals to the output terminal
And the output of the output terminal is active.
Control circuit for switching the output signal of the selection circuit every time
And a clock frequency dividing circuit.

Further, a clock frequency dividing circuit according to the present invention comprises:
A clock signal whose input frequency is Y (Hz) is converted to X (Hz).
Clock divider circuit that converts to clock signal of output frequency
A is, the Y / X R1 + R2 / R3 (R1~R3 the self
R2 <R3), and convert R1 to R3 to
Means for setting the first to third registers, respectively;
The first R1 clock of the clock input to the input terminal
Becomes active, and at the R1 + 1 clock
A counter whose second output signal is active;
Output of one of the first output signal and the second output signal
A first selection circuit for outputting a signal to an output terminal;
And a control circuit for controlling the selection circuit, the control circuit ,
A temporary storage register, the second register, and the third
And the value of the temporary storage register and the second
An adding circuit for outputting a value obtained by adding the value of the register to the register;
The value of the third register was subtracted from the output of the adder circuit
Outputs a value and is active when the subtraction value is negative
Subtracting a BORROW signal to be output to the selection circuit.
Circuit, the output of the adding circuit and the output of the subtracting circuit are input.
When the BORROW signal is active,
Writing the output of the subtraction circuit into the temporary storage register,
When the BORROW signal is inactive, the additional
A second circuit for writing the output of the arithmetic circuit into the temporary storage register.
A selection circuit, wherein the first selection circuit includes the BOR
When the ROW signal is active, the first output signal is
Output when the BORROW signal is inactive
Outputs the second output signal .

[0008]

[Function] By changing the dividing ratio for each cycle,
Performs frequency division at an arbitrary frequency division ratio.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, a clock input to an input terminal I is input to a down counter C to count.
As a result of this counting, the output b becomes high when it becomes 1, and the output a becomes high when it becomes 0. By selecting the two outputs of the down counter C at a fixed ratio by the selection circuit S and the control circuit CTR and outputting them from the output terminal O, frequency division other than 1 / n (n: natural number) is possible. Become.

As an example, FIG. 2 shows an example of a circuit for realizing frequency division 2/9. In order to realize the 2/9 frequency division, it is only necessary to output two pulses every input of nine clocks. Therefore,
This can be achieved by alternately performing the divide-by-4 and divide-by-5. FIG.
In the circuit shown in (1), the dividing ratio R is set to 4 (100 in binary). In the down counter C, the value written to each time a clock is input from the input terminal I becomes 1
Is subtracted by one. Therefore, after the division ratio R is written to the down counter C, the "= 1" signal goes high at the fourth clock, and the "= 0" signal goes high at the fifth clock.

The output level of the control circuit CTR is inverted each time the output terminal O goes high. In the selection circuit S, when the output of the control circuit CTR is at a low level, “=”
When the "0" signal is at a high level, the "= 1" signal is selected and output.

As a result, the "= 0" signal and the "= 1" signal are alternately output to the output terminal O, and a frequency division of 2/9 can be realized. The down counter C is written with a value to which the frequency division ratio R is set each time the output terminal O goes high. FIG. 3 shows the operation of this circuit.

Next, FIG. 4 shows an example of a circuit in which an arbitrary frequency division ratio can be set. In this example, the setting of the x / y dividing ratio can be set without any restrictions other than the bit length of each dividing ratio setting register (R1, R2, R3). Where x,
y is a natural number and has a relationship of y / x.

Each division ratio setting register (R1, R2, R
The value set in 3) is calculated according to the following procedure.

[0016]

(Equation 1) Set the value in each register. R1: a, R2: y-ax, R3: x

The operation of each block of the circuit shown in FIG. 4 will be described below. The clock input from the input terminal I is input to the down counter C. This down counter C
When the output of the selection circuit S1 is active (in this embodiment, high level), the content of the frequency division ratio setting register R1 is latched in synchronization with the input of the next count.

When the output of the selection circuit S1 is active (low level in this embodiment), the latched content is decremented by one for each count input, and when the result is 1, "= 1" When the "" signal is 0, the "= 0" signal becomes active.

In the selection circuit S1, when the output of the control circuit CTR is inactive and the "= 0" signal is active, the "= 1" signal is selected and output from the output terminal O.

The control circuit CTR operates every time the output of the selection circuit S1 changes from active to inactive. First, the content selected by the selection circuit S2 is written in the temporary storage register TMP. Next, the content written in the temporary storage register TMP and the content of the frequency division ratio setting register R2 are added by the addition circuit ADD. This result (TMP +
R2) subtracts the contents of the frequency division ratio setting register R3 from the subtraction circuit S
Subtract by UB.

As a result, when (TMP + R2-R3) is negative, the "BORROW" signal is active (high level in this embodiment), and when it is positive, it is inactive (low level in this embodiment). ). This "BORRO
The W ″ signal becomes the output of the control circuit CTR as it is. At the same time, it is input to the selection circuit S2 in the control circuit CTR.

When the "BORROW" signal is active, the selection circuit S2 outputs the result (TMP + R) of the subtraction circuit SUB.
2-R3) is added to the adder ADD when inactive.
(TMP + R2) is selected and output. This output is written to the temporary storage register TMP at the next operation timing of the control circuit CTR.

The operation of this circuit is defined by an input frequency of 10 MHz.
z (clock frequency of CPU), output frequency: 3276
The case of 8 Hz (clock frequency of a built-in clock) will be described as an example.

First, the value set in each division ratio setting register is:

(Equation 2)

Assume that the value of the temporary storage register TMP is 0 and the value of the down counter C is 305 in the initial state (point in FIG. 5). At this time, (TMP + R2-R3)
Becomes negative, and the "BORROW" signal becomes active. Therefore, the selection circuit S1 selects the “= 1” signal. This signal becomes active for one clock at the 305th count of the input clock. Therefore, at the 306th clock, 305 is written to the down counter C and 45 (TMP + R2) is written to the temporary storage register. This completes the first frequency division with a frequency division ratio of 1/305.

In the second division, (TMP + R2-R
Since 3) is negative, the input clock is divided by the value of R1 (division ratio 1/305).

As described above, the frequency division proceeds, and the TMP becomes 225 at the sixth time, and (TMP + R2-R3) becomes positive. Therefore, the "= 0" signal is selected by the selection circuit S2, and the frequency division ratio becomes

(Equation 3) Becomes When this frequency division is completed, the value written in TMP is 14 (TMP + R2-R3).

By continuously performing the above operations,
Frequency division ratio of clock (10 MHz) from input terminal I 25
A frequency of 6/78125 (32768 Hz) can be output from the output terminal O.

[0029]

As described above, according to the present invention, an arbitrary frequency division can be performed by changing the frequency division ratio for each cycle. This has the effect of requiring only one circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram when the frequency division ratio of the frequency dividing circuit shown in FIG. 1 is 2/9.

FIG. 3 is a signal waveform diagram of each unit when the frequency dividing circuit of FIG. 2 is operated.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a diagram illustrating values of respective registers when the frequency dividing circuit of FIG. 4 is operated.

FIG. 6 is a block diagram showing a conventional frequency divider.

[Explanation of symbols]

 a counter = 0 output b counter = 1 output C down counter CTR control circuit I input terminal O output terminal R division ratio setting register S selection circuit

Claims (2)

(57) [Claims] An N clock of a clock input to an input terminal.
At the first clock, the first output signal becomes active, and N + 1 clocks are output.
A counter in which the second output signal becomes active at the lock
And one of the first output signal and the second output signal
A selection circuit for outputting an output signal of the output terminal to an output terminal; and a selection circuit each time the output of the output terminal becomes active.
And a control circuit for switching an output signal of the path. 2. A clock signal having an input frequency of Y (Hz).
To a clock signal having an output frequency of X (Hz).
A lock frequency dividing circuit, wherein Y / X is R1 + R2 / R3 (R1 to R3 are natural numbers, R2
<R3), and R1 to R3 are the first to
A means for setting each in the third register and an input terminal
The first output signal at the R1 clock of the input clock
Becomes active, and the second output is output at the R1 + 1 clock.
A counter whose signal is active, and said first output signal.
And output one of the second output signal and the second output signal.
A first selection circuit for outputting to the terminal, and the first selection circuit
And a control circuit for controlling the temporary storage register and the second register.
, The third register, and the temporary storage register.
Outputting a value obtained by adding the value and the value of the second register
An adder circuit, and an output of the adder circuit, the third register
And outputs a value obtained by subtracting the value of
The BORROW signal, which becomes active when
A subtraction circuit to output the output of the addition circuit and the subtraction
The output of the circuit is input, and the BORROW signal is activated.
Output, the output of the subtraction circuit is stored in the temporary storage register.
And the BORROW signal is inactive
In the case of, the output of the addition circuit is stored in the temporary storage register.
A second selection circuit for writing, wherein the first selection circuit activates the BORROW signal.
Output the first output signal and output the BOR
When the ROW signal is inactive, the second output signal
A clock frequency dividing circuit for outputting a clock signal.