JP2973417B2 - Digital video signal recording device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording apparatus for a digital video signal applied to record a digital video signal on a magnetic tape by a rotary head. [Prior Art] In a digital VTR which records a digital video signal on a magnetic tape by a rotating head and reproduces the digital video signal from the magnetic tape, a product code is used to correct an error generated in a recording / reproducing process. used. The product code encodes an error correction code in the vertical and horizontal directions of a matrix arrangement of data. FIG. 5 shows a configuration of a recording circuit of a conventional digital VTR. A digital video signal from an input terminal denoted by reference numeral 21 is supplied to a memory 22. In the memory 22, even-numbered data and odd-numbered data of the input digital video signal are separated, and sequence data (even-numbered data) composed of even-numbered data are separated. The sequence of the data is different between a sequence of the odd-numbered data and a sequence of the odd-numbered data (the odd-numbered sequence). This rearrangement of the data order is called shuffling. Memory 22
The even-numbered sequence and the odd-numbered sequence are outer-code encoders
The codes are supplied to 23 and 42, respectively, and the outer codes are coded. Data output from the outer-code encoders 23 and 24 are written to the memories 25 and 26, respectively. Memory 25 and 26
Converts a sequence of outer codes into a sequence of inner codes. Memory 25
, And 26 are supplied to inner-code encoders 27 and 28, and the encoders 27 and 28 encode the inner code. The series data obtained from the inner-code encoders 27 and 28 are supplied to synchronization adding circuits 29 and 30, respectively, and a synchronization signal is inserted into the series data. Recording signals obtained from the synchronization adding circuits 29 and 30 are obtained at output terminals 31 and 32, respectively. Although not shown, a recording signal is supplied to a two-channel rotating head and recorded on a magnetic tape as two parallel tracks. For the sake of simplicity, it is assumed that the unit of the product code (referred to as a block) is configured for every 16 sample data (1 sample data is, for example, 8 bits). As shown in FIG. 6A, when 32 consecutive sample data (words) are supplied to the input terminal 21, one output terminal b of the memory 22 is connected to an even numbered terminal as shown in FIG. An even number series in which the number data is located in order is obtained, and the other output terminal c of the memory 22 is composed of odd number data and has an outer code (referred to as C1 code) as shown in FIG. 6C. An odd number sequence in which the arrangement is rearranged for each length (four words) of the code series (referred to as the C1 series) is obtained. FIG. 7A
7 shows a code configuration in a state encoded by the inner code encoder 27, and FIG. 7B shows a code configuration in a state encoded by the inner code encoder 28. In FIG. 7A, C1 every four words aligned in the vertical direction
The C1 code is encoded for the series, and the check word P of the C1 code is located in the fifth row. The direction of the C1 series matches the order of the series supplied to the outer-code encoder 23. Further, the C2 code is encoded for every four words of the C2 series arranged in the horizontal direction, and the check word Q of the C2 code is located in the fifth column. This C2
The direction of the series is consistent with the order in which they are recorded on the magnetic tape. The configuration of the error correction code for the odd-numbered sequence is the same as the configuration of the error correction code for the even-numbered sequence described above. Each of the C1 series in FIG.
The order of data is rearranged every four words. The data of the first row in each of FIGS. 7A and 7B is recorded on the magnetic tape 33 as two parallel tracks as shown in FIG. In FIG. 8, S indicates the scanning direction of the rotary head, and T indicates the running direction of the magnetic tape 33. As can be understood from FIG.
, The order of data is rearranged (shuffled), so that the recording position of adjacent words is
33 are different in the width direction. That is, it is possible to prevent a temporally continuous word from becoming an error word due to a scratch in the longitudinal direction of the magnetic tape 33, and to improve the ability of the reproducing side to correct the error word. [Problems to be Solved by the Invention] A conventional digital video signal recording device is a memory 2 that rearranges the order of data from the C1 series to the C2 series.
In addition to 5 and 26, a memory 22 for shifting the recording position of temporally adjacent words included in the even-numbered sequence and the odd-numbered sequence is required. An object of the present invention is to provide a recording apparatus for a digital video signal which does not require a memory provided before an encoder for an outer code and has a simplified configuration. [Means for Solving the Problems] The present invention relates to encoding of an error correction code for each column and each row of a matrix-like first data array composed of time-series even-numbered data of a digital video signal. The encoded first data sequence is recorded on a first track of a magnetic tape by a rotary head, and a second matrix-like matrix constituted by time-series odd-numbered data of a digital video signal. Recording a digital video signal in which an error correction code is encoded for each column and each row of the data array, and the encoded second data sequence is recorded on a second track adjacent to the first track. A separating circuit for separating a digital video signal into even-numbered data and odd-numbered data; data in each column of the first data array; A first error correction encoder that performs encoding of a first error correction code on data of each column of the second data array, and a first error correction code added with a check word of the first error correction code. The data of each row of the data array and the data of each row of the second data array to which the check word of the first error correction code has been added are encoded with a second error correction code, and are written on a magnetic tape. A second error correction encoder for sequentially outputting data of each row including a check word of a second error correction code for each row for recording, a first error correction encoder, and a second error correction encoder A memory inserted between the encoder and the encoder to rearrange the order of data from the column direction to the row direction, and a check word of a first error correction code is added to the memory. The first of each column of data in the data sequence,
When writing data of each column of the second data array to which the check word of the first error correction code is added, adjacent data included in the first data array and the adjacent data included in the second data array, A digital video signal recording apparatus characterized in that the order of a plurality of words included in each column is made different from the original order so as to be included in different rows of the first data array and the second data array, respectively. . [Operation] In the even-odd separation circuit 2, the input digital video signal is separated into an even-numbered sequence composed of even-numbered words and an odd-numbered sequence composed of odd-numbered words. These even-numbered series and odd-numbered series are written in the memories 5 and 6, respectively. When writing an odd-numbered sequence to the memory 6, the recording positions of temporally adjacent words included in each of the even-numbered sequence and the odd-numbered sequence are shifted in the longitudinal direction of the magnetic tape. Therefore, according to the present invention, there is no need to provide a memory dedicated to rearranging data, and the configuration can be simplified. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, reference numeral 1 denotes an input terminal to which a digital video signal obtained by quantizing one sample data (word) into 8 bits is supplied. This digital video signal is supplied to the even / odd separation circuit 2. In the even-odd separation circuit 2, even-numbered words and odd-numbered words are alternately taken out to output terminals b and c in synchronization with the sampling clock of the input digital video signal. FIG. 2A shows an input digital video signal;
Each number (0 to 31) is a word number. In this embodiment, a product code is used as an error correction code, and one block of the product code is composed of 16 words of video data. As shown in FIG. 2B, an even-numbered sequence consisting of even-numbered words is taken out from one output terminal b of the even / odd separation circuit 2, and the other output terminal c is taken out as shown in FIG. 2C. Then, an odd-numbered sequence consisting of odd-numbered words is extracted. These even-numbered sequences and odd-numbered sequences are supplied to encoders 3 and 4 of outer codes (referred to as C1 codes), respectively. C1
In the code encoders 3 and 4, an error correction code is coded for each C1 series of four words, and for example, a one-word check word P is generated. Data including the check word P from each of the outer code encoders 3 and 4 is written to the memories 5 and 6. The memories 5 and 6 each have a capacity capable of storing, for example, two blocks of data of a product code, and while data from the encoders 3 and 4 is written in the memory area of one block, Data already written is read from the memory area. When the data from the encoders 3 and 4 is written into the memories 5 and 6, the recording positions of adjacent data included in the even-numbered series and the odd-numbered series are controlled so as to be different in the width direction of the magnetic tape. FIG. 3A shows a state where data from the encoder 3 has been written to the memory 5, and FIG. 3B shows a state where data from the encoder 4 has been written to the memory 6. However, the check word Q of the inner code (C2 code) is stored in the memory 5
And 6 are not written. In FIGS. 3A and 3B, every four words in the vertical direction indicated by C1 are the C1 series. For example, in an even-numbered series, a C1 code check word P is generated for four words (0, 2, 4, 6), and in an odd-numbered series, a check word P is generated for four words (1, 3, 5, 7). As a result, a check word P of the C1 code is generated. When each of the C1 series including the check word P is written into each column of the memory 5 with respect to the memory 5, the write start address is sequentially shifted. As is clear from FIG. 3A, the first word (0, 8, 16, 24) of each C1 series
Are sequentially shifted one word at a time in the diagonal direction. The write address for the memory 6 is also sequentially shifted one word at a time in the diagonal direction as described above. However, as apparent from FIG. 3B, the first C1
The first word (1) of the series is written in the fourth row of the first column. As apparent from FIGS. 3A and 3B, the adjacent two
The words are to be included in different rows in each array. For example, the words 0 and 1 are located in the first row (FIG. 3A) and the fourth row (FIG. 3B), and the words 10 and 11 are located in the third row (FIG. 3A) and the first row. Row (FIG. 3B). The memories 5 and 6 written as described above are sequentially read out from the first row in the horizontal direction and supplied to the encoders 7 and 8 of the C2 code. In each of the encoders 7 and 8, the C2 code is encoded for the C2 series including four words in each row, and the check word Q of the C2 code is generated.
Output data of each of the encoders 7 and 8 is a synchronous addition circuit
9 and 10, and a synchronization signal is added for each data of a predetermined length. The recording data is taken out from the output terminals 11 and 12 of the synchronization adding circuits 9 and 10, respectively. This recorded data is stored in the storage amplifier,
Each is supplied to a rotary head via a rotary transformer or the like, and recorded as two tracks parallel to a magnetic tape. FIG. 4 shows a state in which the data of the first and second rows are recorded on the magnetic tape 13 (the synchronization signal is omitted). In FIG. 4, T indicates the running direction of the magnetic tape 13, and S indicates the scanning direction of the rotary head. The recording positions of adjacent words included in each of the even-numbered series and the odd-numbered series are made different in the width direction of the magnetic tape 13, and therefore, due to scratches in the longitudinal direction of the magnetic tape 13, both temporally adjacent words have an error. Words are prevented, and error data can be satisfactorily corrected on the reproduction side. In the above embodiment, one block of the product code is composed of 25 words for the sake of simplicity. However, actually, one block is constituted by a larger number of words, and the check word P of the C1 code and the check word Q of the C2 code are two or more words. [Effects of the Invention] According to the present invention, when data is written to the memory for conversion of the product code from the C1 series to the C2 series, the data is rearranged by controlling the write address. The memory for rearranging can be omitted.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a schematic diagram showing the order of data used for describing one embodiment of the present invention, and FIG. FIG. 4 is a schematic diagram showing a code pattern according to an embodiment of the present invention, FIG. 4 is a schematic diagram showing a recording pattern according to an embodiment of the present invention, FIG. FIG. 1 is a schematic diagram showing the sequence of data used for explaining a conventional digital video signal recording apparatus, FIG. 7 is a schematic diagram showing a code configuration of a conventional digital video signal, and FIG. FIG. 4 is a schematic diagram illustrating a recording pattern in the recording apparatus. Explanation of main reference numerals in the drawings 1: digital video signal input terminal, 2: even-odd separation circuit,
3,4: outer code encoder, 5,6 memory, 7,8: inner code encoder.

Claims (1)

(57) [Claims] An error correction code is encoded for each column and each row of the first data array in a matrix composed of time-series even-numbered data of the digital video signal,
The encoded first data series is recorded on a first track of a magnetic tape by a rotary head, and a second matrix-like matrix composed of time-series odd-numbered data of the digital video signal is used. Error correction code is encoded for each column and each row of the data array,
An apparatus for recording a digital video signal in which the encoded second data sequence is recorded on a second track adjacent to the first track, wherein the digital video signal is divided into the even-numbered data and the odd-numbered data. A separation circuit that separates the data of each column of the first data array;
A first error correction encoder for encoding a first error correction code for each column of data in the data array, and the first error correction code to which a check word of the first error correction code is added. Each of the data of each row of the data array and the data of each row of the second data array to which the check word of the first error correction code is added is second-ordered.
And a second error correction encoder that sequentially outputs the data of each row including the check word of the second error correction code for each row in order to encode the error correction code and record the data on a magnetic tape. A memory inserted between the first error correction encoder and the second error correction encoder for rearranging the order of data from a column direction to a row direction; The data of each column of the first data array to which the check word of the first error correction code is added, and the data of the second data array to which the check word of the first error correction code is added. When writing column data, adjacent data included in the first data array and the second data array may be different from each other in the first data array and the second data array. So as to be included respectively in that line,
An apparatus for recording a digital video signal, wherein the order of a plurality of words included in each of the columns is made different from the original order.