JP2972568B2 - Bus extender - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system bus expansion device used for an information processing system.

[0002]

2. Description of the Related Art As one of commonly used information processing system configuration methods, there is a so-called bus system for connecting a processor, a main storage device, and an input / output device to a system bus. In such a bus-type information processing system, a processor or an input / output device transmits an instruction for reading or writing data (this is referred to as a request) to a main storage device via a system bus or responds to a read request. Response data (this is called reply)
It can be received via the system bus.

[0003] By connecting a plurality of processors to this system bus, a so-called multiprocessor system can be constructed. If the number of connected processors is from several to about ten, the performance of the entire system will be reduced. It increases almost in proportion to the number of connected devices.

Similarly, the physical memory can be enlarged by connecting a plurality of main storage devices to a system bus. In this case, the entire physical memory space is divided and assigned to each main storage device, so that the entire system has a single physical memory space.

To construct a large-scale high-multiprocessor system, it is necessary to connect a large number of nodes such as a processor and a main storage device to a system bus. However, in practice, a drive for an output buffer of an LSI is required. Due to problems such as performance and delay, the number of nodes that can be connected to one system bus is limited.

As a means for solving such problems and expanding the system bus, Japanese Patent Application Laid-Open No. 61-48060 discloses a bus bridge system in which a buffer is placed between two buses to expand the system bus. Have been. In this system, a system bus is connected to an expansion system bus via a bus extension module, and a main storage device (memory) and an input / output device are connected to both buses. Requests (commands) such as memory read (RD) and memory write (WR) sent to the system bus are transmitted to the other extended system bus via the bus extension module.

As described above, when the system bus is expanded by the bus bridge method, it is possible to construct an information processing system in which a processor or a main storage device twice as large as a system configured by one system bus is connected.

[0008]

In a bus-type information processing system, the number of requests that can be transmitted on a system bus per unit time is approximately proportional to the number of processors connected to the system bus. The upper limit of the number of requests that can be processed by the system bus per unit time is determined by the bandwidth of the system bus.
Therefore, the upper limit of the number of processors that can be connected to the system bus is determined by the bandwidth of the system bus. Even if the number of processors exceeding the upper limit is connected to the system bus, the processing performance of the system bus becomes a bottleneck and the expected performance improvement cannot be obtained.

Therefore, when the number of processors connected to the system bus is doubled by the conventional system bus expansion method as described above, the number of requests transmitted on the system bus per unit time is doubled, There is a problem that the performance of the entire system cannot be improved due to the bottleneck due to the processing capacity of the bus.

An object of the present invention is to improve the performance of the entire system by avoiding a bottleneck in the processing capacity of the system bus, which is a factor hindering performance improvement, when a high multiprocessor system is constructed by connecting two system buses. Another object of the present invention is to provide a bus expansion device that can achieve the above.

[0011]

A bus expansion device according to the present invention is connected to each of two system buses connecting an arbitrary number of processors, a main storage device, and an input / output device, respectively. A bus expansion device for transferring a request transmitted on one system bus of the buses to another system bus, the bus expansion device being connected to the system bus, and the system extending via the bus interface. A determination is made as to which of the two system buses the address of the request received from the bus is a request to access an address space allocated to the main storage device connected to the system bus. Address table unit that determines the system bus to be transferred And an inter-cluster interface for transmitting information from the floating address table unit to the inter-cluster interface of the other bus expansion device. In particular, the address of the request received from the system bus is the address of the two system buses. A floating address table holding information indicating which request is to access an address space allocated to the main storage device connected to which system bus, and information from the floating address table. A logic circuit for determining whether the request should be transferred to the other system bus and preventing transfer to the other system bus when the request should not be transferred to the other system bus. A mode selection register that has or stores a predetermined value in advance, a selector that selects only a specific bit of an address of the request received from the system bus by a signal from the mode selection register, A logic circuit for receiving an output signal of a selector, determining whether the request should be transferred to the other system bus, and preventing transfer to the other system bus when the request should not be transferred to the other system bus. It has a floating address table unit.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a flowchart showing an operation of the embodiment of FIG. 1, and FIG. 3 is a block showing details of a memory array unit of the embodiment of FIG. FIG.

In FIG. 1, a processor (CPU) 50a, a main storage device 30a, and a bus expansion device 10a are connected to a system bus 1a. These are referred to as clusters 2a. Similarly, a processor (CPU) 50b, a main storage device 30b, and a bus expansion device 10b are connected to the system bus 1b. These are referred to as clusters 2b. Processors (CPU) 50a and 50
b, the main storage devices 30a and 30b, and the bus expansion devices 10a and 10b have the same configuration and operation, respectively.

In the main storage devices 30a and 30b, one of physical memory spaces obtained by dividing one continuous physical memory space into two is allocated as a unique physical memory space. The physical memory space allocated to the main storage device 30a is called a cluster 2a system memory space, and the physical memory space allocated to the main storage device 30b is called a cluster 2b system memory space.

The main storage device 30a has a bus interface 31a connected to the system bus 1a, an address decoder 32a for decoding an address input via the system bus 1a, and a main storage section 33a for storing data. I have. Similarly, the main storage device 30b includes a bus interface 31b, an address decoder 32b, and a main storage unit 33b.

The bus expansion device 10a includes a system bus 1a
Interface 11 connected to the other cluster 2 and inter-cluster interface 13 connected to the other cluster 2b
And a floating address table unit incorporating a floating address table (FAT) recording allocation information indicating whether the physical memory space is allocated to the main storage device 30a or 30b connected to the system bus 1a or 1b. (FAT UNIT) 1
2a. The bus expansion device 10b has exactly the same configuration.

As shown in FIG. 3, the floating address table unit (FAT UNIT) 12a includes address registers 41 and 46, valid registers (V registers) 42 and 47, and a cluster register 4
3 and floating address table (FAT) 44
And a logic circuit 45.

The address register 41 and 46, the width of the address holding the requests of 32 bits. The V registers 42 and 47 respectively include an address register 41
And information indicating whether or not the value of the address of the request held by and is valid (valid). Specifically, when a request is received (when a valid address is held), “1” is stored, and when a request is not received (when a valid address is not held), “0” is stored. . The cluster register 43 stores cluster information. This cluster information is set when the information processing system is initialized, and the set value is not changed thereafter. The setting value of the cluster information is
The value is "0" for the bus expansion device 10a of the cluster 2a and "1" for the bus expansion device 10b of the cluster 2b. Floating address table (FA
T) 44 is configured by a memory array, assigned indicating the physical memory space is Re allocated et <br/> in the main memory 30a or 30b are connected to either the system bus 1a or 1b Information ( (Information indicating the correspondence between the physical memory space and the cluster). Specifically, FAT
44 is indexed by the request address, when a "0" when the index address is that assigned to the cluster 2a system memory space, that are assigned to the cluster 2b system memory space taken out "1". In the present embodiment, the FAT 44 is indexed using a 5-bit bit signal 62 of bits 21 to 25 of the request address. FA
T44 is set when the information processing system is initialized, and the set value is not changed thereafter. Logic circuit 4
5 is an exclusive OR circuit (XCR) and an AND circuit (AN
D).

Next, the operation of the bus expansion apparatus configured as described above will be described with reference to FIG.

The processor (CPU) 50 of the cluster 2a
To access the main storage device 30a of the cluster 2a from a, the CPU 50a first accesses the system bus 1a
A request is sent to. This request is received by the bus interface 11 of the bus expansion device 10a (Step 21). Upon receiving the request, the bus interface 11 stores the address of the request in a floating address table unit (FAT UNIT).
12a, and the FAT UNIT 12a sends a floating address table (F
AT) 44 (step 22). As a result, this request is determined to be a request for accessing the memory space of the cluster 2a system (step 2).
3) The processing is terminated in the bus expansion device 10a. CPU
When a request is sent from the system bus 1a to the system bus 1a, the bus interface 31a of the main storage device 30a
At the same time, the request is sent to the main storage unit 33a because the address decoder 32a determines that the request is an access to the main storage device 30a. Is returned to the CPU 50a via a route opposite to the above route.

The processor (CPU) 50 of the cluster 2a
To access the main storage device 30b of the cluster 2b from a, the CPU 50a first accesses the system bus 1a
A request is sent to. This request is received by the bus interface 11 of the bus expansion device 10a (Step 21). At the same time, the bus interface 31a of the main storage device 30a also receives the request, but since the address decoder 32a determines that the request is not an access to the main storage device 30a, the processing of the request in the main storage device 30a is Aborted. The request received by the bus interface 11 is sent to the FAT UNIT 12a,
The floating address table (FAT) 44 is indexed by the address of the request (step 2).
2). Consequently, in order to prove this request is a request to access the cluster 2b system memory space (step 23), the requests cluster 2
A is transmitted from the inter-cluster interface 13 of the bus expansion device 10a to the inter-cluster interface 13 of the bus expansion device 10b of the other cluster 2b (step 24). When the intercluster INTERFACE 13 of the bus expansion unit 10b cluster 2b receives the requests,
The bus interface 11 of the bus expansion device 10b sends the request to the system bus 1b (Step 25). Thereby, the main storage device 30b of the cluster 2b
Receives the request via the bus interface 31b and transmits it to the main storage unit 33b via the address decoder 32b. When the request is a read request, a reply to the request is returned to the CPU 50a via a route reverse to the above-described route.

Next, the FAT UN of the bus expansion device 10a
The operation of the IT 12a will be described in detail with reference to FIG.

The FAT UNIT 12a has a pipeline structure, and a request received from the bus interface 11 is transmitted to the address registers 41 and 46 in synchronization with a clock signal.
6 to the inter-cluster interface 13.

[0025] FAT UNIT12a receives a request from the bus interface 11, and stores the requesters <br/> be sampled in the address register 41 in the First clock cycle, Valentino lid register (V register) 42
To "1". In the next clock cycle, the floating address table (FAT) 44 is indexed using bits 21 to 25 of the address register 41, and the result is sent to the logic circuit 45. The logic circuit 45
44 is a signal the output signal 65 of the output signal 64 and the cluster register 43 Tsu different of, and the output signal 6 3 V register 42 outputs "1" when "1". Therefore, in this case, "1" is output only when the output signal 64 of the FAT 44 outputs "1". That is, the output signal 66 of the logic circuit 45 is "1" only when the received request is an access to the memory space of the cluster 2a system.
Becomes The output signal 66 of the logic circuit 45 is
Sent to and stored. At this time, the address register 4
The 6, requests sent from the address register 41 by the output signal 61 is stored. In the next clock cycle, a request is made from the address register 46 to the inter-cluster interface 13 by the output signal 67.
Although bets is sent, if this requests is access to the cluster 2a system memory space, V register 4
7 is “0”, the inter-cluster interface 13 regards this request as invalid and does not perform the subsequent processing.

FAT UNIT1 of the bus expansion device 10b
The operation of 2a is exactly the same.

The FA in the bus expansion devices 10a and 10b
The T UNIT 12a and the address decoder 32a in the main storage device 30a and the address decoder 32b in the main storage device 30b are functionally substantially the same. However, information held by the address decoder 32a in the main storage device 30a and the information held by the address decoder 32b in the main storage device 30b are used to distinguish an area allocated to the self-storage from another area in the physical memory space. Information
FATUNIT1 in bus expansion devices 10a and 10b
The information held by 2a is different from the physical memory space in that it is information for distinguishing between an area allocated to a clutter-based memory space to which it belongs and an area allocated to another clutter-based memory space. I have.

The above-described bus expansion device can support various types of bus-type information processing systems.
That is, an information processing system in which two main storage devices are connected to both system buses and a total of four main storage devices are connected, or an information processing system in which the main storage device is connected to only one system bus , The address decoders 32a and 32b and the FAT UNIT1
Only by changing the content of the information stored in 2a, it is possible to easily cope with it.

FIG. 4 shows a floating address table unit (FAT UNIT) according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing the details of.

In this embodiment, a mode selection register (MODE) and a selector are used instead of the floating address table (FAT) 44 of the floating address table unit (FAT UNIT) 12a of the bus expansion devices 10a and 10b of the embodiment of FIG. Is used.

That is, as shown in FIG. 4, the floating address table unit (FAT UNIT) 12
b denotes address registers 41 and 46, valid registers (V registers) 42 and 47, a cluster register 43, and a mode selection register (MODE) 78.
, A selector 74 and a logic circuit 45.

Of these components, the configuration and operation of the address registers 41 and 46, the valid registers (V registers) 42 and 47, the cluster register 43, and the logic circuit 45 are shown in FIG. The configuration and operation are the same. Mode selection register (M
ODE) 78 is “00” or “01” or “1”.
The value stored in the MODE 78 is set at the time of initialization of the information processing system, and the set value is not changed thereafter. The stored value is sent to the selector 74 to indicate which bit of the request address extracted from the address register 41 is to be selected.
, Bits 22 to 25 of the address register 41
Are taken out to the selector 74 as the bit signal 82, and arbitrary bits among them are used by the instruction of the MODE 78.

Next, the FAT UN configured as described above is used.
Regarding the operation of IT 12b, FAT U of cluster 2a
The NIT 12b will be described as an example. FA of cluster 2b
The operation of the TUNIT 12b is the same.

[0034] FAT UNIT12b receives a request from the bus interface 11, and stores the requesters <br/> be sampled in the address register 41 in the First clock cycle, Valentino lid register (V register) 42
To "1". In the next clock cycle, bits 22 to 25 of address register 41 are taken out by selector 74 as bit signal 82, and any of them is selected by output signal 88 of MODE 78 and sent to logic circuit 45 as output signal 84. Can be Logic circuit 45
Is the output signal 84 of the selector 74 and the cluster register 4
3 is different from the output signal 65, and the output signal 65 of the V register 42 is "1". That is, only when the received request is an access to the memory space of the cluster 2b system, the logic circuit 4
5 is "1". The output signal 66 of the logic circuit 45 is sent to and stored in the V register 47. Further in the next clock cycle, but by the output signal 67 to the inter-cluster INTERFACE 13 from the address register 46 is <br/> requests sent, if the requests are access to the cluster 2a system memory space, V Since the output signal 68 of the register 47 is “0”, the inter-cluster interface 13 regards this request as invalid and does not perform the subsequent processing.

[0035]

As described above, according to the bus expansion apparatus of the present invention, the address of the request received from the system bus via the bus interface is connected to any one of the two system buses. An unnecessary request is sent to the system bus by providing a floating address table unit that determines whether the request is to access the address space allocated to the storage device and determines a system bus to transfer. Therefore, it is possible to reduce the load on the system bus and avoid a bottleneck in its processing capacity, and thus to improve the performance of the entire system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of FIG.

FIG. 3 is a block diagram showing details of a floating address table unit of the embodiment of FIG. 1;

FIG. 4 is a block diagram showing details of a floating address table unit according to a second embodiment of the present invention.

[Explanation of symbols]

1a, 1b System bus 2a, 2b Cluster 10a, 10b Bus expansion device 11 Bus interface 12a, 12b Floating address table unit (FAT UNIT) 13 Inter-cluster interface 21-25 Step 30a, 30b Main storage device 31a, 31b Bus interface 32a, 32b Address decoder 33a / 33b Main storage unit 50a / 50b Processor (CPU) 41/46 Address register 42/47 Valid register (V register) 43 Cluster register 44 Floating address table (FAT) 45 Logic circuit 61/63/64 / 65, 66, 67, 68, 84.8
8 output signal 62/82 bit signal 74 selector 78 mode selection register (MODE)

Claims (2)

(57) [Claims] 1. An arbitrary number of processors, a main storage device, and an input / output device, which are connected to two system buses respectively, and transmitted to one of the two system buses. A bus expansion device for transferring the request on the other system bus , the bus interface connecting to the system bus,
An address of the request received from the system bus via the bus interface accesses an address space allocated to the main storage device connected to any one of the two system buses. A floating address table unit for determining a system bus to be transferred by judging whether the request is a request to be transferred, and an inter-cluster interface for sending the request to an inter-cluster interface of a bus expansion device on the other end; The address table unit should access an address space allocated to the main storage device connected to any one of the two system buses, in which an address of the request received from the system bus is connected. Request A floating address table holding information indicating whether or not the data is a floating point table, an output signal from the floating address table, an output signal from a cluster register storing predetermined cluster information, and a signal input from the bus interface. inputs the output signal of the first Valentin lid register for storing said a signal output signal and has Tsu different from the output signal and the cluster register floating address table, and the first Cordova lid register a logic circuit for outputting "1" when the output signal is "1", inputs an output signal of said logic circuit
An output signal is output to the inter-cluster interface.
A second valid register and the bus interface
The first address register that holds the signal input from the interface
Input the output signal of the
A second address register that outputs an output signal to Ace
Bus extension device characterized by having a register. 2. A system for connecting an arbitrary number of processors, a main storage device, and an input / output device to each of two system buses, and transmitting the data to one of the two system buses. A bus expansion device for transferring the request on the other system bus , the bus interface connecting to the system bus,
An address of the request received from the system bus via the bus interface accesses an address space allocated to the main storage device connected to any one of the two system buses. A floating address table unit for determining a system bus to be transferred by judging whether the request is a request to be transferred, and an inter-cluster interface for sending the request to an inter-cluster interface of a bus expansion device on the other end; A mode selection register in which an address table unit stores a predetermined value in advance;
A selector for selecting only a specific bit of an address of the request received from the system bus according to a signal from the mode selection register; an output signal of the selector and cluster information set in advance;
The output signal from the cluster register storing
First to store the signal input from the bus interface
And determining whether or not the request should be transferred to the other system bus, and transferring the request to the other system bus when the request should not be transferred to the other system bus. a logic circuit for outputting a signal to block, receiving the output signal of said logic circuit
Output signal to the inter-cluster interface
A second valid register for outputting
The first address that holds the signal input from the interface
Register output signal and input the inter-cluster interface.
Address to output the output signal to the interface
A bus expansion device comprising a register .