JP2969115B1 - Semiconductor device - Google Patents

Abstract

A processor having a maximum / minimum value among a plurality of comparison target data of a plurality of processors on the same semiconductor device can be detected efficiently and at high speed. Then, the comparison target data stored therein is broadcast to other processors via the output data internal common bus 118, the selectors 111 and 112, and the input data internal common bus 119. An arithmetic unit in each processor 200 executes a comparison operation for comparing the magnitude of each of the plurality of comparison target data broadcast from other processors with the comparison target data stored in the processor, and executes the plurality of comparison operations. A plurality of comparison result signals corresponding to the comparison target data are generated. The maximum / minimum value processor detection circuit 350 detects the maximum / minimum value processor based on these comparison result signals and generates its address. This address and the maximum / minimum value are transferred to the outside under the control of the processor selection circuit 300.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device comprising a large-scale integrated circuit (LSI) equipped with a plurality of processors and suitable for a parallel computer for processing a parallel algorithm such as a neural network.

[0002]

2. Description of the Related Art One type of parallel computer is SIMD.
(Single Instruction Stream, Multiple Data Stream
-A single instruction stream / multiple data stream) type parallel computer, and such a parallel computer includes a plurality of processors, a control system for executing a single instruction on the plurality of processors, a plurality of processors, and a plurality of processors. Consists of an interconnected network for communicating data over the Internet. For example, see "Parallel Algorithm on SIMD" described in "Information Processing" Vol. 33, No. 9 (Information Processing Society of Japan, issued on September 15, 1992). A single instruction is sequentially given from the control device to the plurality of processors, and each processor executes each instruction using data unique to each stored in a local memory included therein. . When data transfer between processors is required, it is performed via an interconnection network.

As a practical example of such a SIMD type parallel computer, there is a high-speed neural computer system which realizes high-speed processing of an operation imitating a neural network (neural network). For example, see “Hitachi Microcomputer Techniques”, Vol. Here, a plurality of large-scale integrated circuits (LSIs) each including a plurality of identical processors are mounted on a plurality of boards, and all processors are connected to a control device via a common bus. Each processor is used to mimic the behavior of a neuron (neural cell or nerve fiber).

In such a configuration, a parallel computer including more processors is realized by increasing the number of semiconductor devices. As described above, a semiconductor device equipped with a plurality of processors is a basic unit constituting a processor array of a parallel computer.

In the neural network processing by the SIMD type parallel computer, a plurality of processors execute the same processing on different data, and then execute the same processing.
In some cases, it is necessary to detect the maximum value and the minimum value among a plurality of calculation data calculated by each processor. For example, the learning vector quantization method (Learning Vector
In the Quantization-LVQ) algorithm, this detection is performed for each learning. In the neurocomputer system, a maximum value minimum value detection circuit is provided in a control system device, and the calculated data is sequentially transferred from all processors via a bus. The minimum value was detected.

[0006]

However, such a method requires data transfer by the number of processors, requires at least the processing steps of the number of processors, and takes time to detect the maximum value or the minimum value. . In particular, when the above-described learning vector quantization algorithm is executed by a neurocomputer, the learning time increases in proportion to the number of neurons, and this increase in the detection time is a practical problem of the neurocomputer. As a result of the experiment, it became clear.

An object of the present invention is to provide a semiconductor device having a plurality of processors, which is suitable for efficiently and quickly detecting a processor having a maximum value and a minimum value.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

In order to achieve the above object, according to the present invention, a plurality of processors are provided on a semiconductor device composed of a large-scale integrated circuit (LSI). It is configured to execute a comparison operation for comparing the magnitude of each of the plurality of comparison target data broadcast from the plurality of processors with the comparison target data stored in the processor, and to output a comparison result signal. Further, in response to the comparison result signal output by the arithmetic unit in each processor, a maximum value processor holding a maximum value and a minimum value processor holding a minimum value among the plurality of broadcasted comparison target data. A detection circuit for detecting at least one of the above is provided in the semiconductor device.

As a result, at least one of the maximum value processor and the minimum value processor can be detected in the semiconductor device. This detection is realized by a simple operation of broadcasting comparison target data between processors.

According to a more specific aspect of the present invention, the comparison result signal output from the arithmetic unit in each processor includes a non-minimum value signal indicating that the comparison result data stored in the processor is significant. , And a non-maximum signal that indicates that the comparison result data stored in the processor is smaller. The detection circuit includes a minimum value flag storage unit that stores a flag indicating whether or not the candidate is a minimum value processor, and a maximum value flag storage unit that stores a flag indicating whether the candidate is a maximum value processor. And at least one of them is provided so as to correspond to each one of the plurality of processors. Each of the minimum value flag storage means can be set to an arbitrary state prior to the detection of the minimum value processor. It is configured to be. Each of the maximum value flag storage means can be set to an arbitrary state prior to the detection of the maximum value processor. It is configured to be. As a result, each processor sequentially outputs the comparison operation and the comparison result signal with respect to the plurality of comparison target data sequentially broadcast from the plurality of processors. A processor corresponding to a flag indicating a state of being a candidate for the minimum value processor can be detected as the minimum value processor. Alternatively, a processor corresponding to one of the plurality of maximum value flag storage means indicating that the flag is a candidate for the maximum value processor can be detected as the maximum value processor.

In order to sequentially broadcast the data to be compared from the plurality of processors, a processor selection circuit capable of sequentially selecting the plurality of processors is provided. This circuit can execute the above-described sequential selection in accordance with, for example, addresses sequentially supplied from outside the semiconductor device.

When a parallel computer is configured by using a plurality of such semiconductor devices, the plurality of semiconductor devices can detect at least one of the maximum value processor and the minimum value processor in parallel.

For example, in order to detect at least one of the maximum value processor and the minimum value processor in the entire parallel computer, for example, the maximum value of a plurality of maximum values detected by each semiconductor device or each semiconductor device is detected. What is necessary is just to detect the minimum value among the plurality of minimum values detected by each device. This detection can be performed, for example, by an external device. Therefore, conventionally, the number of processing steps equal to the product of the number of processors in a semiconductor device and the number of semiconductor devices (in other words, the number of all processors in a parallel computer) is required. The processing time required to detect the value processor
According to the present invention, the number of processing steps can be equal to the sum of the number of processors in a semiconductor device and the number of semiconductor devices, so that the detection can be performed at high speed in the entire parallel computer.

According to a more specific aspect of the present invention, a maximum value processor detected in a semiconductor device is detected so that a maximum value processor or a minimum value processor of the entire parallel computer can be detected by a device external to the semiconductor device. Alternatively, an address generating means for generating an address of the minimum value processor is provided in the detection circuit. The processor selection circuit is provided with a circuit for selecting a maximum value processor or a minimum value processor detected in the semiconductor device based on the address. Means is also provided for outputting the comparison target data stored in the selected processor to outside the semiconductor device. Further, there is provided means for outputting the address generated by the address generation means to the outside of the semiconductor device.

In a more desirable mode of the present invention, in each processor, there is provided an instruction means for storing and indicating whether or not the processor is a processor to be compared, and indicates that the instruction means is not a comparison object. The processor is configured to be excluded from the detection target of the maximum value processor or the minimum value processor. That is, when the corresponding processor is not a comparison target, the means for transmitting the comparison target data of each processor is configured to transmit invalid comparison target data instead of the comparison target data stored in the processor. The arithmetic unit of the processor outputs a non-significant comparison result signal when performing a comparison operation on invalid comparison target data. Also,
The minimum value flag storage means or the maximum value flag storage means corresponding to a processor not to be compared can be set in advance to a state that is not a candidate for a minimum value processor or a state that is not a candidate for a maximum value processor. Therefore,
The comparison result signal corresponding to the processor not to be compared and the minimum value flag storage means or the maximum value flag storage means do not affect the detection by the detection circuit.

When a parallel computer is configured by using a plurality of semiconductor devices having such a desirable mode, all processors in any one of the semiconductor devices may not be compared. In such a case, when the detection of the maximum value processor or the minimum value processor of the entire parallel computer is detected by a device external to these semiconductor devices, the detection result of the maximum value processor or the minimum value processor in such a semiconductor device is valid. Not. For this reason, the semiconductor device is provided with means for outputting an invalid maximum value or minimum value outside the semiconductor device and means for outputting an invalid address of the maximum value processor outside the semiconductor device.

When a parallel computer is constituted by using a plurality of semiconductor devices, the detection of the maximum value processor or the minimum value processor of the entire parallel computer is not performed by a device external to these semiconductor devices. Other aspects of the invention that are detectable by a semiconductor device are also disclosed.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention and a parallel computer using the same will be described in more detail with reference to the embodiments shown in the drawings.

(1) Outline of System First, brain neurons (cerebral nerve fibers), that is, neurons of a living body, and their engineering models will be described. A living neuron receives a plurality of inputs from, for example, a plurality of dendrites, and forms a single output from a single axon. The dendrites of the neuron are connected to the axons of other neurons at synapses. Each synapse connection has a weight value (synapse load), and a pulse is formed in the axon when the cumulative addition result of the input and the weight value exceeds a certain threshold value. The weight value is gradually changed by the learning function. In such an engineering model of a neuron, the neuron has a configuration of multiple inputs and one output, and outputs (X1 to Xn) from other neurons and their own weight values (W1 to Wn) are cumulatively added. After adding the threshold value (θ) inherent to the neuron to this, the value Y converted by the internal response function F
Is output. For example, the internal response function F is a step function that forms a signal of logical value “1” when it is positive (meaning that the cumulative addition result has exceeded the threshold value (−θ)) or a continuous nonlinear function. Is the sigmoid function. In a living body, such a large number of neurons are connected (networked) in a complicated manner to form a neural network and perform parallel distributed processing.

FIG. 1 shows an example of a neurocomputer for calculating the operation of the above-mentioned neuron and realizing an operation imitating a neural network by connecting the complexity by data communication. Neurocomputer S
It is configured as an information processing system 400 using an IMD type parallel computer. Reference numeral 600 denotes a host computer for operating the SIMD type parallel computer. Information processing system 400
Includes a control device 500 and a plurality (m) of semiconductor devices 100 having the same structure. An interconnection network connecting these devices includes an instruction external common bus 401,
It comprises an input data external common bus 402 and an output data external common bus 403. The system 400 includes a processor address bus 404 connected to the controller 500,
The semiconductor device further includes a semiconductor device address decoder 407 connected to the bus and all the semiconductor devices 100.

As shown in FIG. 2, each semiconductor device 100
Includes a plurality (n) of processors 200 having the same structure, each including a single LSI. The interconnection network connecting them includes an instruction internal common bus 110, an output data internal common bus 118 and an input data internal common bus 119.
And Each semiconductor device 100 includes an instruction decoder 10
9, maximum value minimum value processor detection circuit 350, processor selection circuit 300, format conversion circuit 102,
3 and the like are further provided.

As shown in FIG. 3, each processor 20
Numeral 0 has a local memory for storing the weight value and the like, an arithmetic unit, and the like, and simulates the operation of one neuron. An instruction that defines an operation procedure typified by the sigmoid function is taken into the semiconductor device 100 via the instruction external common bus 401, and given to the processor 200 via the instruction decoder 109 and the instruction internal common bus 110.
Inputs to the individual processors 200 are provided via input data internal common bus 119. The input data to the input data internal common bus 119 can be given from the input data external common bus 402 outside the semiconductor device 100. Commands and input data are performed by broadcast transfer. That is, all processors 20
0 and an instruction and input data are given in parallel. Note that it does not prevent the input data from being given to only a group of processors selected from the processor 200. Any one of the outputs of the processor 200 is selected and supplied to the output data internal common bus 118. The data provided to the output data internal common bus 118 can be output to an output data external common bus 403 outside the semiconductor device 100. By outputting the output data to the input data external common bus 402 by the control device 500, the data can be broadcast-transferred again to all the processors 200 in all the semiconductor devices 100 and operated again. Further, the operation of broadcasting the input data such that the operation result of one processor is selected and output to the output data internal common bus 118 and the operation of selecting the operation result by the one processor for the transferred input data are performed. By repeating the click, it is possible to perform the operation of the neural network that imitates the desired connection of the neurons.

At this time, the weight value in each processor 200 is initialized by the control device 500 in advance. The operation result obtained from the specific processor by the above series of operations is compared with, for example, an expected value, and the operation content of the processor 200 which performs learning by correcting the weight value of the processor so as to cancel the error is selected. The learning method is determined by a program stored in the control device 500, for example. Input data external common bus 402
Each processor 20 of the semiconductor device 100
The data that is broadcast-transferred to 0 is, for example, data downloaded from the host computer 600 to the control device 500 in advance.

The neuro-algorithm calculated by the neuro-computer is not limited to the above-mentioned neuron engineering model, but may be a self-organizing model or an LVQ.
Algorithms are also possible. The self-organizing model realizes a self-organizing function of the brain of a living body. The processor as a neuron is meant to be logically arranged in, for example, a two-dimensional lattice, and the weight value of each neuron is used as a reference vector. An input pattern is externally provided as a feature vector, and all neurons calculate distances (Euclidean distances) from reference vectors possessed individually. For the neuron having the minimum distance (or including the neuron arranged in the vicinity), the reference vector is updated so that the reference vector is further closer to the feature vector (the distance is reduced). By repeating this procedure for the number of types of input patterns to be characterized, it can be said that the features included in the input pattern group can be obtained as a feature map in the arrangement of the neuron group in a self-organizing manner. That is, the pattern of the output (small distance) of all the processors with respect to the input of the arbitrary input pattern is expressed as a feature of the input pattern, positioned in the logical arrangement of the processors.

In the neurocomputer of FIG. 4, each element of the input pattern is broadcast from the control device 500 to all the processors of the semiconductor device 100 in a time division manner via the input data external common bus 402. Each processor sequentially calculates the square of the difference between each element of the reference vector in the weight value memory and each element, and cumulatively adds the number of dimensions of the vector. Then, all the processors calculate the square root of the cumulative addition result in parallel, and generate result data as a distance between the reference vector and the feature vector of each processor. The control device 500 specifies the processor that has generated the result data as the minimum distance from all the processors,
An instruction to update the reference vector so that only the processor (or the processor including the processor arranged in the vicinity thereof) further brings the reference vector closer to the feature vector (reduces the distance) is issued via an instruction external common bus. Give. By repeating the above series of operations cyclically, calculation for realizing the feature map of the self-organizing model is performed.

In this embodiment, the maximum value / minimum value processor detection circuit 350 detects the minimum value (minimum value in the apparatus) and the maximum value (minimum value in the apparatus) of the plurality of result data generated by all the processors in the semiconductor device 100. It is characterized in that the in-apparatus minimum value processor and the in-apparatus maximum value processor which respectively generate the in-apparatus maximum value) are detected. Since this detection is performed on all the semiconductor devices 100 in parallel,
Runs fast.

Specifically, this detection is performed as follows. The control device 500 transmits the result data generated by each of the processors sequentially to a plurality of processors in each semiconductor device 100 to another processor in the same semiconductor device by using the output data internal common bus 118, the selector 111, and the input data internal common bus 119. Broadcast through. Each processor has an arithmetic unit for comparing the result data generated by itself with the broadcasted result data, and outputs a comparison result signal output from the arithmetic unit to a maximum value minimum value processor detection signal in each semiconductor device 100. The signal is sent to the circuit 350. The comparison result signal is, for example, a non-minimum value signal in which the former is significant (in other words, the self is not the minimum value), and a non-minimum signal in which the former is small (in other words, the self is not the maximum value). Consists of a non-maximum signal. The maximum value / minimum value processor detection circuit 350 determines whether each processor in the semiconductor device is the maximum value processor (internal device maximum value processor) or the minimum value processor (internal device) based on a plurality of comparison result signals supplied from each processor. (Minimum value processor).

After the maximum value processor and the minimum value processor in each semiconductor device are detected in this manner, the maximum value (system maximum value) of all the result data generated by all processors in the information processing system 400. , The minimum value (system minimum value) and the processor that generated each (system maximum value processor and system minimum value processor) can be detected, for example, as follows. The control device 500 includes a maximum value / minimum value detection circuit 608 (FIG. 6). For example, when detecting the system minimum and the processor that generated it, the controller 500
The comparison target data generated by the in-device minimum value processor detected by the maximum value / minimum value processor detection circuit 350 in all the semiconductor devices 100 is transmitted to the control device 500 via the output data external common bus 403. The maximum / minimum value detection circuit 608 in the control device 500 sequentially compares these comparison target data to determine the system minimum value and the semiconductor device 100 that has generated the minimum value. Address information (hereinafter, referred to as processor address) is assigned to each processor in advance on a one-to-one basis. The control device 500 selects the determined semiconductor device 100 and sends the processor address of the maximum value processor in the device to the selected semiconductor device 100.
0, and the system minimum value processor can be identified by the processor address sent from the semiconductor device. The same applies when determining the system maximum value and the system maximum value processor that generated it.

Also, the semiconductor device 100 can efficiently convert between the data formats even if the operation of the neural network by the neurocomputer of FIG. Considered to be possible.
In FIG. 2, as one example, the output of one processor is
The format can be converted by the format conversion circuit 102 or 103 via the output data internal common bus 118 and returned to the processor via the input data internal common bus 119. Also, externally supplied data is transmitted to the processor 2 via the format conversion circuit 102.
00 can be given. Further, the output of one processor can be output to the outside via the format conversion circuit 103. The neurocomputer of FIG.
The above conversion can be performed in parallel by the semiconductor device 100. In addition, the semiconductor device 100 can be provided with data in a fixed-point format for calculations in a floating-point format. Further, data in the floating-point format of the semiconductor device 100 can be extracted as data in the fixed-point format.

The details of the information processing system 400 will be described below.

(2) Control Device 500 As shown in FIG. 5, the control device 500 includes a control storage device 513, a data storage device 514, a program execution control circuit 515, and a host interface control circuit 516. The control storage device 513 is configured by a rewritable memory such as a RAM, and stores a program indicating an operation performed using the plurality of semiconductor devices 100 and a control procedure of the control device 500 necessary for the operation. The data storage device 514 is also formed of a rewritable memory such as a RAM, and stores data used in a program. The program execution control is performed by the program execution control circuit 5
15. The host interface control circuit 516 communicates with the information processing system 400 via a terminal 517.
And an interface for performing communication between the host computer 600. Program execution control circuit 515
Are commonly connected to all the semiconductor devices 100 by an instruction external common bus 401, an input data external common bus 402, and an output data external common bus 403. The program execution control circuit 515 further includes a processor address bus 404
Is connected to the semiconductor device address decoder 407 (FIG. 1).

The host computer 600 is a user interface unit that performs settings of the information processing system 400 and issues execution commands in response to user operations. The setting of the microprogram, the setting of the operation data, the execution of the program, and the retrieval of the result data in the control device 500 are performed in response to a user operation.
The user's operation is executed by the host computer 6 as commands.
00 is issued to the host interface control circuit 516 and executed by the program execution control circuit 515. For example, when the user's operation is an environment setting operation, the host computer 600 issues an environment setting command to the program execution control circuit 515 through communication with the host interface control circuit 516. Program execution control circuit 51
In response to this command, the control device 500 transfers the program translated into, for example, a machine language to the control storage device 513 and the arithmetic data and the initial value data of variables to the data storage device 514, respectively. Control. For example, when the user's operation is an execution start operation, the host computer 600 issues an execution start command to the program execution control circuit 515 through communication with the host interface control circuit 516. In response to the command, the program execution control circuit 515 controls the entire information processing system 400 so as to sequentially start execution according to the program stored in the control storage device 513. In the present embodiment, a program for a neurocomputer is used.

FIG. 6 shows a schematic internal block of the program execution control circuit 515. In the figure, a command execution control circuit 601 controls the entire program execution control circuit 515 and executes a command received from the host computer 600 via the host interface control circuit 516. The command execution control circuit 601 includes a sequencer circuit 604, a data storage device control circuit 605, a bus control circuit 606, an address control circuit 607, and a maximum value minimum value detection circuit 60
8 can be controlled. The sequencer circuit 604 has a program counter (PC) as a parameter register therein, and the command execution control circuit 60
In response to the execution request from the instruction 1, the instruction of reading the microinstruction is instructed to the instruction fetch circuit 602, and at the same time, its program counter is incremented to prepare for the reading of the next microinstruction. The instruction fetch circuit 602
One microinstruction of the microprogram indicated by the program counter is sent from the control storage device 513 to the signal 6.
14 and output to the instruction decode circuit 603. Also, the instruction fetch circuit 602 controls the command execution control circuit 601 to read a microinstruction from the control storage device 513, instead of reading the microinstruction supplied from the command execution control circuit 601 via the signal 613, as an instruction fetched. Instruction decode circuit 603
Can also be supplied.

(3) Microinstructions Microinstructions suitable for use in the present embodiment are horizontal microinstructions. It can also be called a micro instruction of the VLIW system. Here, the VLIW method means a method using an instruction format which is much longer than a normal method, such as 64-256 bits, which is employed in a microprocessor architecture for executing a plurality of processes in parallel. The instruction is composed of a plurality of fields. One example of the format is shown in FIG. The invention is not limited to micro-instructions in this format. Each of the fields 702 to 706 is not used only for control of a specific hardware, but can be used by switching to control of a different hardware. In the present embodiment, each micro-instruction is basically executed in one machine cycle, similarly to a normal micro-instruction control device. A series of processes for the same data is executed sequentially,
Also, a plurality of microinstructions are executed by so-called pipeline control in which the series of processes is executed in parallel with the same series of processes for other data. Each field or each of a plurality of subfields described later included therein may be referred to as an instruction.

A field 701 is a self control field for changing the meaning of the fields 702 to 706. The instruction decode circuit 603 interprets other fields according to the contents of the field 701.

A field 702 is an execution flow control field for controlling the sequencer circuit 604. The instruction decode circuit 603 controls the sequencer circuit 604 to execute a jump instruction, a conditional branch instruction, an execution end instruction, and the like according to the contents of the field. In the case of a jump instruction, the sequencer circuit 604 sets the contents of the program counter as the jump destination under the control of the instruction decode circuit 603. At this time, if it is necessary to restore the program counter, such as a subroutine call instruction, the information necessary for the restoration is saved in the stacker. If the instruction is a restoration instruction, the saved information is restored from the stacker. In the case of an execution end instruction or an illegal instruction, the instruction decode circuit 603 generates an interrupt signal in the command execution control circuit 601 and notifies the host computer 600 via the host interface control circuit 516.

A field 703 is an operation control field, and is an arithmetic unit in each processor in each semiconductor device 100 or a processor selection circuit 3 in each semiconductor device 100.
00 is a field for controlling circuits in each semiconductor device 100 such as the maximum value minimum value processor detection circuit 350 and the like.
This field includes a plurality of subfields for specifying a plurality of operations or operations. Instruction decode circuit 6
03 cuts out the field, and the instruction external common bus 4
Output to 01. Each of the subfields in the cut-out field 703 is sometimes referred to as an operation instruction since each processor mainly processes the operation instruction as an operation instruction designating a plurality of operations. When the subfield is inside the semiconductor device 100 such as the processor selection circuit 300 but controls the operation of a circuit outside the processor 200, the subfield may be called an operation instruction. Also, the specific operation specified by each subfield,
For example, with reference to a comparison operation, the subfield may be called, for example, a comparison operation instruction. When a plurality of fields or subfields in the same microinstruction are supplied to each semiconductor device 100, all of those bits are supplied in parallel by the instruction external common bus 401.

A field 704 is an output data control field for controlling data output to the output data external common bus 403. The instruction decode circuit 603 outputs the field to the instruction external common bus 401. Since this field is processed as an instruction to instruct each semiconductor device 100 to output data, the field is hereinafter also referred to as a data output instruction instruction. This data output instruction includes
It also includes an instruction for instructing any of various data conversions described below. The instruction decode circuit 603 further generates a signal for controlling the address control circuit 607 according to the contents of the field as follows. Address control circuit 6
Reference numeral 07 includes a processor address pointer (not shown) as a parameter register and a control circuit (not shown) for the processor address pointer. , Increments, decrements, or sets data on the control device internal bus 609, and outputs the contents of the processor address pointer to the processor address bus 404. This processor address is used to output data to the output data external common bus 403.
Is specified.

A field 705 is a data control field, and controls a data storage device control circuit 605 (FIG. 6) for accessing the data storage device 514 (FIG. 5). The instruction decode circuit 603 controls the data storage device control circuit 605 according to the contents of the field to execute the following operation. The data storage device control circuit 605 includes:
It includes a data storage device address pointer (not shown) as a parameter register and a control circuit (not shown) for the data storage device address pointer, and the data storage device address pointer is incremented, Decrement or setting of data on the control device internal bus 609 is performed. Further, based on the address in the data storage device indicated by the data storage device address pointer under the control of the instruction decode circuit 603, data is read from the data storage device 514 to the bus 614, or the data on the bus 611 is transferred to the data storage device 514. Write. The data read on the bus 612 is transferred to the control device internal bus 609 via the bus control circuit 606 or the input data is transferred to the external common bus 402 and broadcast to each semiconductor device 100. Bus 611 to be written to data storage device 514
The above data is transferred from the control device internal bus 609 via the bus control circuit 606 or from one of the semiconductor devices 100 via the input data external common bus 402.

A field 706 is a data bus control field, and the instruction decode circuit 603 controls the bus control circuit 206 according to the contents of the field. The bus control circuit 206 includes an input data external common bus 402, an output data external common bus 403, and a data storage device 514.
Is a circuit for controlling connection between the input / output buses 611 and 612 and the control device internal bus 609. FIG. 8 shows an internal block of the bus control circuit 206. In the figure,
The selectors 820 to 822 perform the following operations according to the control signal 610 from the instruction decode circuit 603. The selector 820 selects data on the output data external common bus 403 or data on the output bus 612 of the data storage device 514 and transfers the data to the input data external common bus 402 via the latch circuit 830. The selector 821 selects data on the output data external common bus 403 or data on the control device internal bus 609 and transfers the data to the input bus 611 to the data storage device 514 via the latch circuit 831. The selector 822 outputs the output data external common bus 40 according to the control signal 610 from the instruction decode circuit 603.
3 or output bus 6 of data storage device 514
12 via a latch circuit 832 and a tri-state buffer 834 to control device internal bus 609.
Output to

Therefore, the data read from the data storage device 514 onto the bus 612 can be broadcast to all the semiconductor devices 100 via the output data external common bus 403 by the selector 820. Further, the selector 820 can send data output from the specific semiconductor device 100 to the output data external common bus 403 to the input data external common bus 402 and broadcast the data to all the semiconductor devices 100. .
Further, the final operation result data intended by the system, which is generated by any one of the processors 200 in any one of the semiconductor devices 100 and sent to the output data external common bus 403, is transmitted via the bus 611 by the selector 821. And stored in the data storage device 514.

(4) Semiconductor Device Returning to FIG. 2, in each semiconductor device 100, the instruction decoder 1
09 decodes each of a plurality of instructions supplied in parallel to the instruction input terminal 105 from the control device 500 via the instruction external common bus 401, and, among those instructions, a plurality of instructions to be processed by the processor 200. And a plurality of processors 200 via the instruction internal common bus 110.
Broadcast to. Among a plurality of instructions supplied to the instruction decoder 109, a circuit external to the processor 200 included in the semiconductor device 100, for example, selectors 111 and 11
2, 113, or an instruction that requires the operation of the processor selection circuit 300 and the maximum / minimum processor detection circuit 350 is included, the instruction decoder 109 outputs a plurality of control signals to the circuit (hereinafter also referred to as an instruction (Which may be referred to as) and supplies it to the circuit via signal 109A.

The data output terminal of each processor is connected to the output data internal common bus 118 via the corresponding tri-state buffer 121. The output of the maximum value minimum value processor detection circuit 350 is also connected to the output data internal common bus 118 via the tristate buffer 115. The maximum value minimum value processor detection circuit 350
Signal 21 from all processors 200 in semiconductor device 100
The maximum value processor and the minimum value processor which respectively generate the maximum comparison target data and the minimum comparison result data are identified by a plurality of comparison result signals repeatedly supplied via the control unit 2 and the addresses of the respective processors are generated. The maximum value minimum value processor detection circuit 350 supplies these addresses to the processor selection circuit 300. The processor selection circuit 300 can output these generated addresses to the output data internal common bus 118 via the tri-state buffer 115.

The processor selection circuit 300 is a circuit for selecting a processor to output data to the output data internal common bus 118. The processor address used for selection is supplied from the control device 500 to the processor address bus 404, the processor address input terminal 108, the signal 11
4 or an address supplied from the maximum value / minimum value processor detection circuit 350.

The selector 111 selects input data supplied to the external data input terminal 104 from the control device 500 via the input data external common bus 402 or data on the output data internal common bus 118, and selects the selector 112 and format conversion. Output to the circuit 102. The selector 112 selects the output data of the selector 111, the output data of the format conversion circuit 102 or the output data of the format conversion circuit 103, and outputs it to the input data internal common bus 119. Therefore, the selector 111,
112, not only the input data supplied from the external data common bus 402 but also any of the processors 2
The data output by 00 is also broadcast to all processors 200.

The selector 113 controls the data on the output data internal common bus 118 or the format conversion circuit 103.
Output data of the tristate buffer 120
Output to When a semiconductor device selection signal applied from outside the semiconductor device via the semiconductor device selection signal input terminal 107 to the semiconductor device address decoder 407 is asserted, the tri-state buffer 120 selects the selector 1
13 outputs the output data to the output data external common bus 403 via the external data output terminal 106. Therefore, the data output from each processor to the output data internal common bus 118 is also the maximum value minimum value processor detection circuit 35.
The processor address output from 0 is also the selector 11
3. The data can be transferred to the control device 500 via the tri-state buffer 120 and the output data external common bus 403.

Although omitted from the drawing, the semiconductor device 10
Each of the 0 terminals 104 to 108 is provided with a latch circuit for inputting or outputting data in synchronization with the timing of an external signal connected to each terminal.
In addition, a clock signal for synchronously operating circuits inside the semiconductor device 100 is supplied from an external terminal.
Although omitted from the drawing, a line for transmitting a control signal from the instruction decoder 109 to the selector 113 and a line for supplying a semiconductor device selection signal from the semiconductor device selection signal input terminal 107 to the tristate buffer 120 are synchronized with this clock signal. And a two-stage latch circuit, which operates as a selector 113 and a tri-state buffer 12.
The operation timing of 0 is adjusted to the timing at which the processor 200 outputs data.

(5) Processor Referring to FIG. 3, an instruction decoder 209 in each processor 200 includes a semiconductor device 10 including the processor.
A plurality of controls for decoding a plurality of instructions input in parallel from the instruction input terminal 207 from the decoder 109 in the instruction processor 0 via the instruction internal common bus 110 and supplying the decoded instructions to a plurality of circuits related to the respective instructions in the processor 200 Generate signals in parallel (hereafter also called instructions),
The signals are supplied in parallel to these circuits via a signal 209A.
Each processor 200 has a computing unit necessary to imitate the operation of one neuron. Here, the arithmetic unit includes a multiplier 202 and an arithmetic and logic unit (ALU) 201 which performs four arithmetic operations, simple logical operations, shift operations, and the like. The memory 203 is a local memory of the processor 200, and is here called a weight value memory because it mainly holds a weight value required for a calculation that imitates the operation of a neuron. The weight memory 203 is composed of a rewritable memory such as a RAM. The weight value is initialized by the control device 500 in advance. The weight value memory 203 reads data from the address specified by the instruction in accordance with the instruction, or stores the data in the multiplier 202 or the ALU 20.
1 can be written. The data read from the weight value memory 203 is used by the ALU 201, the multiplier 202 or the selector 217 described later via the bus 230. The read address is specified by a weight value memory read instruction. The register file 204 includes a plurality of registers.
1 or used to store the operation result data by the multiplier 202, and the data held therein is used by the ALU 201 or the multiplier 202 or the selector 217 via the bus 230. A register for reading data from or writing data to the register file 204 is specified by an instruction. In addition,
The register file 204 writes to the register of the first address among the three addresses specified by a plurality of instructions at the same time, reads from the registers of the second and third addresses, and furthermore, Writing can be performed in parallel. The data input terminal 20 via the input data internal common bus 119 of the semiconductor device 100
5 is supplied to the multiplier 202 or the ALU 201 via the bus 230.

Either the input data, the data read out from the register file 204 according to the instruction or the multiplication result data generated by the multiplier 202 is supplied to the multiplier 202 as first data. Either the data read from the memory 204 according to the instruction or the data read from the weight value memory 203 according to the instruction is supplied as the second data.
The multiplier 202 performs multiplication in a floating-point format or multiplication in a fixed-point format on the first and second data in accordance with an instruction.

The ALU 201 receives either the input data, the data read from the register file 204 according to the instruction, or the output data of the multiplier 202 as the first data.
And the register file 20
4, data read according to the instruction, data read from the weight value memory 203 according to the instruction, or A
One of the output data of the LU 201 is supplied as the second data. The ALU 201 performs arithmetic addition and subtraction in a floating-point format, arithmetic addition and subtraction in a fixed-point format, a logical operation or a shift operation on these first and second data in accordance with instructions.

The output data of the multiplier 202 or the ALU 201 is written to the register file 204 via the signal 232 in accordance with the instruction. Note that this writing may not be performed. Similarly, the output data of the multiplier 202 or the ALU 201 is written into the weight memory 203 via the signal 231 according to the instruction. Note that this writing may not be performed. The operation result data of the ALU 201 is transferred to the bus 23 via the latch circuit 221.
0, and similarly, the operation result data of the multiplier 202 is also supplied to the bus 230 via the latch circuit 222.

All processors 20 in all semiconductor devices 100
“0” receives a set of commands, which is broadcast from the control device 500 and includes a plurality of commands, and executes the plurality of commands in parallel. A plurality of sets of instructions sequentially broadcast from the control device 500 are similarly executed. In this way, all processors in the system execute the same processing using different weight values, and store the result data in the register file 204 or the weight value memory 2.
03.

Data transfer from each processor 200 to the outside is performed as follows. The data to be sent to the outside is read out from the register file 204 or the weight value memory 203 according to the instruction and supplied to the selector 217 via the bus 230. The selector 217 selects this data in accordance with the data output instruction and outputs the selected data via the data output terminal 206 to the output data internal common bus 11.
8

Although omitted from the drawing, in FIG.
The instruction decoder 209 prohibits rewriting of various memories (register file 204 and weight value memory 203) in the processor 200 in accordance with the comparison target flag 220 by an instruction. Processor 2
00, a processor execution selection signal is input via a terminal of the processor 200, and various memories (register file 204 and weight value memory 2
03) is prohibited. Thus, it becomes possible to select a processor that executes an instruction broadcast to all processors via the instruction internal common bus 110 in FIG. In FIG. 2, the processor execution selection signal is a processor address signal 114 input via the processor address input terminal 108 when the semiconductor device selection signal input via the semiconductor device selection signal input terminal 107 is asserted. The one corresponding to the processor pointed to is generated to be asserted. Also, terminals 205 to 20 of the processor
Reference numeral 8 includes a latch circuit (not shown), which is used to input or output data in synchronization with the timing of an external signal connected to each.

(6) Device Operation Hereinafter, details of circuits and operations related to detection of a processor that has generated the maximum or minimum result data in the information processing system 400 will be described. In the present embodiment, for this detection, first, the maximum value processor or the minimum value processor in the device which has generated the maximum or minimum result data in each semiconductor device 100 is detected. After that, the control device 500 compares the maximum value or the minimum value detected by each semiconductor device 100, and detects the processor that has generated the system maximum value or the system minimum value.

(6a) Detection of maximum value / minimum value in device First, a device related to detection of a maximum value processor or a minimum value processor in each semiconductor device 100 (hereinafter, referred to as detection of a maximum value / minimum value processor in the device). And the operation (hereinafter, referred to as a first operation) will be described in detail. In the detection of the maximum value / minimum value processor in the device, comparison target data is read from one processor in each semiconductor device 100 and broadcast to all processors 200 in the semiconductor device 100.
This comparison target data is data generated as a result of a series of processes in each processor. Each processor compares the comparison target data held by itself with the broadcast comparison target data. Each processor notifies the maximum / minimum value processor detection circuit 350 of the comparison result signal.
This operation is repeated while sequentially changing the processor from which the comparison target data is to be read. The maximum value / minimum value processor detection circuit 350 determines the maximum value processor in the device and the minimum value processor in the device based on a plurality of comparison result signals generated by each processor 200 in the semiconductor device 100 by this repetition. The above operations are executed in parallel by all the semiconductor devices 100. Here, it is assumed that the comparison target data of each processor is stored in the same location in the register file 204 or the weight memory 203 regardless of the processor and is data expressed in a floating-point format. It is also assumed that all processors 200 in all semiconductor devices 100 are processors to be compared. The operation of the device when any of the processors is not the processor to be compared will be described later.

(6a-1) Comparable Data Output Instruction First, referring to FIG. 1, the control device 500 sends the comparison target data output instruction to the Broadcasts information on data storage locations. This information includes information specifying one of the register file 204 and the weight value memory 203,
It contains the number of the register to be read in the register file 204 or the data read address of the weight memory 203. The control device 500 simultaneously gives a processor address including an in-device processor address for one processor from which the comparison target data is to be read out via the processor address bus 404 and broadcasts it to all the semiconductor devices 100. The upper bits of the processor address are a semiconductor device address for identifying the plurality of semiconductor devices 100, and the lower bits of the processor address are an in-device processor number for identifying a plurality of processors in the semiconductor device 100. In this case, the semiconductor device address among the supplied processor addresses is
Not used within 0. The instruction external common bus 401
The instruction is supplied to the processor 500 by the instruction decode circuit 603 (FIG. 6) in the control device 500. The processor address is supplied to the processor address bus 404 by the control device 5.
This is performed by the address control circuit 607 in FIG. This is the same in other operations.

Referring to FIG. 2, instruction decoder 109 in each semiconductor device 100 decodes the comparison target data output instruction, and outputs the comparison target data output instruction and the information on the storage location of the comparison target data. Internal common bus 11
0 through all the processors 20 in the semiconductor device 100.
Broadcast to 0. Further, when the instruction decoder 109 decodes the comparison target data output instruction, the instruction decoder 109 is designated by the processor address in the device supplied to the processor selection circuit 300 from the control device 500 via the processor address bus 404 and the signal 114. An instruction for outputting data from the processor to the output data internal common bus 118 is generated and output to the processor selection circuit 300. The processor address in the device among the processor addresses given to the processor address input terminal 108 is supplied to the processor selection circuit 300 via a signal 114.

Referring to FIG. 3, an instruction decoder 209 in each processor 200 decodes the instruction and selects the register file 204 or the weight value memory 203 based on the information on the storage location of the data to be compared. When selected, the register file 204 or the weight value memory 203 reads the comparison target data specified by the information, and supplies the comparison target data to the selector 217. In this case, it is assumed that all processors 200 are comparison processors. In this case, as described later, the comparison target flag register 220 (hereinafter, the comparison target flag held in this register may also be referred to as the comparison target flag 220).
Is set in any of the processors 200.
At this time, the selector selects the read comparison target data and outputs it via the data output terminal 206 to the tri-state buffer 121 (FIG. 2) corresponding to the processor.

Referring to FIG. 4, the processor selection circuit 3
00 includes selectors 305 and 306 and a processor selection signal generation circuit 307. Processor selection circuit 300
Operates in synchronization with a clock signal in the semiconductor device 100, and is connected to an input unit (not shown) of an instruction supplied from the decoder 109 (FIG. 2) so that the timing of execution with the processor 200 is adjusted. Is provided with a one-stage latch circuit (not shown). This is the same for the maximum value minimum value processor detection circuit 350. The latch circuits 320, 321, 322, 323 described in FIG.
324 operates in synchronization with the clock signal in the semiconductor device 100, and
It is provided to adjust the timing of execution with 0.

As will be described later, the selector 305 selects one of the address of the internal maximum processor and the address of the internal minimum processor supplied from the maximum / minimum processor detection circuit 350. The selector 306 receives the processor address in the device supplied from the control device 500 via the processor address input terminal 108 and the signal 114 and the output address of the selector 305. In this case, in response to the instruction, the selector 306 outputs the output data internal common bus 1 from the processor specified by the in-device processor address supplied via the signal 114 supplied from the instruction decoder 109.
In order to output data to 18, the internal processor address on signal 114 is selected. Further, the processor selection signal generation circuit 307 includes an in-device processor address output from the selector 306 and zero detection circuits 308, 3
09 is input. The processor selection signal generation circuit 307 outputs a processor selection signal to be supplied to the processor indicated by the processor address in the device from the selector 306 to the signal 122 in response to the instruction supplied from the instruction decoder 109, or outputs the signal Or 3
18 is a circuit for generating a signal to be described later to be supplied to. When generating the processor selection signal, the processor selection signal generation circuit 307 outputs the processor corresponding to the processor at the timing when the processor indicated by the processor address in the device from the selector 306 outputs the comparison target data to the tristate buffer 121 corresponding to the processor. It asserts the select signal and operates to supply it to its tri-state buffer 121 via signal 122. In this case, the processor selection signal generation circuit 3
07 asserts a processor selection signal for the processor specified by the internal processor address supplied from the signal 114. Thus, the comparison target data read from the processor specified by the in-device processor address supplied by the control device 500 is transferred to the output data internal common bus 118.

(6a-2) Data Comparison Operation Instruction Next, referring to FIG. 1, the control device 500 reads out all the semiconductor devices 100 onto the output data internal common bus 118 in each semiconductor device 100. Broadcasting a floating-point data comparison operation command for comparing the comparison target data with the comparison target data in each processor in each semiconductor device 100.

Referring to FIG. 2, instruction decoder 109 in each semiconductor device 100 decodes the instruction, generates an instruction for selecting output data internal common bus 118, and outputs a signal to selector 111 (FIG. 2). An instruction is supplied through the signal 109A to select the output of the selector 111, and is supplied to the selector 112 (FIG. 2) via the signal 109A. The selector 111 (FIG. 2)
In response to the above-mentioned command supplied from No. 9, the comparison target data read onto the output data internal common bus 118 is selected. The selector 112 selects the comparison target data output from the selector 111 in response to the instruction supplied from the instruction decoder 109, and supplies the selected data to the input data internal common bus 119. Thus, the comparison target data read from the selected processor is broadcast to all the processors 200 in the semiconductor device 100 via the output data internal common bus 118, the selectors 111 and 112, and the input data internal common bus 119. The instruction decoder 109 further broadcasts a floating-point data comparison operation instruction for the data on the input data internal common bus 119 and the data to be compared in the processor to all the processors 200 via the instruction internal common bus 110.

Referring to FIG. 3, in each processor 200, comparison target data read from any of the processors is input to data input terminal 205, and instruction decoder 209 decodes the floating-point data comparison operation instruction. . Under the control of the instruction decoder 209, the bus 230 supplies the comparison target data to the ALU 201 as first data, and the weight value memory 203 or the register file 204 reads out the comparison target data specified previously,
The bus 230 sends the comparison target data to the ALU 201 as a second
The ALU 201 performs a comparison operation on the two comparison target data.

When the ALU 201 subtracts the second data (B) from the first data (A) supplied thereto in accordance with the comparison operation instruction, the non-minimum signal asserted when the operation result becomes a positive number A comparison result signal composed of a pair of a value signal 215 and a non-maximum value signal 216 that is asserted when the operation result becomes a negative number is output. In this case, the non-minimum value signal 215 is asserted when the comparison target data read from any processor is larger than the comparison target data in the own processor. Therefore, when this signal is asserted, its own comparison target data is not the minimum in the same semiconductor device 100. Conversely, when this signal is not asserted, the data to be compared by itself may be minimized in the same semiconductor device 100. In this case, the non-maximum value signal 216 is asserted when the comparison target data in the own processor is smaller than the comparison target data read from any of the processors. Therefore, when this signal is asserted, the data to be compared is:
It is not the maximum in the same semiconductor device 100. Conversely, when this signal is not asserted, the data to be compared is likely to be maximum in the same semiconductor device 100. It is to be noted that the data to be compared is first output from the output data internal common bus 1 by the data to be compared output instruction.
Since the input comparison target data and its own comparison target data are equal to each other, the non-minimum value signal 21
5, both the non-maximum signal 216 are not asserted.

The selectors 210 and 211 select the signals 215 and 216 according to the comparison operation command, respectively.
The processor 200 is output via a comparison result information output terminal 208 and signals 212a and 212b included in the signal 212.
Is supplied to the maximum value / minimum value processor detection circuit 350 (FIG. 2) in the semiconductor device 100 in which

The comparison operation instructions executable by the ALU 201 include a floating-point data comparison operation instruction and an integer data comparison operation instruction. In the floating-point data comparison operation instruction, the first and second data are converted to floating-point data. The above-described subtraction is performed as data of a format. In the integer data comparison operation instruction, the above-described first and second data are performed as data of a fixed-point format (integer format). In the floating point data comparison operation, when at least one of the first and second data is non-numerical data, the non-maximum value signal 216 and the non-minimum value signal 2
15 is not asserted.

(6a-3) Maximum / Minimum Value Detection Instruction Next, referring to FIG. 1, the control device 500 issues a maximum / minimum value detection instruction to all the semiconductor devices 100 via the external common bus 401. I do. Referring to FIG. 2, instruction decoder 109 in each semiconductor device 100 decodes the instruction and outputs a maximum / minimum value detection instruction to maximum / minimum value processor detection circuit 350.

Referring to FIG. 4, the maximum value minimum value processor detection circuit 350 includes a maximum value flag register 301, a minimum value flag register 302, and two address generation circuits 3
03, 304, and two zero detection circuits 308, 309. The maximum value flag register 301 is provided in the semiconductor device 100
, Each storage area is associated one-to-one with one processor, connected to the corresponding processor 200 via signal 212b, and outputs the non-maximum value output by that processor. Signal 216 is provided there. Each storage area stores a maximum value flag for the corresponding processor. This maximum value flag is 1
When set to indicates that the corresponding processor is likely to be the maximum processor. The minimum value flag register 302 has a minimum value flag storage area equal to the number of processors in the semiconductor device 100, and each minimum value flag storage area is associated with one processor on a one-to-one basis. Corresponding processor 2
00 and the non-minimum signal 215 output by the processor is provided there. Each storage area stores a minimum value flag for the corresponding processor. When the minimum value flag is set to 1, it indicates that the corresponding processor is likely to be the minimum value processor.

As described later, each flag in the maximum value flag register 301 and the minimum value flag register 302 is set to 1 when the corresponding processor is the processor to be compared at the time of initialization, and is set to 0 otherwise.
Is reset to In this case, since all processors are assumed to be compared, all flags of these registers are set to 1 at the time of initialization. In other words, it indicates that all processors may be maximum value processors.

The maximum value flag register 301 receives a signal 212 from each processor in response to the maximum value minimum value detection instruction.
When the non-maximum value signal input via the processor is 0, the maximum value flag corresponding to the processor is held as it is,
When the non-maximum value signal is 1, the flag is reset (in other words, 0 is output). Therefore,
It indicates that the processor is not a maximum processor. When the non-maximum value signal for any of the processors is set to 1 by the maximum value / minimum value detection instruction and the corresponding maximum value flag is reset once, the maximum value / minimum value detection instruction is executed again, and the non-maximum value signal is output. Even if it becomes 0, the flag is not set again. Thus, if the processor is found not to be a maximum processor, the corresponding maximum flag will continue to indicate so. An associated circuit (not shown) in each storage area and the maximum value flag register 301 operates as a circuit for detecting whether the corresponding processor is the maximum value processor.

Similarly, the minimum value flag register 302 stores
When the non-minimum value signal input from each processor via the signal 212 is 0 in response to the maximum value / minimum value detection instruction, the minimum value flag corresponding to the processor is held as it is, and the non-minimum value signal is When it is 1, the flag is reset (in other words, 0 is output). This indicates that the processor is not a minimum processor. When the non-minimum value signal for any of the processors is set to 1 by the maximum value / minimum value detection instruction and the corresponding minimum value flag is reset once, the maximum / minimum value detection instruction is executed again thereafter, and the non-minimum value signal is output. Even if it becomes 0, the flag is not set again. Thus, if the processor is found not to be a minimum processor, the corresponding minimum flag will continue to indicate so. An associated circuit (not shown) in each storage area and the minimum value flag register 302 operates as a circuit for detecting whether or not the corresponding processor is the minimum value processor.

The output of the maximum value flag register 301 is connected to the address generation circuit 303. The address generation circuit 303 generates an in-device processor address of the processor 200 corresponding to the set maximum value flag in the maximum value flag register 301. If there are a plurality of maximum value flags set in the maximum value flag register 301, one of a plurality of in-device processor addresses assigned to the plurality of processors 200 corresponding to the plurality of maximum value flags is set. For example, the smallest in-device processor address is generated. Similarly, the output of the minimum value flag register 302 is connected to the address generation circuit 304. The address generation circuit 304 generates an in-device processor address of the processor 200 corresponding to the set minimum value flag in the minimum value flag register 302. When there are a plurality of minimum value flags set in the minimum value flag register 302, one of a plurality of processor addresses in the device assigned to the plurality of processors 200 corresponding to the plurality of minimum value flags. For example, the smallest in-device processor address is generated. Address generation circuits 303 and 30
The expression format of the address generated by the semiconductor device 10 is
0 is the same as the processor address signal 114 applied to the processor address input terminal 108 from outside.

The output of the maximum value flag register 301 is connected to the zero detection circuit 308. This circuit outputs 1 when all the maximum value flags in the maximum value flag register 301 are 0 (reset), When at least one of the maximum value flags is 1 (set), 0 is output. Similarly,
The output of the minimum value flag register 302 is connected to the zero detection circuit 309.
When all the minimum value flags in 02 are 0 (reset), 1 is output, and when at least one of the minimum value flags is 1 (set), 0 is output.

Thus, the execution of the maximum / minimum detection instruction is completed. Outputs of the address generation circuits 303 and 304 and the zero detection circuits 308 and 309 are output from the processor selection circuit 3
Used later by 00.

By the operation from the comparison target data output instruction to the maximum value / minimum value detection instruction, each semiconductor device 10
All the processors 200 in 0 execute the magnitude comparison between the comparison target data of one processor indicated by the processor address given at the same time as the comparison target data output instruction and its own comparison target data in parallel at the same time. Are reflected in the maximum value flag register 301 and the minimum value flag register 302.

In order to execute the above operation for all the processors 200 in each semiconductor device 100, the control device 500 executes a comparison target data output instruction, a floating-point data comparison operation instruction, and a maximum / minimum value detection instruction. Each semiconductor device 10
The broadcast is repeated a number of times equal to the number of all the processors 200 in 0. However, when repeatedly issuing the comparison target data output instruction, the control device 500 broadcasts the in-device processor addresses for sequentially different processors in each semiconductor device 100. As a result, all the processors 200 in each semiconductor device 100 compare the comparison data of the other processors with the comparison data of the own processor in the magnitude relation, and the comparison result in each processor is set to the maximum value flag register. 301 and the minimum value flag register 302. That is, the processor having the minimum value in each semiconductor device 100 is the minimum value flag register 3
The processor corresponding to the minimum value flag whose value of 02 is 1 (set state), and the processor having the maximum value is the maximum value of the value 1 (set state) in the maximum value flag register 301. The processor corresponding to the value flag. The in-device processor addresses of the in-device maximum value processor and the in-device minimum value processor are generated by address generation circuits 303 and 304, respectively. There may be more than one maximum processor in the device. At this time, as described above, the address generation circuit 303 generates an in-device processor address of one of the processors. The same applies to the in-device processor address generated by the address generation circuit 304 for the in-device minimum value processor.

The first operation is executed in parallel in all the semiconductor devices 100, and is executed in each semiconductor device 100 by pipeline processing. Therefore, all semiconductor devices 10
The number of processing steps required to execute the repetition the number of times equal to the number of processors 200 in 0 is equal to the number of processing steps required for magnitude comparison of one processor 200 and the number of processing steps equal to the number of processors 200 in the semiconductor device 100. Only the number of steps needs to be added.

Thus, the first operation of detecting the maximum value processor and the minimum value processor in each semiconductor device 100 is completed.

(6b) Detection of System Maximum Processor and System Minimum Processor Next, the control device 500 executes a second operation to detect the minimum processor or the maximum processor in the entire information processing system 400. I do. In this second operation,
The control device 500 causes the comparison data stored in the maximum value processor or the minimum value processor detected in all the semiconductor devices 100 to be transmitted from the respective semiconductor devices 100 to the control device 500, and the control device 500 stores the data therein. A certain maximum value / minimum value detection circuit 608 (FIG. 6) detects a system minimum value or a system maximum value and the semiconductor device 100 that has sent the system minimum value or system maximum value from the comparison target data. In the following, the operation of the apparatus when detecting the system minimum value is described, and when the system maximum value is detected,
The different operation parts are written in parentheses.

Referring to FIG. 1, control device 500 broadcasts a minimum value (or maximum value) data output instruction and information on a storage location of comparison target data to all semiconductor devices 100. The information on the storage location of the comparison target data is the same as the information specified earlier when the comparison target data output instruction was broadcast. At the same time, the control device 500 outputs a processor address having a semiconductor device address for one semiconductor device 100 to the processor address bus 404. The semiconductor device address decoder 407 asserts a semiconductor device selection signal for the semiconductor device 100 specified by the semiconductor device address, and supplies the signal to the semiconductor device 100 via a signal 408. Control device 500 further issues a data bus control instruction instructing that data on output data external common bus 403 be taken into control device internal bus 609 in program execution control circuit 515.
(FIG. 6), and further supplies a maximum value / minimum value detection instruction to a maximum value / minimum value detection circuit 608 (FIG. 6).

Referring to FIG. 2, in each semiconductor device 100, instruction decoder 109 decodes the above-mentioned minimum (or maximum) data output instruction, and outputs data to all processors 20.
For 0, a comparison target data output instruction and information on the storage location of the comparison target data are broadcast. Further, the processor selection circuit 300 outputs an instruction to output data from the processor having the minimum value (or the maximum value) to the output data internal common bus 118. Also, for the selector 113,
Output data An instruction to output data on the internal common bus 118 to the tri-state buffer 120 is issued.

Referring to FIG. 3, each processor 200
, The instruction decoder 209 decodes the instruction. The weight value memory 203 or the register file 204 reads out the comparison target data specified by the above information of the storage location of the comparison target data, and supplies the same to the selector 217 via the bus 230. The selector 217 determines that all processors are to be compared,
Since 20 is set to 1, the data is selected and output to the tri-state buffer 121 (FIG. 2) corresponding to the processor via the data output terminal 206.

Referring to FIG. 4, the processor selecting circuit 3
00 performs the following operation in response to the instruction generated by the instruction decoder 109 to output data from the processor having the minimum value (or maximum value) to the output data internal common bus 118.

The selector 305 includes an address generation circuit 3
The in-device processor address of the minimum value processor and the processor value of the maximum value processor output from the address generation circuit 303 are input.
In this case, the selector 305 includes the address generation circuit 304
Selects the in-device processor address of the minimum value processor (or the in-device processor address of the maximum value processor output by the address generation circuit 303). The selector 306 includes the output of the selector 305 and the control device 5.
An internal processor address supplied from 00 through a signal 114 is input. In this case, the selector 30
6 selects the address of the minimum value processor (or the address of the maximum value processor) selected by the selector 305 and supplies it to the processor selection signal generation circuit 307.

The processor selection signal generation circuit 307 includes:
The output of the selector 306 and the outputs of the zero detection circuits 308 and 309 in the maximum value minimum value processor detection circuit 350 are input. In this case, the maximum value flag register 301
Holds at least one maximum value flag of value 1. Therefore, the output of the zero detection circuit 309 is zero. The same applies to the minimum value flag register 302 and the zero detection circuit 308. The processor selection signal generation circuit 307 responds to the above instruction to
When the output of the processor 09 (or the zero detection circuit 308) is 0, the processor selection signal corresponding to the minimum processor (or the maximum processor) indicated by the processor address in the device supplied from the selector 306 is compared with the processor selection signal. Assert when data is output.

Referring to FIG. 1, this processor select signal is provided to its minimum value processor (or maximum value processor) via signal 122. As a result, the comparison target data output from the processor is transferred to the output data internal common bus 118. The selector 113
The data to be compared on the output data internal common bus 118 is output to the tri-state buffer 120. The semiconductor device selection signal asserted by the semiconductor device address decoder 407 (FIG. 2) is supplied to the semiconductor device selection signal input terminal 107 in the tri-state buffer 120 in one of the selected semiconductor devices 100. Supplied via Therefore, the comparison target data read to the output data internal common bus 118 in the one semiconductor device 100 is sent to the output data external common bus 403 via the external data output terminal 106, and further transmitted to the control device 500. Will be transferred. No data is sent from another semiconductor device 100 to the output data external common bus 403.

Referring to FIG. 6, bus control circuit 606
Responds to the data bus control instruction given from the instruction decode circuit 603 to output data external common bus 4.
03 is transferred to the control device internal bus 609. The maximum value minimum value detection circuit 608 is connected to the control device internal bus 609 and the address control circuit 607, and detects the maximum value and the minimum value of a plurality of comparison target data sequentially supplied to the control device internal bus 609. The address control circuit 607 controls the semiconductor device 100 to which the maximum value and the minimum value are supplied by the processor address bus 404.
Is a circuit for identifying based on the semiconductor device address supplied to the device. Specifically, the maximum value / minimum value detection circuit 608 includes:
In response to the maximum value / minimum value detection instruction given from the instruction decode circuit 603, the comparison target data transferred to the control device internal bus 609 is taken. Further, the address control circuit 607 takes in the semiconductor device address previously sent to the processor address bus 404. If there is already captured comparison data, it is compared with newly captured comparison data, and the larger comparison data and the smaller comparison data, and the semiconductor device corresponding to the semiconductor device 100 that has supplied the respective data. Store the address. If there is no comparison data already taken in, the semiconductor device address for the newly taken comparison data is stored.

As described above, the minimum comparison target data (or the maximum comparison target data) in one selected semiconductor device 100 is output to control device 500. Control device 5
00 repeats the above operation for different semiconductor devices 100. In this way, the maximum value minimum value detection circuit 608 can detect the maximum comparison target data in the system and the semiconductor device 100 including the processor that generated it. The detected system maximum value and the processor address of the system maximum value processor are stored in, for example, a data storage device (FIG. 5) in control device 500. The description of the instruction for the storage and the circuit operation is omitted.

Note that the second operation can be performed by pipeline processing, and the number of processing steps required to execute the number of times equal to the number of semiconductor devices 100 in the information processing system 400 is one semiconductor device 100 Only the number of processing steps equal to the number of all the semiconductor devices 100 in the information processing system 400 is added to the number of processing steps for reading the internal minimum value (or the internal maximum value).

(6c) System minimum value (or maximum value)
Next, a third operation for detecting the address of the processor that has generated the comparison target data of the system maximum value (or the system minimum value) will be described.

Referring to FIG. 1, control device 500 broadcasts a minimum value (or maximum value) processor address output instruction to all semiconductor devices 100, and at the same time, a comparison target data of system maximum value (or system minimum value). Are transmitted to the processor address bus 404 for all the semiconductor devices 100 that have generated the. The semiconductor device address decoder 407 asserts a semiconductor device selection signal for one semiconductor device 100 specified by the semiconductor device address and supplies the signal to the semiconductor device 100 via a signal 408. Control device 500 further issues a data bus control instruction instructing that data on output data external common bus 403 be taken into control device internal bus 609 in program execution control circuit 515.
06 (FIG. 6).

Referring to FIG. 2, in semiconductor device 100 in which the corresponding semiconductor device selection signal is asserted, instruction decoder 109 decodes the instruction and gives minimum value (or maximum value) to processor selection circuit 300. ) Outputs an instruction to output the address of the processor having Further, the selector 113 issues an instruction to output data on the output data internal common bus 118 to the tri-state buffer 120.

Referring to FIG. 3, the processor selecting circuit 3
At 00, the processor selection signal generation circuit 307
The following operation is performed according to the output instruction supplied from the instruction decoder 109.

The selector 305 includes the address generation circuit 30
4 selects the in-device processor address of the minimum value processor (or the in-device processor address of the maximum value processor output by the address generation circuit 303).
The selector 306 selects an internal processor address of the minimum value processor (or an internal processor address of the maximum value processor) selected by the selector 305 and supplies the selected processor address to the processor selection signal generation circuit 307 and the selector 310.

To the selector 310, the processor address in the device of the minimum value processor (or the processor address in the device of the maximum value processor) selected by the selector 305 and the non-numerical data (NaN) are input. As we are now discussing, all processors 200 in all semiconductor devices 100 are to be compared, and therefore zero detection circuit 30
When the output of 9 (or 308) is 0, the processor selection signal generation circuit 307 responds to the instruction by
The selector 310 is configured to supply a selector control signal 318 to the selector 310 so that the selector 310 selects the in-device processor address supplied by the selector 305. Therefore, the selector 310 selects the selector 3
The processor address selected in step 05 is selected and output as a signal 117. The signal 117 is output via the tristate buffer 115 to the output data internal common bus 1.
18. Further, the processor selection signal generation circuit 307 transmits a control signal 116 to be supplied to the tri-state buffer 115 to transfer the processor address in the device on the signal 117 to the output data internal common bus 118. 117
Assert at the timing transferred to. In this way, the in-device processor address of the system minimum value processor (or system maximum value processor) is transferred to the control device 500 via the external data output terminal 106 and the output data external common bus 403.

In the semiconductor devices 100 other than the semiconductor device 100 for which the corresponding semiconductor device selection signal is asserted, the processor selection circuit 300 operates in the same manner, but the tristate buffer 120 is not turned on. The internal processor address is not output to the output data external common bus 403 from 100.

As described above, in this embodiment, the maximum value processor in the device, the minimum value processor in the device, the maximum value in the device, or the minimum value in the device are determined by the processor selection circuit 300 provided in each semiconductor device 100. The minimum value processor detection circuit 350 can detect the value at high speed. Further, a system maximum value processor, a system minimum value processor, a system maximum value, or a system minimum value can be detected together with a maximum value minimum value detection circuit 608 in the control circuit.

(7) Device operation when there is a processor not to be compared In the first to third operations described above, all the semiconductor devices 1
It was assumed that all processors 200 in 00 were to be compared. However, any processor 200 in any semiconductor device 100 may be excluded from comparison. When at least one of the processors is out of the comparison target, the operation of the device is changed as follows.

(7a) Referring to FIG. 3, in the first operation, when each processor executes a comparison data output instruction, and when the processor is a comparison target, comparison target flag 220 is 1. Therefore, as described above, the selector 217 selects the comparison target data read from the weight value memory 203 or the register file 204, and sends the selected data to the output data internal common bus 118. However, when any of the processors is not a comparison target, the comparison target flag 220 is 0, so that the selector 217 in that processor selects predetermined non-numeral data (NaN) and outputs the output data internal common bus 11.
Send to 8. This non-numerical data is composed of a bit string that can be distinguished from floating point data. For example, all the bit strings located at the exponent part of the floating-point data have the value 1.

As described above, when at least one of the first and second data provided to the comparison operation in the ALU 201 in any of the processors is a non-numerical data, the non-minimum value signal 215, the non-maximum signal Neither value signal 216 is asserted. Therefore, even when the data comparison instruction is executed after the non-numerical data is subsequently broadcast to all processors 200 in the same semiconductor device 100,
Depending on the result of the comparison operation in each processor, the maximum value flag and the minimum value flag for that processor are not changed. As described above, even when a comparison data output instruction is executed even for a processor that is not a comparison target, the detection of the maximum value and the minimum value in the present embodiment is not affected. Therefore, control device 500 can cause all processors to execute the same series of instructions regardless of whether or not each processor is a comparison target.

(7b) Referring to FIGS. 1 and 2, the second
In the operation of (1), the control device 500 sends the output data internal common bus 1 from the processor having the minimum value (or the maximum value).
18 to output data to all semiconductor devices 10
When broadcasting to 0, all processors in any of the semiconductor devices 100 may not be compared. In this case, it is better not to send comparison target data from the semiconductor device 100 to the control device 500. In the present embodiment, the processor selection circuit 300 operates as follows.

Referring to FIG. 4, the semiconductor device 100
Are all 0 in the minimum value flag register 302 (or the maximum value flag register 301). Therefore, the output of the zero detection circuit 309 (or 308) is 1. In response to the comparison target data output instruction supplied from the instruction decoder 109, the processor selection signal generation circuit 307 responds to the zero detection circuit 309 (or the zero detection circuit 30).
When the output of 8) is 1, the selector 310 selects non-numerical data as invalid comparison target data, and
A selector control signal 318 is supplied to the selector 310 so as to be transmitted to the selector 17. Further, in order to transfer the non-numerical data on the signal 117 to the output data internal common bus 118, the processor selection signal generation circuit 307 changes the control signal 116 supplied to the tri-state buffer 115 to the Assert at the transferred timing. Thus, the non-numerical data is transferred to the control device 500 via the external data output terminal 106 and the output data external common bus 403. The control device 500 discards the non-numerical data as invalid comparison target data.

(8) Format Conversion Circuit Referring to FIG. 2, the format conversion circuit 102 converts the output of the selector 111 into a floating-point format, assuming it is data of a fixed-point format, and outputs the data. The format conversion circuit 103 converts the data of the output data internal common bus 118 into a fixed-point format, assuming that the data is in a floating-point format, and outputs the converted data.

The format conversion circuit 102 can format-convert the data output from the processor 200 to the output data internal common bus 118 and return it to the same processor or another processor again via the input data internal common bus 119. In the above description, the comparison target data of all the processors 200 is assumed to be data in the floating-point format expression. However, even if the comparison operation data of any one of the processors 200 is in the fixed-point data format, the floating-point format conversion circuit 102 uses the floating-point format conversion circuit 102 inside the semiconductor device regardless of the externally connected data bus. It can be unified into expression data. That is, all the semiconductor devices 10
The above-described conversion can be executed in parallel for each 0, and it is considered that the format of the entire apparatus can be unified at high speed. Further, the fixed-point format conversion circuit 1
03 can be used to unify the data in a fixed-point format.

Further, externally applied data can be provided to the processor 200 via the format conversion circuit 102. For example, fixed-point format data can be externally provided to the semiconductor device 100 as data used for arithmetic operation in a floating-point format. The output of each processor can be output to the outside via the format conversion circuit 103. For example, floating-point format data generated by the semiconductor device 100 can be extracted to the outside as fixed-point format data.

(9) Initial Setting Operation (9a) Initial Setting of Comparison Target Flag The initialization of the comparison target flag 220 in each processor is performed as follows. Referring to FIG. 3, in each processor, the ALU 201 determines whether the operation result data is, for example, zero, non-zero, negative, non-zero, In the case of positive, non-zero positive, non-numerical data (numerical data) input, or non-numerical data not input, the operation result was non-numerical data ( That is,
If the calculation is not possible) or if the data does not become non-numerical data (that is, the calculation is possible), a condition code indicating the state of the calculation is output. The condition code register 219 is a multi-bit register that stores a plurality of operation states.
The condition code generated by the LU 201 is written to the condition code register 219 according to the instruction. In some cases, this writing is not performed. The selector 218 selects and outputs any one bit of the condition code register 219 according to the instruction.

The comparison target flag 220 includes the selector 21
8 are connected. Writing of the comparison target flag to the comparison target flag 220 of each processor is executed by a comparison target flag preset command and a comparison target flag write command. At the time of the initial setting operation, when the control device 500 broadcasts the comparison target flag preset command to all the semiconductor devices 100 and each semiconductor device 100 broadcasts this command to each processor, the comparison target flag 2 is set in each processor.
20 is set by this comparison target flag preset command (in other words, 1 is output). Control device 500
Broadcasts a comparison flag write command to all the semiconductor devices 100, and each semiconductor device 100 broadcasts this command to each processor. In each processor, the selector 218 specifies the condition code register 2
Select any 19 bits. Comparison target flag 220
Is reset (in other words, 0 is output) only when the selected bit is 0. When the output of the selector 218 is 1, it remains set. That is,
Once the comparison target flag is reset by the comparison target flag write instruction, the comparison target flag write instruction is executed again thereafter unless the comparison target flag preset instruction is performed, and the output of the selector 218 at that time is set to 1
In this case, it is possible to accumulate the reset without being set again.

For example, if the processor 200 whose comparison target data is non-numerical data is to be excluded from the comparison, the control device 500 can exclude such a processor as follows. Prior to the execution of the comparison target flag preset instruction, the comparison target flag 2 of all processors is executed by the comparison target flag preset instruction.
Set 20 to 1. Thereafter, the ALU 201 causes each processor to perform an arbitrary floating-point operation on the data to be compared. ALU20 for the operation
1 is written into the condition code register 219. A comparison flag writing instruction is executed to specify that the selector 218 selects a bit indicating that non-numerical data has not been input to the ALU in the condition code register 219. As a result, the comparison target flag 2 in the processor 200 whose comparison target data is non-numerical data by the above-described operation.
20 is reset to 0, and the comparison target flag 220 in the other processor remains set to 1.

(9b) Initial Setting of Maximum Value Flag Register and Minimum Value Flag Register Referring to FIG. 1, first, control device 500 broadcasts a preset information output instruction to all semiconductor devices 100. FIG.
With reference to FIG.
9 decodes the instruction and broadcasts a preset information output instruction to all processors 200. Referring to FIG. 3, in each processor 200, the instruction decoder 20
9 decodes the instruction, controls the selector 210 and the selector 211, and negates the comparison target flag 220 output from the inverter 228 via the comparison result information output terminal 208. It is output instead of the maximum value signal 216. The outputs of the selectors 211 and 210 at this time are also referred to as a non-minimum value signal 215 and a non-maximum value signal 216, respectively, for simplification. Here, assuming that all processors in all semiconductor devices 100 are comparison targets, all processors 20
The comparison target flag 220 in 0 is set. Therefore, the non-minimum value signal 215 and the non-maximum value signal 216 output from the selectors 210 and 211 are both 0.

Returning to FIG. 1, control device 500 next issues a maximum value / minimum value flag preset command to all semiconductor devices 100.
To broadcast. Referring to FIG. 2, the instruction decoder 109 of each semiconductor device 100 decodes the maximum / minimum value flag preset instruction and outputs the maximum / minimum value flag preset instruction to the maximum / minimum value processor detection circuit 350. . Referring to FIG. 4, the processor selection circuit 300
At the maximum value flag register 30 according to the instruction.
The flags in the 1 and minimum value flag registers 302 are:
When the non-maximum value signal 216 or the non-minimum value signal 215 is output from the corresponding processor 200 in the same semiconductor device 100, the signal is set when the signal is 0 and reset when the signal is 1. In this case, all the processors are to be compared, and the non-maximum value signal 216 and the non-minimum value signal 215 output from each processor are both 0. The flag is set to 1.

In the above, it has been assumed that all the processors 200 of all the semiconductor devices 100 are to be compared. However, if any of the processors in any of the semiconductor devices 100 is not a comparison target, the comparison target flag 220 in that processor is initialized to 0 by the method described above. The non-minimum value signal 215 and the non-maximum value signal 216 output from this processor are both 1 as is clear from the above description. Therefore, when the maximum value minimum value flag preset instruction is executed, both the maximum value flag in the maximum value flag register 301 and the minimum value flag in the minimum value flag register 302 for this processor are reset to 0.

By the operation from the preset information output instruction to the maximum value / minimum value flag preset instruction, the comparison target flag 220 is stored in the minimum value flag register 302 and the maximum value flag register 301 of the maximum value / minimum value processor detection circuit 350. Processor 200 set
Are set, and the other flags are reset. As a result, the processor 200 for which the comparison target flag 220 is not set is excluded from the candidate for the processor having the maximum value and the candidate for the processor having the minimum value, prior to the above-described first operation,
The maximum and minimum values are not subject to processor detection.

(10) Modifications Although the present invention has been specifically described based on the embodiments of the present invention, the present invention is not limited thereto, and can be variously modified without departing from the gist thereof. Needless to say. The following is an example of such a modification.

(10a) Other detection method of system minimum value (maximum value) The system maximum value, system maximum value processor, system minimum value and system minimum value are not provided in the controller 500. It is also possible to determine the minimum value processor. For this purpose, a program in the control device 500 and each semiconductor device 100 are executed so as to execute the following operation instead of the second and third operations described above. May be modified.

For example, instead of the second operation, control device 500 transmits a data transmission instruction and information on the storage position of the minimum value (or maximum value) in the device detected in each semiconductor device 100 which is data to be transmitted. Is broadcast to all the semiconductor devices 100. A semiconductor device address for selecting one of the semiconductor devices 100 is transmitted to the processor address bus 404.
And the semiconductor device address decoder 407 causes the semiconductor device 100 to be selected. In the selected semiconductor device 100, the instruction decoder 109 broadcasts the instruction and the information to all processors, and outputs an instruction to output a minimum value (or a maximum value) to the processor selection circuit 300 to the output data external common bus 403. Then, an instruction to select the output data internal common bus 118 is supplied to the selector 113. Each processor reads data into the corresponding tri-state buffer 121 in the same manner as described above. Further, in response to the output instruction, the processor selection circuit 300 sends a processor selection signal to the tristate buffer 121 corresponding to the maximum value processor in the semiconductor device 100, and the processor selection signal read from the processor 200 The minimum value (or the maximum value in the device) is transferred to the output data internal common bus 118. The address of the minimum (or maximum) processor is calculated by the address generation circuit 304 in the maximum / minimum processor detection circuit 350.
(Or the address generation circuit 303).
The selector 113 in the selected semiconductor device 100
Sends the maximum value data on the output data internal common bus 118 to the tri-state buffer 120 in response to the selection instruction from the instruction decoder 109. Tristate buffer 120 sends the data to output data external common bus 403 in response to a signal from signal 408.

Control device 500 supplies to bus control circuit 606 (FIG. 6) an instruction to transfer the internal minimum value (or maximum value) data on output data external common bus 403 to input data external common bus 402. . Further, similarly to the first operation, the comparison operation instruction and the storage position information of the data to be compared are broadcast to all the semiconductor devices 100 via the instruction external common bus 401. The bus control circuit 606 broadcasts the minimum value (or maximum value) data in the device to all the semiconductor devices 100 via the input data external common bus 402. In each semiconductor device 100, the same operation as the first operation is performed, and the maximum value flag register 301 and the minimum value flag register 302 in the maximum value minimum value processor detection circuit 350 are updated. The control device 500 performs the above operation by sequentially selecting different semiconductor devices 100. Thus, the second operation ends. As a result, the comparison target data of all the processors in all the semiconductor devices are compared with each other. As a result, only the minimum value flag for the processor having the system minimum value and the maximum value flag for the processor having the system minimum value are 1, and both of these flags are 0 for the other processors.

In the above operation, when all the processors in any one of the semiconductor devices are not to be compared,
The maximum value data of the semiconductor device 100 is invalid. In this case, the processor selection circuit 300 in the semiconductor device 100 sends out non-numerical data in the same manner as the operation described above. Therefore, the read data from the semiconductor device 100 does not affect the detection of the system minimum value or the system maximum value.

Thereafter, control device 500 performs the following operation in place of the third operation already described, and obtains the processor address of the system maximum value processor. In this case,
Control device 500 does not know which semiconductor device 100 has the system minimum value (or system maximum value). Therefore, the address of the detected maximum value processor is transmitted to each semiconductor device 100. That is, the control device 50
0 broadcasts an instruction to output the address of the maximum value processor to all the semiconductor devices 100, and sends a semiconductor device address for selecting one of the semiconductor devices 100 to the processor address bus 404. The processor selection circuit 300 in the semiconductor device 100 sets the processor address in the device of the maximum value processor in the semiconductor device 100 as in the case of the operation already described.
Send to 00. The control device 500 performs this operation by sequentially switching the semiconductor device to be selected.
The processor addresses in the device of the maximum value processor sequentially detected from 00 are received.

However, there is the following problem here. Of all the semiconductor devices 100, one or more have the system maximum value, and the other semiconductor devices 100 do not have the system maximum value. In such a semiconductor device 100, the minimum value flag register 302 (or the maximum value flag register 3
01) are all 0. In this embodiment, at this time, the address generation circuit 304 (or the address generation circuit 303) outputs an in-device processor address having a value of 0. However, this address is invalid. Accordingly, as shown in FIG. 9, the processor selection circuit 300 in each semiconductor device 100 includes the address generation circuit 30
4 (or the address generation circuit 303) is generated by the address generation circuit 304 (or the address generation circuit 303) so that it is possible to identify whether the processor address in the device of the minimum value (or the maximum value) generated by the processor is invalid. A selector 312 for switching and adding an all 1 bit string or an all 0 bit string to the upper side of the internal processor address is provided between the selectors 305 and 310. The address generation circuit 304 (or the address generation circuit 30)
When the in-device processor address generated by 3) is invalid, the output of the zero detection circuit 309 (or 308) is 1. Therefore, the processor selection signal generation circuit 307
Is the minimum value (or the maximum value) from the instruction decoder 109.
If the output of the zero detection circuit 309 (or 308) is 1 when the instruction to send the processor address in the processor of the processor to the output data external common bus 403 is received,
The selector 312 is controlled by a line 319 to select the selector 312.
A new invalid processor address is generated by adding a bit string of all 0s to the upper side of the processor address in the device of the minimum value (or maximum value) output from the processor 05 and is supplied to the selector 310. On the other hand, if the output of the zero detection circuit 309 (or 308) is 0, the processor selection signal generation circuit 307 switches the selector 312 to the line 3
19, a new processor address is generated by adding an all-ones bit string to the upper side of the processor address in the device of the minimum value (or maximum value) processor output from the selector 305, and is supplied to the selector 310. . This new processor address is
Transferred to 00. The control device 500 controls the entire semiconductor device 1
Of the processor addresses sent from 00, a processor address having a bit string of all 1s on the upper side is processed as a valid processor address. The semiconductor device address of the semiconductor device 100 that has output the valid processor address is the address that the control device 500 itself has sent to the processor address bus 404 to select the semiconductor device 100 first, and the control device 500 A set of the semiconductor device address and the in-device processor address within the detected valid processor address is used as the processor address of the system minimum (or maximum) processor. In the above method, it is not necessary to provide the maximum value / minimum value detection circuit 608 in the control device 500.

(10b) Other types of parallel computers For example, SPMD (each processor is included in the control device 500 and includes a program storage device such as the control storage device shown in FIG. 5 and a program execution control circuit) Single P
rogram, Multiple Data) system. The method of the parallel computer at this time is MIM
D (Multiple Instruction Stream, Multiple Data Str
eam) type parallel computer. The local memory 203 or the register file 2 of each processor
04 may be provided commonly to a plurality of processors in the same semiconductor device, or may be a shared memory system provided commonly to the entire system. A plurality of pairs of global buses for data input / output of a semiconductor device or a processor may be provided. INDUSTRIAL APPLICABILITY The present invention can be generally applied to an information processing system having at least a plurality of arithmetic units and operating a parallel algorithm by data communication between the arithmetic units.

As described above, the semiconductor device 10
0, a plurality of integrated processors 200 inside the semiconductor device irrespective of an externally connected data bus.
Since the magnitude comparison operation of data between the semiconductor devices 100 can be performed, in the information processing system 400 equipped with the plurality of semiconductor devices 100, the operation of detecting a processor having a maximum value or a minimum value simultaneously and in parallel for each semiconductor device 100 becomes possible,
Processing steps required to detect a processor having a maximum value or a minimum value in the system can be greatly reduced. Now, the semiconductor device 10 in the information processing system 400
The number of 0s is m, and the processor 2 in each semiconductor device 100
Assuming that the number of 00 is n, the minimum processing step required for detecting the maximum value or the minimum value according to the prior art is n ×
m [steps]. However, the overhead of the pipeline was ignored. However, in the above embodiment, it can be set to n + m [steps] (however, the overhead of the pipeline is ignored). For example, when m = 64 and n = 8, it is about 7 times faster than the conventional technique, and when m = 64 and n = 16, it is about 1 time faster than the conventional technique.
It is three times faster, and when m = 64 and n = 64, it is about 32 times faster than the prior art. Thereby, for example, it is possible to easily configure a parallel computer in which the calculation for repeating the processing for specifying the maximum value or the minimum value such as the learning vector quantization algorithm is accelerated.

Further, since the information as a result of the comparison operation is accumulated and held in the maximum value flag register 301 and the minimum value flag register 302, the detection of each processor having the maximum value and the minimum value can be performed by an arbitrary processing step. It can be executed intermittently. When non-numerical data is input to the comparison operation, it does not affect the maximum value flag register 301 and the minimum value flag register 302, so that the maximum value or minimum value detection information is accurate and the data to be compared is Can be data in floating-point format including non-numerical data. Further, the maximum value flag register 301 and the minimum value flag register 302
For example, even when all the semiconductor devices are reset, the semiconductor device outputs non-numerical data, so that the maximum value or the minimum value of the semiconductor device is given to a parallel computer (for example, the information processing system 400) mounted. It can indicate that the value detection result is not accurate.

Further, the processor which does not need to detect the maximum value or the minimum value is set in the maximum value flag register 301 and the minimum value flag register 30 which are executed at the beginning of the detection procedure.
By resetting the comparison target flag 220 in the processor prior to the preset 2, it is possible to exclude the detection target, so that the processing related to the comparison operation has the same procedure regardless of the target processor. Can be.

Since the comparison operation can be executed by, for example, the ALU 201 in the processor, the logical scale added by the present invention can be relatively small. Further, the floating point format conversion circuit 102 is provided inside the semiconductor device.
To the data in the floating-point format, or the data in the fixed-point format using the fixed-point format conversion circuit 103. Format can be unified. This makes it possible to provide a semiconductor device in which a conversion circuit between data formats is efficiently provided without providing a data conversion circuit for each processor.
The chip size of the semiconductor device can be reduced.

When data external to the semiconductor device 100 is input into the processor 200, the data can be converted into a floating-point format.
When the data in 00 is output to the outside of the semiconductor device 100, the data can be converted into a fixed-point format. All of these conversions are performed by a format conversion circuit provided on a pipeline of a time-division bus. The conversion time can be virtually negligible. This makes it possible to provide a semiconductor device that can easily realize a processor array of a parallel computer for executing a parallel algorithm in which data in a floating-point format and data in a fixed-point format are mixed.

[0128]

As described above, according to the present invention, a semiconductor device formed on an LSI including a plurality of processors and capable of efficiently detecting a processor having a maximum value or a minimum value can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a SIMD-type parallel computer using a semiconductor device according to the present invention.

FIG. 2 is a schematic block diagram of a semiconductor device according to the present invention.

FIG. 3 is a schematic block diagram of a processor used in the apparatus of FIG. 2;

4 is a schematic block diagram of a maximum / minimum value processor detection circuit and a processor selection circuit used in the semiconductor device of FIG. 2;

FIG. 5 is a schematic block diagram of a control circuit used in the SIMD type parallel computer of FIG. 1;

6 is a schematic block diagram of a program execution control circuit used for the control circuit of FIG.

FIG. 7 is a diagram showing a schematic format of a microinstruction used in the SIMD type parallel computer of FIG. 1;

8 is a schematic block diagram of a bus control circuit used in the control circuit of FIG.

FIG. 9 is a schematic block diagram of a processor selection circuit used in another semiconductor device according to the present invention.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideaki Koizumi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Takuo Okahashi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Atsushi Takeuchi 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Takashi Yokoi 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Hitachi Central Research Laboratory ( 56) References Hitachi Microcomputer Technical Report Vol. 8, No. 1 p2-10 1994 (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 15/16 610 G06F 15/16 640 G06F 15/18 520 JICST file (JOIS)

Claims (11)

(57) [Claims] A plurality of processors, data output by one of the processors can be output to the outside, and data sent by one of the processors and data input from the outside are selected to select all of the plurality of processors. A large-scale integrated circuit having an interconnecting network for broadcasting to a plurality of processors, a processor selecting circuit for selecting an arbitrary one of the plurality of processors, and a detecting circuit. A semiconductor device capable of configuring a processor array of a parallel computer by connecting the input and output to and from the outside of a connection network, wherein each processor includes a data storage unit and the comparison target data stored in the data storage unit. Means that can be sent to the interconnection network, comparison target data input from the interconnection network, and comparison target data stored in the processor And a computing unit capable of executing a comparison operation for discriminating the magnitude of the comparison result and outputting a comparison result signal, wherein the plurality of processors are capable of executing the comparison operation and outputting the comparison result signal simultaneously and in parallel. Each processor is configured to sequentially execute the comparison operation on each of a plurality of comparison target data sequentially input from the interconnection network and output the comparison result signal. The detection circuit, based on the plurality of comparison result signals respectively output by the plurality of processors, a maximum value processor that stores comparison target data that is the maximum value for the plurality of comparison target data, A semiconductor device for detecting at least one of a minimum value processor storing comparison target data having a minimum value. 2. The comparison result signal output by each processor includes at least a non-minimum value signal indicating that the comparison target data stored in the processor for each of the comparison operations is significant. The circuit includes a plurality of minimum value flag storage units each corresponding to one of the plurality of processors, and capable of storing a flag indicating whether or not the corresponding processor is a candidate for the minimum value processor. The minimum value flag storage means can set any state, and furthermore, sets the flag to a state which is not a candidate for the minimum value processor in response to only the significance of the non-minimum value signal output from the corresponding processor. Each of a plurality of comparison target data broadcast from the plurality of processors via the interconnection network. A state in which the minimum value flag storage means responds to the non-minimum value signal sequentially output by the comparison operation of the processor, and is a candidate of the minimum value processor among the plurality of minimum value flag storage means. 2. The semiconductor device according to claim 1, wherein a processor corresponding to the one indicated by the following is detected as the minimum value processor. 3. The detecting circuit according to claim 1, wherein when at least one of said plurality of minimum value flag storage means indicates a state of being a candidate for a minimum value processor, the detection circuit corresponds to one of the candidates. A minimum processor address generation unit capable of generating one of the addresses assigned to each of the plurality of processors, wherein the processor selection circuit is configured to execute at least an address generated by the minimum processor address generation unit. The semiconductor device is configured to be capable of selecting a processor, and the semiconductor device depends on whether or not at least one of the plurality of minimum value flag storage means indicates a state of being a candidate for the minimum value processor by the detection circuit. The comparison target data or the invalid comparison target stored in the processor selected by the processor selection circuit. The semiconductor device according to claim 2 having an external enable output means of the semiconductor device by switching the over data. 4. The semiconductor device according to claim 1, wherein:
The address or the invalid address generated by the minimum processor address generation unit is switched depending on whether at least one of the plurality of minimum value flag storage units indicates a candidate for a minimum value processor. 4. The semiconductor device according to claim 3, further comprising a unit capable of outputting to the outside of the semiconductor device. 5. The comparison result signal output by each processor includes at least a non-maximum value signal indicating that the comparison target data stored in the processor for each of the comparison operations is significant. The circuit includes a plurality of maximum value flag storage means respectively corresponding to one of the plurality of processors, and capable of storing a flag indicating whether or not the corresponding processor is a candidate for the maximum value processor. The maximum value flag storage means can set any state, and furthermore, sets the flag to a state which is not a candidate for the maximum value processor in response to only the significance of the non-maximum value signal output from the corresponding processor. Each of a plurality of comparison target data broadcast from the plurality of processors via the interconnection network. A state in which the maximum value flag storage means responds to the non-maximum value signal sequentially output by the comparison operation of the processor, and is a candidate of the maximum value processor among the plurality of maximum value flag storage means. 5. The semiconductor device according to claim 1, wherein a processor corresponding to one of the following is detected as the maximum value processor. 6. 6. The detection circuit according to claim 1, wherein at least one of said plurality of maximum value flag storage means indicates a state of being a candidate for a maximum value processor. A maximum processor address generating unit capable of generating one of the addresses assigned to each of the plurality of processors, wherein the processor selecting circuit is configured to generate at least a maximum processor address based on the address generated by the maximum processor address generating unit. The semiconductor device is configured to be capable of selecting a processor, and the semiconductor device depends on whether or not at least one of the plurality of maximum value flag storage means indicates a state of being a candidate for a maximum value processor by the detection circuit. The comparison target data or the invalid comparison target stored in the processor selected by the processor selection circuit. The semiconductor device according to claim 5 having a mechanism capable of outputting to the outside of the semiconductor device by switching the over data. 7. The semiconductor device according to claim 1, wherein:
The address or the invalid address generated by the maximum value processor address generation means is switched depending on whether at least one of the plurality of maximum value flag storage means indicates a state of being a candidate for a maximum value processor. 7. The semiconductor device according to claim 6, further comprising a unit capable of outputting to the outside of the semiconductor device. 8. Each of the processors includes instruction means for storing and instructing whether or not the processor is a processor to be compared in response to an instruction given from the outside, and the instruction means included in the processor. Means for switching between the stored comparison target data and the invalid comparison target data of the processor in response to an instruction as to whether or not the processor is a comparison target processor and transmitting the data to the interconnection network. The arithmetic unit in each processor is configured to output an insignificant comparison result signal when comparison data broadcast from another processor to the interconnection network is invalid comparison data. The semiconductor device according to claim 2. 9. The processor selection circuit is configured to be capable of sequentially selecting at least all processors in the same semiconductor device, and the means for broadcasting by the interconnection network is selected by the processor selection circuit. All the processors in the same semiconductor device can simultaneously input the data sent by the processor, and the sequential selection of the processor in the processor selection circuit and the sequential selection in the interconnection network thereby. The semiconductor device according to claim 1, wherein the detection is performed by a suitable broadcast. 10. The means for sequentially selecting an arbitrary one of the plurality of processors by the processor selection circuit includes a processor for sequentially selecting at least one of the plurality of processors based on an address assigned to each processor sequentially input from outside the semiconductor device. The semiconductor device according to claim 9, configured to make a selection. 11. A semiconductor device comprising: a first data format conversion circuit capable of converting fixed-point format data to a floating-point format; and a second data format capable of converting floating-point format data to a fixed-point format. A conversion circuit, wherein the interconnection network is connected to an input data internal common bus connected to respective inputs of the plurality of processors, and to respective outputs of the plurality of processors via a tri-state buffer. An output data internal common bus, the input of the second data format conversion circuit is connected to the output data internal common bus, and the semiconductor device comprises: The first data format is switched by switching from the data on the internal common bus. First selecting means for inputting to the mat conversion circuit, data input from the outside, data on the output data internal common bus, data output by the first data format conversion circuit, Second selecting means for switching from the data output by the second data format conversion circuit to output to the input data internal common bus, data on the output data internal common bus, and the second data format conversion 11. The semiconductor device according to claim 1, further comprising third selection means for switching the data output from the circuit and outputting the data to the outside.