JP2967796B2 - Layout design method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of designing a layout of a semiconductor integrated circuit, and more particularly to a method of automatically designing a layout of a semiconductor integrated circuit using a computer.

[0002]

2. Description of the Related Art In recent years, the scale of semiconductor integrated circuits and the variety of small-quantity products have been increasing, and there has been an increasing demand for reducing the number of design days by introducing automatic design using a computer.

Incidentally, automatic layout design has two stages, ie, layout and wiring, which are roughly divided, and it is desirable to provide layout that facilitates wiring.

Hereinafter, a conventional method for improving the layout to facilitate wiring in automatic layout design will be described.

There is a conventional method in which the relative positional relationship of each module on a circuit diagram is stored and arranged on a layout. This is a method of calculating the layout area of each module, arranging the modules so that they do not overlap on the layout, and minimizing the layout area so as to minimize the relative positional relationship on the circuit diagram.

In addition, in order to improve placement with high accuracy, provisional routing is performed in the placement step, and placement is changed based on the result, or layout is changed in the wiring step. To allow for both placement and routing
A method of asymptotically optimizing characteristics and area has been used.

In addition, a certain evaluation criterion, for example, a suction vector (a direction in which each module should be moved and a quantity indicating a moving distance obtained from the connection relation of each module) is uniquely determined and arranged based on the determined vector. There was also a method of exchanging existing modules.

In automatic layout design of a semiconductor integrated circuit, it is desirable that the layout area be as small as possible.

In the automatic layout design, a method of improving the layout so as to reduce the layout area is desired. Conventionally, the reduction of the layout area involves packing the laid out modules one-dimensionally (vertically and horizontally). The processing was performed by repeating.

[0010]

However, with respect to a method of improving the layout so that wiring is easy, according to a conventional layout improvement method for storing a circuit diagram, particularly when the layout area and shape of each module are different, The layout area tends to be large. In another conventional method for improving placement by alternately repeating placement and routing, it takes a considerable processing time to determine an optimum placement. Therefore, it is not practical in a circuit having a large number of elements. Another method of exchanging the arranged modules is that if the number of pairs to be exchanged is large and the circuit with a large number of elements takes considerable processing time, and if the layout area and shape of each module is The layout area tends to be large due to restrictions (area, shape, design rules, etc.) taken into account.

According to the method of reducing the layout size, according to the method of one-dimensionally packing modules,
There is a lot of unnecessary free space in the layout that does not disappear even if the repetition processing is performed, and the processing is repeated many times until the layout size is minimized, so that processing time is required.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a layout design system for generating a mask pattern of each element on a circuit diagram using a computer, arranging the mask pattern on a mask layout, and then performing wiring. This is an improvement method, and its object is to improve the arrangement effectively in a short processing time.

[0013]

According to the method of designing a layout of a semiconductor integrated circuit of the present invention, in the step of improving the layout, the steps of selecting each module on the layout in the order opposite to the moving direction are selected. Moving or moving the module in the movement target direction, and then deforming the module.

[0014]

According to the above layout design method, by sequentially moving the modules arranged in the area in the movement destination direction, a free area is newly generated in the movement destination direction of the module to be moved later and moved later. Since the module to be moved easily moves in the movement target direction, the modules connected on the circuit diagram can be collected quickly and effectively on the layout, or can be collected close to the layout origin. The time required to execute the above layout method is expected to be proportional to the number of modules, but this is a sufficiently short process as compared with the conventional arrangement improvement method. Therefore, the arrangement can be effectively improved in a short time.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention can be applied to the improvement of the arrangement of element modules in a block layout, the improvement of the arrangement of blocks in a chip, and the like. In this embodiment, a method of improving the arrangement of element modules in a block will be described.

In the sequential movement of each module on the layout according to the present invention, it is important how to determine the destination of movement within the area in the direction of movement.

In the following, in order to improve the layout in which wiring is easy using a simple circuit diagram model, it is necessary to determine a moving destination in order to effectively collect modules connected on the circuit diagram on a layout. An example of the method and an embodiment in which the method is effective in the present invention will be described.

Here, with respect to the movement of the element, the element may be deformed in accordance with the shape of the empty area at the destination after the movement, but will not be described below.

By the way, in a circuit diagram of a block, a system in which a power supply potential wiring and a ground potential wiring (hereinafter referred to as a priority wiring) are provided above and below is generally used. In a block mask layout, a power supply potential wiring and a ground potential wiring are arranged above and below a block, and a wiring method is generally used in which a main line is made thicker than a general wiring.

FIG. 1 is a block circuit diagram of an analog circuit modeled on the basis of the flow of electric signals from a power supply potential to a ground potential. In FIG. 1, straight lines 1n and 2n represent priority wiring, and other straight lines represent wiring other than priority wiring. In FIG. 1, the broken lines indicate, for modeling, a wiring with a lower priority for reflecting the connection relationship in the arrangement, and a pair element that is treated as one module because it is an adjacently designated element.

FIG. 3 is an example of a mask layout diagram before arrangement improvement in which each element module of a simple circuit diagram model is arranged on a mask layout. In FIG. 3, A1, A2, A
Reference numerals 3, B1, B2, B3, B4, B5, and B6 denote mask patterns of each element module, 1N and 2N denote estimated positions of priority wirings, and dotted lines denote connection relationships between modules by wirings other than the priority wirings. Show.

According to the arrangement shown in FIG. 3, there are intersections of wirings, and it is difficult to form wirings as they are. According to the connection relationship of each module by wiring other than the priority wiring (hereinafter referred to as general wiring), in order to facilitate wiring, (B1,
A1, B4), (B2, A2, B5), (B3, A3,
B6) are related to each other as a group that should be placed close to each other. Modules related in this way are:
By changing the arrangement so that they are collected on the layout, wiring becomes easier. The relation between modules is determined by the connection relation of general wiring. When a wiring method in which priority wiring is arranged above and below a block is used, wiring between modules by priority wiring is performed without being greatly affected by the arrangement state. This is because you can do it.

FIG. 2 is a flowchart according to the present invention. According to the present invention, the arrangement can be changed so that the modules related as a group as described above are collected. Hereinafter, the invention will be described in detail with reference to the flowchart of FIG.

Process 1 in the flowchart of FIG. 2 is for arranging each module generated from the block circuit diagram on a layout. The arrangement by the process 1 may consider some arrangement restrictions (layout size, estimated wiring length, designation of adjacent proximity based on electrical characteristics, and the like).

FIG. 4 shows an example in which a part of the layout diagram of FIG. 3 is randomly arranged with each module as a symbol. The solid circles are symbols on the layout, and the symbols a1, b1, and b4 are the modules A in FIG.
1, B1 and B4.

FIG. 5 shows another example in which a part of the layout diagram of FIG. 3 is arranged at random as a symbol for each module, similarly to FIG.

In the processing 2, preprocessing for associating modules is performed. Although a simple circuit diagram model is used in the description of the present embodiment, in an actual block circuit diagram, such modeling is performed by first adjoining adjacent designated modules into small groups, or by using a general wiring net. This is because it is necessary to perform preprocessing such as assigning a priority first.

In the process 3, the module data stored in the computer is rearranged in the order of the arrangement coordinates of the modules and stored again. In the following, re-storing data after rearranging data as described above is called sorting. In addition, forward sort refers to a case where data is rearranged such that the arrangement coordinates of modules are arranged from left to right in a block layout, and reverse sort refers to a case where data is rearranged from right to left. I do.

In the process 4, all the modules are moved with the right direction as the movement destination direction for each module in the reverse order of the sorted module data, that is, in the order from right to left in the block layout. To move to the right here means to move the empty area as close as possible to the module with the largest arrangement coordinates in the area of the movement destination direction among the other modules connected by general wiring. It is determined first and the arrangement position is changed.

FIG. 4 shows an example of processing when it is assumed that the above-mentioned movement of the module can be performed without considering the layout constraint. In FIG. 4, the symbol represented by a solid circle represents each module in the arrangement before movement. And the symbol represented by the dotted circle is the positional relationship after the movement. The processing of each module of the module group (b1, a1, b4) to be arranged nearby is performed in the order of b4, a1, b1 based on the arrangement relation of each module in the arrangement before the movement. First, b
The module connected to 4 by general wiring does not move because it does not exist to the right of b4. Since a1 is connected to b4, it moves near b4 by the movement of the arrow 1. Since b1 is connected to a1, it moves to the vicinity of a1 by the movement of arrow 2. In this way, the module groups (b1, a1, b4) to be arranged in the vicinity are:
Collected in one move to the right.

In FIG. 5, however, only the movement of the arrow 3 is performed, and it is not possible to collect all the modules of the group only once by moving rightward.

Therefore, in process 6, all the modules are moved with the left direction as the movement destination direction for each module in the order in which the module data sorted in process 5 is sorted, that is, from left to right in the block layout. I do. Here, the movement to the left means, in this case, of the destination module to which the module to be moved is connected, in the area of the movement destination direction, an empty area as close as possible to the module with the smallest arrangement coordinates is determined as the movement destination. Then, the arrangement position is changed.

In FIG. 6, the processing of each module of the module group (b1, a1, b4) to be arranged in the vicinity depends on the arrangement relation of each module in the arrangement after the first rightward movement. Performed in the order of b4. First,
The module connected to b1 by the general wiring does not move because it does not exist to the left of b1. Since a1 is connected to b1, it moves to the vicinity of b1 by the movement of the arrow 4. Since b4 is connected to a1, the movement of arrow 5 moves to the vicinity of a1. In this way, the module groups (b1, a1, b4) to be arranged in the vicinity are:
Collected with one move to the right and one move to the left. After the processes 4 and 6, the process of moving the block origin and minimizing the block size is required. In some cases, an empty area is formed vertically, but this vertical area can be deleted very easily.

According to the layout improvement method of the present invention, the layout of the modeled circuit diagram is processed in process 1
It can be seen that improvements can be made by performing steps # 6 to # 6.

In general, an actual block circuit can be easily modeled on the basis of a signal flow from a power supply potential wiring to a ground potential wiring, but it is difficult to completely model it. The processes 3, 4, 5, and 6 are repeated while determining the evaluation function to determine the optimal arrangement. The evaluation function may include a virtual wiring length, a layout size, and the like. In each of the movements of the modules in the processing 4 and the processing 6, the optimum moving destination is determined by judging the evaluation function (distance between the connection terminals and the like). In addition, in an actual mask layout, there are restrictions on the layout (element area, shape, design rules, and the like). Therefore, by sequentially moving the modules arranged in the movement direction,
In the present invention, it is possible to create an empty area in the movement destination direction to facilitate the movement.

FIG. 7 is a mask layout diagram in an example in which the present invention is applied to the mask layout of FIG.

In FIG. 7, each module name A1, A2,
A3, B1, B2, B3, B4, B5, and B6 correspond to A1, A2, A3, B1, B2, B3, B4, B5, and B in FIG.
This is the same module as 6. H1 is the block height, W1 is the block width, and H2 is the block height and W2 is the block shown by the dashed-dotted rectangle in FIG. Indicates the width.

N1, N, which are the expected priority wiring positions in FIG.
2 is obtained by moving and deforming N1 and N2 in FIG. 6 according to the size of the block.

In FIG. 3, the processing of each element module is B6, B
The rightward movement is performed in the order of 5, A2, B4, A3, B2, B3, A1, and B1. For the movement of each module, the distance between the connection terminals is determined, and the optimum destination for the movement is determined. First, B6 and B5 do not move. A2 moves to the position in FIG. 7 so as to minimize the distance between the connection terminals with B5. B4 does not move, and A3 moves so as to minimize the distance between the connection terminals with B6. B2 moves so as to minimize the distance between the connection terminals with A2. B3 moves so as to minimize the distance between the connection terminals with A3. A1 is originally A
2. Move to the position where A3 is located so as to minimize the distance between the connection terminals with B4. B1 moves to the position where B2 was originally located so as to minimize the distance between the connection terminals with A1. Then, change the block size from H1 to H2.
FIG. 7 shows the layout after the width is modified from W1 to W2.
It is.

The above is the embodiment according to the present invention as set forth in claim 3. To improve the arrangement in which wiring is easy, it is necessary to select the optimal index such as the virtual wiring length of each element module or the above-mentioned suction vector. Or a combination thereof may be used as an evaluation function at the time of moving each module, and the movement according to the present invention may be performed so as to minimize the evaluation function.

In the above example, the present invention is implemented so as to improve the arrangement to facilitate wiring. However, the embodiment according to the present invention described in claim 4, that is, the moving target direction is set in the direction of the layout origin, If the movement destination is set to the empty area closest to the layout origin and the sequential movement according to the present invention as described in claim 1 is performed, the movement of the module for reducing the layout size can be performed two-dimensionally. The layout size can be effectively reduced in a short period of time as compared with the generally performed one-dimensional module movement.

[0042]

As described above, according to the present invention, the arrangement can be effectively improved in a short time.

In a block mask layout automatic design system to which the invention of claim 3 is applied, a block having about 100 element modules and using a virtual wiring length as an evaluation function for judgment 1 and judgment 2 in FIG. The evaluation function was improved by 10%, and the number of unrouted wires could be reduced in the automatic wiring after the placement was improved, compared with the case where the placement was not improved.

Similarly, in the automatic block mask layout design system to which the invention of claim 4 is applied, the layout area can be reduced by several tens% at the maximum.

[Brief description of the drawings]

FIG. 1 is a diagram modeling a block circuit diagram of an analog circuit;

FIG. 2 is a flowchart of a layout design method according to the present invention;

FIG. 3 is a mask layout diagram before placement improvement.

FIG. 4 is a diagram laid out using the mask pattern of FIG. 3 as a symbol;

FIG. 5 is a diagram laid out using the mask pattern of FIG. 3 as a symbol;

FIG. 6 is a diagram after the symbol layout diagram of FIG. 5 is changed.

FIG. 7 is a mask layout diagram obtained by improving the layout of the mask layout of FIG. 3;

[Explanation of symbols]

 1n Power supply potential wiring on circuit diagram 2n Ground potential wiring on circuit diagram 1N Power supply potential wiring on mask layout 2N Ground potential wiring on mask layout

Claims (4)

(57) [Claims] A method for designing a layout of a semiconductor integrated circuit, comprising: a step of selecting each module on a layout in a direction opposite to a movement target direction; and a step of moving the selected module in the movement target direction or deforming after the movement. . 2. A first step of selecting each module on the layout in the direction opposite to the movement target direction, a second step of moving the selected module in the movement target direction, or deforming after the movement, and the first step. A third step of performing the second step in the same manner by reversing the movement direction, and a step of repeating the first to third steps. 3. A first step of selecting each module on the layout in the direction opposite to the movement target direction, and a step of selecting the other module in the area of the movement target direction and having a connection relationship with the selected module. A second step of searching for a distantly arranged module, a third step of setting an empty area closest to the counterpart module as a movement destination, and moving or deforming the selected module to the movement destination. A semiconductor integrated circuit, comprising: a fourth step of performing the above, a fifth step of performing the first to fourth steps in the same manner by reversing the movement target direction, and a step of repeating the first to fifth steps. Layout design method. 4. A step of selecting each module on the layout in the direction opposite to the direction toward the layout origin, a step of setting an empty area closest to the layout origin as a movement destination, and a step of selecting the module selected as the movement destination. Moving or deforming after moving the semiconductor integrated circuit.