JP2966067B2 - Multilayer lead frame - Google Patents
Multilayer lead frameInfo
- Publication number
- JP2966067B2 JP2966067B2 JP2235067A JP23506790A JP2966067B2 JP 2966067 B2 JP2966067 B2 JP 2966067B2 JP 2235067 A JP2235067 A JP 2235067A JP 23506790 A JP23506790 A JP 23506790A JP 2966067 B2 JP2966067 B2 JP 2966067B2
- Authority
- JP
- Japan
- Prior art keywords
- plane
- lead
- lead frame
- insulating layer
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49527—Additional leads the additional leads being a multilayer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は多層リードフレームに関する。Description: TECHNICAL FIELD The present invention relates to a multilayer lead frame.
（従来の技術） 半導体装置に用いられるリードフレームには、インナ
ーリードと電源プレーンあるいは接地プレーン等の金属
プレーンを積層して形成した多層リードフレームがあ
る。多層リードフレームではポリイミド等の電気的絶縁
性を有するフィルムをインナーリードと金属プレーン間
に介在させて電気的絶縁をとっている。(Prior Art) As a lead frame used in a semiconductor device, there is a multilayer lead frame formed by laminating inner leads and a metal plane such as a power plane or a ground plane. In the multilayer lead frame, a film having electrical insulation such as polyimide is interposed between the inner lead and the metal plane to achieve electrical insulation.
第３図は多層リードフレームの従来例を示す。図で10
は接地プレーン、12は電源プレーン、14はインナーリー
ドで、それぞれ接着剤層を有する絶縁フィルム16を中間
に介在して接合されている。FIG. 3 shows a conventional example of a multilayer lead frame. 10 in the figure
Is a ground plane, 12 is a power plane, and 14 are inner leads, which are joined with an insulating film 16 having an adhesive layer therebetween.
接地プレーン10は半導体チップを搭載するステージを
兼ねるもので、電源プレーン12は半導体チップ搭載面を
囲む枠状に形成され、インナーリード14は電源プレーン
12を取り囲んで配置される。インナーリード14の前端は
電源プレーン12の前縁よりも若干後退させて配置する。
電源プレーン12上に半導体チップとワイヤボンディング
で接続するボンディング部を確保するためである。The ground plane 10 also serves as a stage for mounting the semiconductor chip, the power plane 12 is formed in a frame shape surrounding the semiconductor chip mounting surface, and the inner leads 14 are
It is arranged surrounding 12. The front end of the inner lead 14 is disposed slightly receding from the front edge of the power plane 12.
This is for securing a bonding portion on the power supply plane 12 to be connected to the semiconductor chip by wire bonding.
また、接地プレーン10、電源プレーン12は、それぞれ
外周端から外方に延出して設けた突起とインナーリード
14のうちの接地リード、電源リードとがスポット溶接等
によりそれぞれ電気的に接続される。In addition, the ground plane 10 and the power plane 12 each have a protrusion and an inner lead extending outward from the outer peripheral end.
The ground lead and the power supply lead are electrically connected to each other by spot welding or the like.
（発明が解決しようとする課題） 多層リードフレームは上記のように電気的絶縁性を有
する絶縁フィルムを中間に介在させて金属プレーンおよ
びインナーリードを積層するが、従来の多層リードフレ
ームでは接合する金属プレーンの内外形サイズと絶縁フ
ィルムを同寸法にして接合している。すなわち、たとえ
ば電源プレーン12と接地プレーン10とを接合する場合、
電源プレーン12と同サイズの絶縁フィルムを用いて接合
する。(Problems to be Solved by the Invention) As described above, the multi-layered lead frame laminates the metal plane and the inner lead with an insulating film having electrical insulation interposed therebetween, but the conventional multi-layered lead frame joins the metal to be bonded. The inner and outer dimensions of the plane and the insulating film are the same size and joined. That is, for example, when joining the power plane 12 and the ground plane 10,
The power supply plane 12 is joined using an insulating film of the same size.
多層リードフレームに用いるインナーリードや金属プ
レーンはエッチングによって製造する場合もあるが、量
産が容易なプレス加工で生産する場合はプレス加工時に
プレスバリが生じることによってインナーリードと金属
プレーン間、すなわちこれらの金属層間で電気的なショ
ートをおこすおそれがある。第２図はプレスバリの発生
状態を説明的に示している。プレス加工による場合は第
２図（ａ）に示すように打ち抜き加工時にプレスバリ18
aが縦方向に生じたり、その後プレス型内での移送時な
どに押圧されることによって第２図（ｂ）に示すように
横方向にプレスバリ18bが生じたりする。In some cases, inner leads and metal planes used for multilayer lead frames are manufactured by etching.However, when mass-produced by press working, press burrs occur during press working, so that the inner leads and metal planes, There is a risk of causing an electrical short between the metal layers. FIG. 2 illustrates the state of occurrence of press burrs. In the case of press working, as shown in FIG.
a is generated in the vertical direction, and is then pressed at the time of transfer in a press die, etc., so that press burrs 18b are generated in the horizontal direction as shown in FIG. 2 (b).
従来は金属プレーン等と同寸法の絶縁フィルムを用い
て貼り合わせているから最大75μｍ程度の位置ずれが生
じやすい。したがって、上記プレスバリが生じると絶縁
フィルムとの位置ずれもあり金属層間での機械的な接触
によって電気的なショートが発生するおそれがある。Conventionally, since an insulating film having the same dimensions as a metal plane or the like is used for bonding, a positional shift of about 75 μm or less is likely to occur. Therefore, when the press burrs are generated, there is a positional shift with the insulating film, and there is a possibility that an electric short circuit occurs due to mechanical contact between metal layers.
また、最近はリードフレームの電気的特性を向上させ
るため、特性インピーダンスのマッチングを図ることが
求められている。特性インピーダンスをマッチングさせ
るためには絶縁フィルムを薄厚にする必要があるから、
プレスバリによる金属層間の電気的ショートはさらに発
生しやすくなる。Recently, in order to improve the electrical characteristics of the lead frame, matching of characteristic impedance is required. In order to match the characteristic impedance, it is necessary to make the insulating film thin,
Electrical shorts between metal layers due to press burrs are more likely to occur.
なお、インナーリードと金属プレーンのボンディング
部にはワイヤボンディング性を向上させるため銀めっき
を施すことが多いが、銀マイグレーションによって金属
層間の電気的絶縁性が低下するという問題がある。絶縁
フィルムが薄厚になって金属層間距離が短くなると銀マ
イグレーションによる金属層間の電気的ショートがさら
に発生しやすくなる。The bonding portion between the inner lead and the metal plane is often plated with silver in order to improve the wire bonding property, but there is a problem that the electrical insulation between the metal layers is reduced by silver migration. When the thickness of the insulating film is reduced and the distance between the metal layers is reduced, an electrical short between the metal layers due to silver migration is more likely to occur.
そこで、本発明は上記問題点を解消すべくなされたも
のであり、その目的とするところは、プレス加工で生産
する場合や薄厚の絶縁フィルムを用いる場合等であって
も金属層間の電気的な絶縁性を有効に確保することので
きる多層リードフレームを提供しようとするものであ
る。Therefore, the present invention has been made to solve the above problems, and the purpose thereof is to provide an electric connection between metal layers even when producing by press working or using a thin insulating film. An object of the present invention is to provide a multilayer lead frame capable of effectively securing insulation.
（課題を解決するための手段） 本発明は上記目的を達成するため次の構成をそなえ
る。(Means for Solving the Problems) The present invention has the following configuration to achieve the above object.
すなわち、インナーリードと１枚あるいは複数枚の金
属プレーンを電気的絶縁層を中間に介在させて積層した
多層リードフレームにおいて、前記電気的絶縁層の内側
の端面を、前記インナーリードの内側の端面位置よりも
内方に延出させるとともに、前記電気的絶縁層の外側の
端面を、積層した各金属プレーンの外側の端面位置より
も外方に延出させたことを特徴とする。That is, in a multilayer lead frame in which an inner lead and one or more metal planes are laminated with an electrical insulating layer interposed therebetween, the inner end face of the electrical insulating layer is positioned at the inner end face position of the inner lead. And the outer end face of the electrical insulating layer is extended more outward than the outer end face position of each of the stacked metal planes.
また、インナーリードに、金属プレーンとして、矩形
枠状に形成した電源プレーンと該電源プレーンの下層に
配設されて半導体チップが搭載される接地プレーンとが
前記電気的絶縁層を中間に介在させて積層されているこ
とを特徴とする。Further, a power supply plane formed in a rectangular frame shape as a metal plane on an inner lead and a ground plane disposed below the power supply plane and on which a semiconductor chip is mounted with the electric insulating layer interposed therebetween. It is characterized by being laminated.
また、電気的絶縁層が、接着剤層を有する絶縁フィル
ムにより形成されていることを特徴とする。Further, the electrical insulating layer is formed of an insulating film having an adhesive layer.
（作用） 前記電気的絶縁層の内側の端面を、前記インナーリー
ドの内側の端面位置よりも内方に延出させ、また、前記
金属プレーンの内側の端面位置よりも内方に延出させた
ことにより、電気的絶縁層が薄厚になっても金属層間で
プレスバリが接触したりすることを防止する。また、金
属層間を連絡する電気的絶縁層の表面距離が長くなり、
ボンディング部に銀めっきを施した場合に金属層間の電
気的絶縁性が銀マイグレーションによって低下すること
を防止する。(Function) The inner end face of the electrical insulating layer is extended more inward than the inner end face position of the inner lead, and is extended more inward than the inner end face position of the metal plane. This prevents the press burrs from contacting between the metal layers even when the electrical insulating layer becomes thin. Also, the surface distance of the electrically insulating layer connecting the metal layers becomes longer,
This prevents the electrical insulation between metal layers from being reduced by silver migration when silver plating is applied to the bonding portion.
また、前記電気的絶縁層の外側の端面を、前記金属プ
レーンの外側の端面位置よりも外方に延出させたことに
より、金属プレーンの外周端から延出して設けた突起を
所定のインナーリードに接合する際に、他の金属プレー
ンの外周端面に接触させずに接合できる。Further, by extending the outer end face of the electrical insulating layer outwardly from the outer end face position of the metal plane, the protrusion extending from the outer peripheral end of the metal plane can be provided in a predetermined inner lead. Can be joined without contacting the outer peripheral end surface of another metal plane.
（実施例） 以下、本発明の好適な実施例を図面とともに説明す
る。Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings.
第１図は本発明に係る多層リードフレームに半導体チ
ップを搭載した一実施例を示す説明図である。FIG. 1 is an explanatory view showing one embodiment in which a semiconductor chip is mounted on a multilayer lead frame according to the present invention.
実施例の多層リードフレームは接地プレーン10の上層
に電気的絶縁性を有する絶縁フィルム16aを介して電源
プレーン12を接合し、さらに電源プレーン12の上層に絶
縁フィルム16bを介してインナーリード14を接合してい
る。半導体チップ20は接地プレーン10上に接合される。In the multilayer lead frame of the embodiment, the power supply plane 12 is bonded to the upper layer of the ground plane 10 via an insulating film 16a having electrical insulation, and the inner leads 14 are bonded to the upper layer of the power plane 12 via the insulating film 16b. doing. The semiconductor chip 20 is bonded on the ground plane 10.
電源プレーン12は矩形枠状であり、絶縁フィルム16a
も同じく矩形枠状に形成して接地プレーン10と電源プレ
ーン12とを接合している。ここで、絶縁フィルム16aは
その外周寸法を電源プレーン12の外周寸法よりやや大き
く設定すると共に、内周の矩形枠寸法を電源プレーン12
の内周の寸法よりもやや小さく設定する。これにより、
絶縁フィルム16aの内周の端面が電源プレーン12の内周
の端面位置よりも内側に若干突出することになる。ま
た、絶縁フィルム16aの外周部分でも電源プレーン12の
外周の端面よりも外側に絶縁フィルム16aが若干延出す
る。電源プレーン12とインナーリード14との間に設ける
絶縁フィルム16bについても同様で、矩形枠状に形成し
た絶縁フィルム16bの内周の端面がインナーリード14の
前端面よりも内側に若干延出するように絶縁フィルム16
bの内周側の枠寸法を設定する。The power plane 12 has a rectangular frame shape and has an insulating film 16a.
Similarly, the ground plane 10 and the power plane 12 are joined together in a rectangular frame shape. Here, the outer dimensions of the insulating film 16a are set to be slightly larger than the outer dimensions of the power plane 12, and the inner rectangular frame dimension is set to the power plane 12.
Set slightly smaller than the inner circumference of This allows
The inner peripheral end face of the insulating film 16a slightly protrudes inward from the inner peripheral end face position of the power supply plane 12. In addition, the insulating film 16a slightly extends outside the outer peripheral end surface of the power plane 12 even at the outer peripheral portion of the insulating film 16a. The same is true for the insulating film 16b provided between the power supply plane 12 and the inner leads 14.The inner peripheral end surface of the insulating film 16b formed in a rectangular frame shape slightly extends inward from the front end surface of the inner leads 14. Insulating film 16
Set the inner frame size of b.
図中のＡは、絶縁フィルム16a、16bが電源プレーン1
2、インナーリード14の端面から内方に延出している延
出長さを示す。また、図中のＢは、絶縁フィルム16a、1
6bの外周部分が外方に延出している延出長さを示す。実
施例では絶縁フィルム16a、16bの延出長さをそれぞれ約
1mmに設定した。絶縁フィルムを用いて金属プレーンや
インナーリードを積層する際の位置ずれが最大75μｍ程
度であること、プレスバリの長さが25μｍ程度であるこ
と、さらに樹脂封止性を考慮すると、絶縁フィルム16
a、16bの延出長さは1mm程度が好適である。A in the figure indicates that the insulating films 16a and 16b are the power plane 1
2. Indicates the extension length extending inward from the end face of the inner lead 14. B in the figure is the insulating film 16a, 1
6b shows an extension length in which the outer peripheral portion of 6b extends outward. In the embodiment, the extension lengths of the insulating films 16a and 16b are respectively
It was set to 1 mm. Considering that the positional deviation when laminating metal planes and inner leads using an insulating film is up to about 75 μm, the length of the press burr is about 25 μm, and the resin sealing property is taken into consideration, the insulating film 16
The extension length of a and 16b is preferably about 1 mm.
上記実施例のように、絶縁フィルム16a、16bの内周の
端面を電源プレーン12、インナーリード14の端面よりも
内方に延出させることにより、プレス加工の際にプレス
バリが生じても絶縁フィルム16a、16bの内周側の延出部
分で支持されるから、絶縁フィルム16a、16bをかなり薄
厚にしても、金属層間の接触による電気的ショートを防
止することができる。As in the above embodiment, by extending the inner peripheral end faces of the insulating films 16a and 16b inwardly than the end faces of the power supply plane 12 and the inner leads 14, even if press burrs are generated during press working, insulation is performed. Since the films 16a and 16b are supported by the extended portions on the inner peripheral side, even if the insulating films 16a and 16b are considerably thin, it is possible to prevent electrical short-circuit due to contact between metal layers.
また、第１図で接地プレーン10、電源プレーン12およ
びインナーリード14のボンディング部には銀めっき層22
を設けているが、上記のように絶縁フィルム16a、16bを
内方に延出させたことにより、金属層間の絶縁層表面の
距離が長くなり、銀マイグレーションによる電気的絶縁
性の低下を防止することができる。In FIG. 1, a silver plating layer 22 is provided on the bonding portions of the ground plane 10, the power plane 12, and the inner leads 14.
However, by extending the insulating films 16a and 16b inward as described above, the distance between the surfaces of the insulating layers between the metal layers is increased, thereby preventing a decrease in the electrical insulation due to silver migration. be able to.
実施例では絶縁フィルム16a、16bを幅広に形成して内
周と外周でそれぞれ若干量ずつ絶縁フィルムが延出する
ように設けたが、銀マイグレーションの影響を排除する
等の目的で内周側のみ延出するようにしてもよい。In the embodiment, the insulating films 16a and 16b are formed to be wide and provided so that the insulating films extend slightly by the inner circumference and the outer circumference by a small amount, but only on the inner circumference side for the purpose of eliminating the influence of silver migration and the like. It may be extended.
絶縁フィルムとして外方に若干延出する大きさのもの
を用いる効果としては、電源プレーン12あるいは接地プ
レーン10の外周端に延出して設けた突起とインナーリー
ドの電源リードあるいは接地リードとを接続する際に、
この突起が電源プレーン12などの中間に設けた金属プレ
ーンの外周端面に接触することを防止でき、金属層間で
電気的ショートをおこさずに電源リードあるいは接地リ
ードを接合できるという利点がある。The effect of using the insulating film having a size slightly extending outward is to connect the protrusion provided on the outer peripheral edge of the power plane 12 or the ground plane 10 to the power lead or the ground lead of the inner lead. At that time,
This projection can be prevented from contacting the outer peripheral end surface of a metal plane provided in the middle of the power plane 12 or the like, and has an advantage that a power lead or a ground lead can be joined without causing an electrical short between metal layers.
なお、上記実施例のリードフレームはプレス加工品に
のみ適用されるものではなく、エッチング加工品につい
てももちろん有効である。絶縁フィルムが薄厚化するこ
とにより銀マイグレーションの問題は共通であり、積層
時の位置ずれ、金属プレーンの外周端に設けた突起の接
触による電気的ショートの問題も共通するからである。It should be noted that the lead frame of the above embodiment is not only applied to a press-processed product, but is also effective for an etched product. This is because the problem of silver migration is common due to the thinning of the insulating film, and the problems of misalignment at the time of lamination and electrical short-circuit due to contact of projections provided on the outer peripheral edge of the metal plane are also common.
また、上記実施例の多層リードフレームは接地プレー
ン10、電源プレーン12、インナーリード14をこの順に積
層しているが、これらの配置順はもちろん限定されるも
のではなく、また金属プレーンの設置数等も限定されな
い。In the multilayer lead frame of the above embodiment, the ground plane 10, the power plane 12, and the inner lead 14 are stacked in this order, but the order of arrangement is not limited, and the number of metal planes may be set. Is not limited.
以上、本発明について好適な実施例を挙げて種々説明
したが、本発明はこの実施例に限定されるものではな
く、発明の精神を逸脱しない範囲内で多くの改変を施し
得るのはもちろんのことである。As described above, the present invention has been described variously with reference to preferred embodiments. However, the present invention is not limited to the embodiments, and it is needless to say that many modifications can be made without departing from the spirit of the invention. That is.
（発明の効果） 本発明に係る多層リードフレームによれば、上述した
ように、積層した金属プレーン間および金属プレーンと
インナーリード間の電気的絶縁性を好適に確保すること
ができ、プレス加工によってリードフレームを製造する
場合や電気的特性を向上させるため電気的絶縁層を薄厚
に設ける場合であっても金属層間の電気的ショートが生
じない製品となる等の著効を奏する。(Effect of the Invention) According to the multilayer lead frame according to the present invention, as described above, electrical insulation between the stacked metal planes and between the metal plane and the inner leads can be suitably secured, and the press working is performed. Even when a lead frame is manufactured or when an electrical insulating layer is provided with a small thickness to improve electrical characteristics, a product having no electrical short between metal layers can be provided with remarkable effects.
第１図は本発明に係る多層リードフレームに半導体チッ
プを搭載した実施例の説明図、第２図はプレスバリの発
生状態を示す説明図、第３図は多層リードフレームの従
来例を示す説明図である。 10……接地プレーン、12……電源プレーン、14……イン
ナーリード、16、16a、16b……絶縁フィルム、18a、18b
……プレスバリ、20……半導体チップ、22……銀めっき
層。FIG. 1 is an explanatory view of an embodiment in which a semiconductor chip is mounted on a multilayer lead frame according to the present invention, FIG. 2 is an explanatory view showing a state of occurrence of press burrs, and FIG. 3 is an explanatory view showing a conventional example of a multilayer lead frame. FIG. 10: Ground plane, 12: Power plane, 14: Inner lead, 16, 16a, 16b: Insulating film, 18a, 18b
… Press burrs, 20… Semiconductor chips, 22… Silver plating layer.
Claims (3)
属プレーンを電気的絶縁層を中間に介在させて積層した
多層リードフレームにおいて、 前記電気的絶縁層の内側の端面を、前記インナーリード
の内側の端面位置よりも内方に延出させるとともに、 前記電気的絶縁層の外側の端面を、積層した各金属プレ
ーンの外側の端面位置よりも外方に延出させたことを特
徴とする多層リードフレーム。1. A multilayer lead frame in which an inner lead and one or a plurality of metal planes are laminated with an electrical insulating layer interposed therebetween, wherein an inner end face of the electrical insulating layer is connected to an inner side of the inner lead. A multi-layer lead, wherein the outer end surface of the electrical insulating layer extends outwardly from the outer end surface position of each of the laminated metal planes. flame.
矩形枠状に形成した電源プレーンと該電源プレーンの下
層に配設されて半導体チップが搭載される接地プレーン
とが前記電気的絶縁層を中間に介在させて積層されてい
ることを特徴とする請求項１記載の多層リードフレー
ム。2. A metal plane on an inner lead,
A power supply plane formed in a rectangular frame shape and a ground plane disposed below the power supply plane and having a semiconductor chip mounted thereon are stacked with the electrical insulating layer interposed therebetween. Item 4. The multilayer lead frame according to Item 1.
ィルムにより形成されていることを特徴とする請求項１
または２記載の多層リードフレーム。3. The electrical insulating layer according to claim 1, wherein the electrical insulating layer is formed of an insulating film having an adhesive layer.
Or the multilayer lead frame according to 2.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2235067A JP2966067B2 (en) | 1990-09-04 | 1990-09-04 | Multilayer lead frame |
| US07/753,794 US5235209A (en) | 1990-09-04 | 1991-09-03 | Multi-layer lead frame for a semiconductor device with contact geometry |
| EP91308079A EP0474469B1 (en) | 1990-09-04 | 1991-09-04 | Multi-layer lead frame for a semiconductor device |
| KR1019910015414A KR950001369B1 (en) | 1990-09-04 | 1991-09-04 | Multi-layer lead frame for a semiconductor device |
| DE69125072T DE69125072T2 (en) | 1990-09-04 | 1991-09-04 | Multi-layer leadframe for a semiconductor device |
| HK98100452A HK1001575A1 (en) | 1990-09-04 | 1998-01-20 | Multi-layer lead frame for a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2235067A JP2966067B2 (en) | 1990-09-04 | 1990-09-04 | Multilayer lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04114461A JPH04114461A (en) | 1992-04-15 |
| JP2966067B2 true JP2966067B2 (en) | 1999-10-25 |
Family
ID=16980581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2235067A Expired - Fee Related JP2966067B2 (en) | 1990-09-04 | 1990-09-04 | Multilayer lead frame |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5235209A (en) |
| EP (1) | EP0474469B1 (en) |
| JP (1) | JP2966067B2 (en) |
| KR (1) | KR950001369B1 (en) |
| DE (1) | DE69125072T2 (en) |
| HK (1) | HK1001575A1 (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5556807A (en) * | 1992-02-18 | 1996-09-17 | Intel Corporation | Advance multilayer molded plastic package using mesic technology |
| JPH0653277A (en) * | 1992-06-04 | 1994-02-25 | Lsi Logic Corp | Semiconductor device assembly and its assembly method |
| US5854094A (en) * | 1992-07-28 | 1998-12-29 | Shinko Electric Industries Co., Ltd. | Process for manufacturing metal plane support for multi-layer lead frames |
| US5777265A (en) * | 1993-01-21 | 1998-07-07 | Intel Corporation | Multilayer molded plastic package design |
| JP2931741B2 (en) * | 1993-09-24 | 1999-08-09 | 株式会社東芝 | Semiconductor device |
| US5343074A (en) * | 1993-10-04 | 1994-08-30 | Motorola, Inc. | Semiconductor device having voltage distribution ring(s) and method for making the same |
| US5578869A (en) * | 1994-03-29 | 1996-11-26 | Olin Corporation | Components for housing an integrated circuit device |
| JP2536459B2 (en) * | 1994-09-26 | 1996-09-18 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| GB2293918A (en) * | 1994-10-06 | 1996-04-10 | Ibm | Electronic circuit packaging |
| US5965936A (en) * | 1997-12-31 | 1999-10-12 | Micron Technology, Inc. | Multi-layer lead frame for a semiconductor device |
| KR100253028B1 (en) * | 1994-11-10 | 2000-04-15 | 로데릭 더블류 루이스 | Multi-layer lead frame for a semiconductor device |
| US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
| GB9515651D0 (en) * | 1995-07-31 | 1995-09-27 | Sgs Thomson Microelectronics | A method of manufacturing a ball grid array package |
| US6054754A (en) | 1997-06-06 | 2000-04-25 | Micron Technology, Inc. | Multi-capacitance lead frame decoupling device |
| US6515359B1 (en) * | 1998-01-20 | 2003-02-04 | Micron Technology, Inc. | Lead frame decoupling capacitor semiconductor device packages including the same and methods |
| US6114756A (en) | 1998-04-01 | 2000-09-05 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit leadframes |
| US6414386B1 (en) * | 2000-03-20 | 2002-07-02 | International Business Machines Corporation | Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings |
| KR20030066994A (en) * | 2002-02-06 | 2003-08-14 | 주식회사 칩팩코리아 | Multi-layer lead frame and chip size package using the same |
| US8354743B2 (en) * | 2010-01-27 | 2013-01-15 | Honeywell International Inc. | Multi-tiered integrated circuit package |
| US9741644B2 (en) | 2015-05-04 | 2017-08-22 | Honeywell International Inc. | Stacking arrangement for integration of multiple integrated circuits |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61108160A (en) * | 1984-11-01 | 1986-05-26 | Nec Corp | Semiconductor device with built-in capacitor and manufacture thereof |
| GB2174538A (en) * | 1985-04-24 | 1986-11-05 | Stanley Bracey | Semiconductor package |
| JP2734463B2 (en) * | 1989-04-27 | 1998-03-30 | 株式会社日立製作所 | Semiconductor device |
| JP2744685B2 (en) * | 1990-08-08 | 1998-04-28 | 三菱電機株式会社 | Semiconductor device |
-
1990
- 1990-09-04 JP JP2235067A patent/JP2966067B2/en not_active Expired - Fee Related
-
1991
- 1991-09-03 US US07/753,794 patent/US5235209A/en not_active Expired - Lifetime
- 1991-09-04 KR KR1019910015414A patent/KR950001369B1/en not_active IP Right Cessation
- 1991-09-04 EP EP91308079A patent/EP0474469B1/en not_active Expired - Lifetime
- 1991-09-04 DE DE69125072T patent/DE69125072T2/en not_active Expired - Lifetime
-
1998
- 1998-01-20 HK HK98100452A patent/HK1001575A1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920007164A (en) | 1992-04-28 |
| HK1001575A1 (en) | 1998-06-26 |
| EP0474469A1 (en) | 1992-03-11 |
| DE69125072T2 (en) | 1997-06-19 |
| DE69125072D1 (en) | 1997-04-17 |
| JPH04114461A (en) | 1992-04-15 |
| KR950001369B1 (en) | 1995-02-17 |
| EP0474469B1 (en) | 1997-03-12 |
| US5235209A (en) | 1993-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2966067B2 (en) | Multilayer lead frame | |
| JP3198796B2 (en) | Mold module | |
| JPH0448767A (en) | Resin-sealed semiconductor device | |
| JP2001024145A (en) | Semiconductor device and its manufacture | |
| US10505298B2 (en) | Joint structure of a resin multilayer substrate and a circuit board | |
| JPH06163794A (en) | Multilayer lead frame of metal core type | |
| US20210045241A1 (en) | Resin multilayer substrate and electronic device | |
| KR19990063447A (en) | Semiconductor device and manufacturing method | |
| US11810703B2 (en) | Multilayer coil circuit substrate | |
| JP2001118986A (en) | Semiconductor device and electronic apparatus | |
| JP2001332580A (en) | Semiconductor device and method of manufacturing the same | |
| JP2000012773A (en) | Semiconductor device and its manufacture | |
| WO2011043382A1 (en) | Circuit substrate and method of production thereof | |
| JP2001251057A (en) | Apparatus wherein device is mounted on multilayer printed wiring board, multilayer printed wiring board and device | |
| US10188000B2 (en) | Component mounting board | |
| JP2003283131A (en) | Laminated circuit and its manufacturing method | |
| JP2942790B2 (en) | Multilayer lead frame for semiconductor device | |
| JPH077125A (en) | Multilayer lead frame | |
| JPH01289151A (en) | Integrated circuit device | |
| JPH065771A (en) | Multilayer lead frame and semiconductor device | |
| JP2670568B2 (en) | Semiconductor device | |
| JP2766361B2 (en) | Semiconductor device | |
| JP2514966Y2 (en) | Multilayer leadframe | |
| JP4655300B2 (en) | Lead frame | |
| JP4388168B2 (en) | Resin molded substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080813 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090813 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090813 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100813 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |