JP2953899B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2953899B2
JP2953899B2 JP5027707A JP2770793A JP2953899B2 JP 2953899 B2 JP2953899 B2 JP 2953899B2 JP 5027707 A JP5027707 A JP 5027707A JP 2770793 A JP2770793 A JP 2770793A JP 2953899 B2 JP2953899 B2 JP 2953899B2
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
semiconductor element
semiconductor
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5027707A
Other languages
Japanese (ja)
Other versions
JPH06244360A (en
Inventor
隆幸 吉田
賢造 畑田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5027707A priority Critical patent/JP2953899B2/en
Publication of JPH06244360A publication Critical patent/JPH06244360A/en
Application granted granted Critical
Publication of JP2953899B2 publication Critical patent/JP2953899B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
半導体実装技術における半導体素子の積層実装技術に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technology for stacking semiconductor elements in a semiconductor mounting technology.

【０００２】[0002]

【従来の技術】近年、電子機器は高性能化、高機能化、
小型化が著しく、そこに実装される半導体素子も高性能
化が進み、また高密度実装されることが要求されてい
る。このため、半導体素子を３次元的に実装するという
要求がＩＣ、メモリーカードに代表される薄型、大容量
機器において顕著になってきている。2. Description of the Related Art In recent years, electronic devices have become more sophisticated and more sophisticated.
The miniaturization is remarkable, and the performance of the semiconductor elements mounted thereon is also improved, and it is required that the semiconductor elements be mounted at a high density. For this reason, the demand for three-dimensionally mounting semiconductor elements has become remarkable in thin, large-capacity devices represented by ICs and memory cards.

【０００３】以下図面を参照しながら、上記した従来の
半導体素子の３次元実装方法の一例について説明する。An example of the above-described conventional three-dimensional semiconductor device mounting method will be described with reference to the drawings.

【０００４】図３は従来の３次元実装の断面構成図を示
すものである。図３において、４１は配線基板、４２は
複数の半導体素子（または、単にチップと呼ぶこととす
る）、４３は実装に用いられたＴＡＢリード、４４は全
体の封止に用いられた絶縁封止樹脂である。FIG. 3 shows a sectional view of a conventional three-dimensional mounting. In FIG. 3, reference numeral 41 denotes a wiring board; 42, a plurality of semiconductor elements (or simply referred to as chips); 43, TAB leads used for mounting; and 44, insulating sealing used for overall sealing. Resin.

【０００５】図４において、図３の実装体の組立方法を
説明する。まず図４（ａ）に示すように、複数の半導体
素子４２に転写バンプ法によりＴＡＢ用フィルムキャリ
ア４５のインナーリード４６を接続する。その後、複数
の半導体素子４２のそれぞれの非共通端子のＴＡＢ用フ
ィルムキャリアのアウターリード４７を切断する。次
に、ＴＡＢフィルムキャリア４５に実装された半導体素
子４２を配線基板４１の電極パッド４８とＴＡＢフィル
ムキャリア４５のアウターリード４７を位置合わせし積
層する。その後、ボンディングツール４９によりアウタ
ーリード４７と配線基板４１の電極パッド４８を一括に
加圧、加熱し接合する。最後に、アウターリード４７の
外側のテープ部分を取り除き、絶縁樹脂４４により全体
を封止することにより、図３に示す３次元の実装体が完
成する。この様な製造方法は、例えば特開平２−２９０
０４８号公報に記載されている。Referring to FIG. 4, a method of assembling the package of FIG. 3 will be described. First, as shown in FIG. 4A, the inner leads 46 of the TAB film carrier 45 are connected to the plurality of semiconductor elements 42 by the transfer bump method. After that, the outer leads 47 of the TAB film carrier of the non-common terminals of the plurality of semiconductor elements 42 are cut. Next, the semiconductor element 42 mounted on the TAB film carrier 45 is laminated by aligning the electrode pads 48 of the wiring board 41 with the outer leads 47 of the TAB film carrier 45. Thereafter, the outer leads 47 and the electrode pads 48 of the wiring board 41 are collectively pressurized and heated by a bonding tool 49 to be joined. Finally, the tape portion outside the outer leads 47 is removed, and the whole is sealed with the insulating resin 44, thereby completing the three-dimensional mounting body shown in FIG. Such a manufacturing method is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-290.
048.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、アウターリード４７と配線基板４１の電
極パッド４８とを正確に位置合わせしなければならず、
またアウターリード４７のボンディングにも特殊なボン
ディングツール４９を使用しなければならないといった
問題点があり、またチップ間の絶縁層が必要であり、イ
ンナーリード４６および層間絶縁樹脂の分だけ全体の厚
みが厚くなるといった問題を有していた。However, in the above structure, the outer leads 47 and the electrode pads 48 of the wiring board 41 must be accurately aligned.
In addition, there is a problem that a special bonding tool 49 must be used for bonding the outer leads 47. Further, an insulating layer between chips is required, and the total thickness is reduced by the inner leads 46 and the interlayer insulating resin. There was a problem that it became thick.

【０００７】本発明は上記問題点に鑑み、複雑な位置合
わせ工程を必要とせず、チップの厚みのみでチップ積層
が可能な３次元実装形態を提供するものである。SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a three-dimensional mounting mode in which a chip can be stacked only by the thickness of the chip without requiring a complicated alignment step.

【０００８】[0008]

【課題を解決するための手段】上記問題点を解決するた
めに本発明では、一主面の電極パッドにリード、または
ワイヤが接続された構造を持つ半導体素子片の、他面の
少なくとも電極パッド領域が切削され、他の部分に対し
薄くなるように段切りが形成された半導体素子片の複数
個を積層し、前記電極パッドに接続されたリードを回路
基板に接続した半導体装置を提案する。このとき、第一
の半導体素子片の第一の段部に第二の半導体素子片の電
極パッドとこれに接続されたリードの一部が配置され
る。According to the present invention, there is provided a semiconductor device having a structure in which a lead or a wire is connected to an electrode pad on one main surface, and at least an electrode pad on the other surface. A semiconductor device is proposed in which a plurality of semiconductor element pieces, each of which has a region cut and stepped so as to be thinner than other portions, are stacked, and leads connected to the electrode pads are connected to a circuit board. At this time, the electrode pad of the second semiconductor element piece and a part of the lead connected thereto are arranged on the first step portion of the first semiconductor element piece.

【０００９】[0009]

【作用】本発明は上記した構成により、チップの積層に
おいて、第一の半導体素子片の第一の段部に第二の半導
体素子片の電極パッドとこれに接続されたリードの一部
を配置する構成を繰り返すため、また、チップのパッシ
ベーシン膜をチップ間の絶縁膜に利用することによりチ
ップ厚さのチップ３次元積層実装を可能とすることがで
きる。According to the present invention, the electrode pad of the second semiconductor element and a part of the lead connected to the electrode pad are arranged on the first step of the first semiconductor element in the stacking of the chips. In order to repeat the configuration described above, it is possible to use the passive basin film of the chip as an insulating film between the chips, thereby enabling a three-dimensional stack mounting of the chip having the chip thickness.

【００１０】[0010]

【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。An embodiment of the present invention will be described below with reference to the drawings.

【００１１】図１は本発明の実施例における３次元実装
形態の断面図を示すものである。図１において、１は配
線基板、２は第１の半導体素子（または、単にチップと
呼ぶこととする。）、３は第１のチップの上に積層され
る裏面が切削された複数のチップ、４はワイヤ（実施例
ではリードではなくワイヤを用いた場合をモデルに説明
する。）、５は絶縁封止樹脂、６は切削された段部を表
す。FIG. 1 is a sectional view of a three-dimensional mounting form according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a wiring board, 2 denotes a first semiconductor element (or simply referred to as a chip), 3 denotes a plurality of chips each having a rear surface cut on the first chip, Reference numeral 4 denotes a wire (in the embodiment, a case where a wire is used instead of a lead will be described as a model.) Reference numeral 5 denotes an insulating sealing resin, and reference numeral 6 denotes a cut step.

【００１２】以上のように構成された半導体装置の組立
工程について、以下図２を用いて説明する。The process of assembling the semiconductor device configured as described above will be described below with reference to FIG.

【００１３】図２（ａ）に示すように、第１のチップ２
（裏面が切削されていなくてもかまわない）を配線基板
１に接着し、対応する電極どうしをワイヤにより電気的
に接続する。次に、図２（ｂ）に示す様に、第１のチッ
プ上に積載される第２、第３といったチップ３の裏面周
縁部をダイサーにより切削し、段部６を形成する。ワイ
ヤ４が接続される電極パッド７は、この周縁部に形成さ
れている。その後、図２（ｃ）に示すように、この第
２、第３のチップ３をチップ１上に積層し、対応する電
極どうしをワイヤにより接続する。図２（ｄ）は、図２
（ｃ）の上面図である。最後に、図２（ｅ）に示すよう
に、全体を絶縁樹脂により封止する。これにより半導体
素子２、３の配線基板１への３次元的実装が完了する。As shown in FIG. 2A, the first chip 2
(It does not matter if the back surface is not cut) is bonded to the wiring board 1, and the corresponding electrodes are electrically connected by wires. Next, as shown in FIG. 2B, the peripheral edge of the back surface of the second or third chip 3 mounted on the first chip is cut by a dicer to form a stepped portion 6. The electrode pad 7 to which the wire 4 is connected is formed on this peripheral portion. Thereafter, as shown in FIG. 2C, the second and third chips 3 are stacked on the chip 1 and the corresponding electrodes are connected by wires. FIG.
It is a top view of (c). Finally, as shown in FIG. 2E, the whole is sealed with an insulating resin. Thus, the three-dimensional mounting of the semiconductor elements 2 and 3 on the wiring board 1 is completed.

【００１４】なお、本実施例では、第２、３のチップ
は、第１のチップを基板上に載置した後に段差を形成し
ているが、第１のチップを基板上に載置する前に予め段
差を形成しておいても勿論かまわない。In this embodiment, the second and third chips form a step after the first chip is mounted on the substrate, but before the first chip is mounted on the substrate. Of course, a step may be formed beforehand.

【００１５】また、上記実施例においては、第２、３の
チップにおける電極パッドは平坦な主面側に形成されて
いるが、段差６側に形成してもよいことは勿論である。
更には、図２における最下層のチップ２においても、周
縁部に段差があっても何等差し支えはなく、そうするこ
とにより、使用する半導体素子の形状を一種類に統一す
ることができるので、自動組立における半導体素子の形
状判別操作が省略できる等の利点が得られる。In the above embodiment, the electrode pads of the second and third chips are formed on the flat main surface side, but may be formed on the step 6 side.
Furthermore, even in the lowermost chip 2 in FIG. 2, there is no problem even if there is a step at the peripheral portion. By doing so, the shape of the semiconductor element to be used can be unified into one type, so that automatic An advantage is obtained that the operation of determining the shape of the semiconductor element in assembly can be omitted.

【００１６】[0016]

【発明の効果】以上のように本発明では、 一主面の電
極パッドにリード、またはワイヤが接続された構造を持
つ半導体素子片の、他面の少なくとも電極パッド領域が
他の部分に対し薄くなるように段切りが形成された半導
体素子片の複数個を第一の半導体素子片の第一の段部に
第二の半導体素子片の電極パッドとこれに接続されたリ
ードの一部が配置されるように積層し、前記電極パッド
に接続されたリードを回路基板に接続した半導体装置を
提案することにより、チップの積層においてチップのパ
ッシベーシン膜をチップ間の絶縁膜に利用することによ
りチップ厚さのチップ３次元積層実装を可能とすること
ができる。As described above, according to the present invention, at least the electrode pad region on the other surface of a semiconductor element piece having a structure in which a lead or a wire is connected to an electrode pad on one main surface is thinner than other portions. A plurality of semiconductor element pieces with step cuts formed are arranged on the first step portion of the first semiconductor element piece with the electrode pads of the second semiconductor element piece and some of the leads connected thereto. The present invention proposes a semiconductor device in which the leads connected to the electrode pads are connected to a circuit board so that the passive basin film of the chip is used as an insulating film between the chips in stacking the chips. Chips can be three-dimensionally stacked.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例における半導体素子の構成を
示す断面図FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.

【図２】同実施例半導体素子の製造工程図FIG. 2 is a manufacturing process diagram of the semiconductor device of the embodiment.

【図３】従来例における半導体素子の構成を示す断面図FIG. 3 is a cross-sectional view showing a configuration of a semiconductor element in a conventional example.

【図４】同従来例半導体素子の製造工程図FIG. 4 is a manufacturing process diagram of the conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 配線基板 ２ 裏面が第１の半導体素子 ３ 第１のチップの上に積層される複数のチップ ４ ワイヤ ５ 絶縁封止樹脂 DESCRIPTION OF SYMBOLS 1 Wiring board 2 The back surface of a 1st semiconductor element 3 The some chip laminated | stacked on a 1st chip 4 Wire 5 Insulation sealing resin

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】複数個の半導体素子を回路基板に積層して
なる半導体装置であって、積層される半導体素子は、そ
の周縁部が中央部に対して薄肉に形成されると共に前記
周縁部にはリード、またはワイヤが接続される電極パッ
ドが形成されており、このように構成された半導体素子
を積層すると共に、前記電極パッドに接続されたワイヤ
もしくはリードを前記回路基板に接続したことを特徴と
する半導体装置。1. A semiconductor device comprising a plurality of semiconductor elements stacked on a circuit board, wherein the stacked semiconductor elements have a peripheral portion formed to be thin with respect to a central portion, and have a peripheral portion formed on the peripheral portion. Is formed with an electrode pad to which a lead or a wire is connected. The semiconductor element thus configured is laminated, and a wire or a lead connected to the electrode pad is connected to the circuit board. Semiconductor device.
JP5027707A 1993-02-17 1993-02-17 Semiconductor device Expired - Fee Related JP2953899B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5027707A JP2953899B2 (en) 1993-02-17 1993-02-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5027707A JP2953899B2 (en) 1993-02-17 1993-02-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06244360A JPH06244360A (en) 1994-09-02
JP2953899B2 true JP2953899B2 (en) 1999-09-27

Family

ID=12228471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5027707A Expired - Fee Related JP2953899B2 (en) 1993-02-17 1993-02-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2953899B2 (en)

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