JP2953739B2 - Buffer control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a buffer control system, and more particularly to an input buffer control system which is advantageously applied to an electronic device such as a switch network of a packet switch.

2. Description of the Related Art Conventionally, as a communication path switch of a packet switch using an input buffer, there is a "packet switching system" described in, for example, JP-A-1-123550. The switch network of this system is provided between an input port and an output port, and aims to efficiently transfer an input packet. The switch network has a buffer, and an input port is connected to an input of the buffer. A qualifying network and a final network are connected in parallel to the output of the buffer, and an output port is connected to the final network.

The qualifying network buffer accumulates packets from the input ports, assembles qualifying packets of only destination information including output port numbers, and outputs the qualifying packets to the qualifying network. When there are a plurality of qualifying packets having the same output port number, the qualifying network selects one of them and selects only qualifying packets having different output terminal numbers. Then, the selected packet is notified to the buffer as winning.

The buffer outputs the same qualifying packet again in the case of winning, and outputs another packet in the case of losing.
In the prior art, this qualifying output is repeated several times to increase the packets of different destinations and output them to the qualifying network,
This eliminates packet loss in the final network and improves throughput.

(Problems to be Solved by the Invention) However, in such a system in the related art, although discarding of packets in the switch network is reduced, when packets having a large capacity lost in the preliminary round are concentrated in a specific buffer, the capacity is reduced. In some cases, the probability of discarding a packet due to an overrun increases. Further, when the buffer capacity corresponding to the input port is increased to solve this problem, there is a disadvantage that the hardware amount of the entire system increases.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks, and a buffer control method for preventing discarding of packets stored in a buffer without increasing the buffer capacity of an input port in a packet switch comprising a switch network including a qualifying network and a qualifying network. The purpose is to provide.

(Means for Solving the Problems) According to the present invention, in a buffer control method of a packet switch having a buffer for temporarily storing input information on an input side, a packet switch to which this method is applied is used in a switching control. Receiving a predetermined packet including an indication of the buffer usage, detecting means for detecting the usage of the buffer from the packet, receiving a detection result from the detection means, and notifying the detection result to a communication path switch at a subsequent stage of the buffer And a control unit that, when the communication path switch receives a notification that the buffer usage is large, preferentially processes a packet transmitted from the buffer.

According to the present invention, in a buffer control method in a data processing device having a buffer for temporarily storing input information on an input side, a data processing device to which this method is applied includes a plurality of buffers having buffers for storing input information. A data processing means, a bus connected to the plurality of data processing means and transmitting the information output from the data processing means in a multiplexed manner, and detecting a data holding amount of each of the plurality of data processing means; And control means for giving priority to information from the data processing means having a large data holding amount and outputting the information to the bus.

(Operation) According to the present invention, upon switching control, a predetermined packet including the buffer usage is received, the buffer usage of the packet to be actually transferred is detected from this packet, and the buffer usage is determined from the detection result. Priority is given to packets that are heavily used.

(Embodiment) Next, an embodiment of a buffer control system according to the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a packet to be input to the switch network is temporarily stored in an input buffer, a buffer use indication bit is given to the packet, and the packet is output to the switch network. When a packet is input, the switch network preferentially processes a packet having a large buffer usage to prevent discarding of the packet in the input buffer.

FIG. 2 shows the configuration of a packet switch network showing an embodiment of the buffer control system of the present invention. The switch 26, which is a self-routing multistage switch network, is provided between input ports 100 to 107 and output ports 130 to 137. The switch 26 has packet buffers 220 to 227,
The input side is connected to input ports 100 to 107, respectively, and the output side is connected to a preliminary network 24 and a final network 25 in parallel. The final network 25 also has an output port on its output side.
130 to 137 are connected.

FIG. 1 shows a functional block diagram of the packet buffers 220 to 227 as a packet buffer 200. The packet buffer 200 includes a buffer control unit 201 and a buffer 20.
2. It is composed of a buffer usage detecting circuit 203 and a qualifying packet assembling circuit 204, which are connected as shown in FIG.

Packets input from the input ports 100 to 107 (FIG. 2) are temporarily stored in the buffer 202. The control unit 201 controls the buffer 202, the detection circuit 203, and the packet assembling circuit 204 to assemble the qualifying packet 214 shown in FIG. The assembling circuit 204 sets the valid bit U to “in use (= 0)” based on the presence or absence of a packet in the buffer 202.
Alternatively, “empty (= 1)”. And the assembly circuit 204
Input the output terminal number AD0 from the control unit 201, and
The non-winning bit W indicating the remaining winnings input from is set to non-winning (= 1) at the first time. In addition, the assembly circuit
204 inputs the usage amount indicating bit B of the buffer 202 from the detection circuit 203, assembles a qualifying packet, and outputs it to the qualifying network 24. If there is no packet in the packet buffer 202, the packet is output as an empty packet of the valid bit U.

Upon receiving the qualifying packet 214, the qualifying network 24 selects one of the packets with the largest buffer usage from among the packets having the same output port number by comparing the output port number AD0 except for the empty packet. Then, qualifying packets having different output port numbers are selected, and this is notified to the control unit 201 of each packet buffer 200.

The control unit 201 inverts (= 0) the non-winning bit W in the case of the remaining winning, and outputs it to the qualifying network again. In the case of a loss, the storage of this packet is continued, and another packet to be transmitted next is output to the qualifying network. After repeating this several times, the control unit 201 instructs the packet assembling circuit 204 to assemble the final packet 216 (FIG. 3).
Is output to the final net 25. The final packet 216 is composed of a valid bit U indicating whether the packet is an empty packet or a used packet, an output port number AD1, destination subscriber information AD2, and information I.

In the qualifying packet 214 shown in FIG. 3, the non-winning bit W is the same as the packet having the same output port number AD0.
The remaining packet becomes "0" and its value becomes smaller than that of the lost packet.

Packets input from the input ports 100 to 107 to the self-routing multistage switch 26 are temporarily
It is stored in 0 to 227. The packet buffers 220 to 227 perform control to send individually stored packets to the qualifying network 24 first. Packets input to the qualifying network 24 from the packet buffers 220 to 227 are compared in the sorting network A 20 with respect to the size of all qualifying packets input to the network 20.

At this time, the number to be compared is, for example, when the buffer usage amount indication bit B is 1 bit, the output port number AD0 is quadrupled and the unwinned bit W is doubled,
A buffer usage amount indicating bit B is added to this, and a valid bit U is added to the most significant bit. By this processing, the numbers for comparing the sizes of the qualifying packets are preceded by a valid bit U, followed by an output port number, a non-winning bit, and a buffer usage amount indicating bit B.

Specifically, in the qualifying packet shown in FIG. 3, an empty packet (valid bit = 1) is treated as "larger" than a busy packet. Also, among the used packets having the same output port number AD0, the qualifying packet (unwinned bit = 0) already won in the qualifying network 24 is “small”.
Is treated as Further, in the qualifying packet having the same output port number AD0 and the non-winning bit being “1”, the qualifying packet (buffer usage amount indication bit = 0) output from the packet buffer having a large buffer usage is treated as “small”. As a result, the qualifying packet 214 of the packet buffer in which many packets are stored wins preferentially.

Here, for example, if the buffer usage amount indicating bit B is 2 bits, four types of usage amounts can be defined. That is, for example, the buffer usage amount indicating bit B is set to “11” when the buffer usage amount is 1/4 or less, “10”,
Set "01" for / 2 to 3/4 and "00" for 3/4 or more. In this case, the output port number AD0 is multiplied by 8, the non-victory bit W is quadrupled, the buffer indication bit B is added, and the valid bit U is added as the most significant bit. Is the qualifying packet 214, the size can be compared even when the buffer usage amount indicating bit B is 2 bits. Similarly, an arbitrary number of bits can be used for the buffer usage amount indicating bit B as needed.

The sorting network A 20 that has received the qualifying packet configured in this way determines the size of the packet by comparing the bit sequence of the packet in order from the higher order, and according to the size of the number of the output terminal of its own network. The qualifying packet is output to output terminals 240 to 246. These output terminals, that is, the discarding network 21 that has input the qualifying packet to its own input terminal, compares the output port number AD0 of the qualifying packet 214 of the adjacent input terminal, and if they are the same, inputs to the input terminal whose input terminal number is larger. Discard the dropped packet.

Also, the output port number is the same and the unwinned bit is “1”.
In the packet No., a packet having a small value of the buffer usage amount indicating bit B is not discarded, and as a result, a qualifying packet with a large buffer usage remains. For the packet that survived this comparison, the qualifying packet follows the route that has been transmitted so far, and notifies the packet buffer of the surviving packet.

The buffer that has received the remaining winning notification sets the unwinning bit of the remaining winning packet to “0” and outputs this packet to the qualifying network 24 again. The buffer which has not received the winning remaining report outputs the unwinned bit W of the other qualifying packet 214 in the buffer to the qualifying network 24 as "1". The buffer sends the qualifying packet 214 several times to the qualifying network 24 while sending the qualifying packet once to the qualifying network 25.
Output to 25.

The final packet 216 (FIG. 3) input to the final network 25 is compared with the output port number AD2 of the routing tag 154 in the sorting network B22. Output to terminal. The routing network 23 outputs the input packet in a non-block manner to the output ports 130 to 137 of the output port number by the routing tag 154. In this embodiment, the example in which the switch network is composed of the qualifying network 24 and the qualifying network 25 has been described. However, even in a self-routing switch network without the qualifying network 24, the buffer usage is incorporated by incorporating the buffer usage into the packet. Can be preferentially processed.

Next, as a second embodiment of the present invention, FIG. 4 shows a configuration when a buffer control method is applied to a data processing device. A plurality of data processing apparatuses 1 to n of the distributed processing system temporarily store input data in buffers 1B to nB, respectively, and then compete and output data to one bus H. The bus multiplexes data of each apparatus. Transfer. The control circuit 11 detects the buffer usage of each device from the line b, and gives a priority to the device having a large buffer usage to output data. With this method, it is possible to prevent overflow without increasing the capacity of the buffers 1B to 1N as compared with the conventional data multiplex transfer method due to competition.

As described above, the present invention is not limited to a packet switch, but can be applied to an electronic device that processes data in a plurality of buffers.

(Effects of the Invention) As described above, according to the present invention, it is possible to preferentially process a qualifying packet from a packet having a large buffer usage amount by incorporating the buffer use state into the qualifying packet information. This makes it difficult for packets arriving at the buffer to be discarded without increasing the buffer capacity, and if the packets arriving at the buffer have the same discard easiness, the capacity of the buffer can be reduced. The amount of hardware of the applied system as a whole can be reduced.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of a packet buffer in a buffer control system according to the present invention. FIG. 2 is a configuration diagram when the packet buffer shown in FIG. 1 is applied to a switch network of a packet switch. FIG. 3 is a configuration diagram of a qualifying packet and a final packet in the embodiment shown in FIG. 1, and FIG. 4 is a configuration diagram showing a configuration when a buffer control system according to the present invention is applied to a data processing device. Description of Signs of Main Parts 1 to n Data processing device 1B to nB, 202 Buffer 11 Control circuit 20, 22 Sorting network 21 Discard network 23 Routing network 26 Self-routing multistage Switches 100 to 107 Input ports 130 to 137 Output ports 200, 220 to 227 Packet buffer 201 Buffer controller 203 Buffer usage detection circuit 204 Packet assembling circuit AD0 Target output port number B …… Buffer usage amount indication bit U …… Effective bit W …… Unwinned bit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshikatsu Uetake 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-1-123550 (JP, A) International Publication 89/9521 (WO, A1) IEICE Technical Report SE87-132 IEICE Technical Report CS89-13 IEICE, Vol. J72-B-I No. 2 pp.109-117 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/56, 12/28

Claims (1)

(57) [Claims] 1. A packet buffer for buffering a packet for each input port, a selected network for switching a packet connected to each packet buffer to a target output port, and a selected network connected to each of the packet buffers. In a buffer control method for a packet switch including a qualifying network for selecting a packet to be input, the packet buffer includes a buffer unit for temporarily storing packet information input from the input port, and a buffer used by the packet unit. Detecting means for generating and outputting display information of buffer usage based on the detected usage, receiving display information of buffer usage output from the detecting means, and receiving the received display information. Notification means for generating and outputting predetermined qualifying packets, including: Control means for generating a qualifying packet based on the received qualifying packet and sending the qualifying packet to the qualifying network. The qualifying network receives a qualifying packet including display information indicating that the used amount is large from the notifying means. A buffer control method, comprising: processing means for processing the received qualifying packet preferentially and sending the preferentially processed qualifying packet to the control means.