JP2953381B2 - Monitoring method of shared buffer type switch using CAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a monitoring system for a shared buffer type switch using a CAM.
In a shared buffer type switch using a CAM used in an ATM communication device, the present invention relates to a method of monitoring an address chain error, which is a unique problem of the shared buffer, and recovering the error when an error occurs.

[0002]

2. Description of the Related Art Conventionally, ISDN (Integrated Services Digital Network) has been provided, but recently there is B-ISDN (Broadband ISDN) having a higher transmission speed. This B
-ISDN is an A (ATM) switch for ATM (Asynchronous Transfer Mode)
It is realized by a TM communication device and transfers information in units called cells. One of the methods for realizing this ATM is a CAM (Content Addressable M).
memory) using a shared buffer type switch.

FIG. 2 is a block diagram showing an example of a conventional shared buffer type switch using a CAM.

[0004] The physical address of the CAM 202 matches the cell address of the cell buffer 201. CAM20
2 holds information on a cell block in the cell buffer 201. The memory 203 includes a cell buffer 201
Is a memory or a register that holds information on queues that exist in the server. The buffer control unit 204 writes and reads ATM cells to and from the cell buffer 201 using information in the CAM 202 and the memory 203.

FIG. 3 is a diagram showing a data format in the CAM 202 shown in FIG.

The address 301 is the address of the CAM 202 and corresponds to the cell address of the cell buffer 201. Valid 302 indicates whether the ATM cell stored at the cell address 301 in the cell buffer 201 is a valid cell or an invalid cell. A valid cell is a cell to be read, and an invalid cell is an empty block, indicating that a new input ATM cell may be written. The port 303 indicates an output port to which the cell address 301 is to be transferred. pri
D304 indicates a QOS (Quality Of Service) class viewed from the delay priority of the cell address 301. priL 305 indicates the QOS class from the viewpoint of the discard priority of the cell address 301. There is a queue for each output port that is identified by priD 304. Therefore, a queue of “maximum number of output ports × maximum number of delay classes” exists in the cell buffer 201. seq
Reference numeral 306 denotes a sequence number indicating the order of cells in the queue of the delay class indicated by priD 304 among the cells transferred to the output port indicated by port 303, and takes consecutive numbers.

FIG. 4 is a view for explaining information contained in the memory 203 shown in FIG.

The memory 203 is divided into areas corresponding to the maximum number of output ports. The area corresponding to each output port is further divided into areas corresponding to the maximum number of delay classes. The area corresponding to each delay class includes three registers. Head
The sequence number 401 indicates the address of the ATM cell located at the head of the delay class queue of the corresponding output port number of the register in the cell buffer 201.
Similarly, the tail sequence number 402 indicates the last address of the same queue in the cell buffer 201. The maximum sequence number is the maximum queue length allowed in the system. The queue length 403 indicates the length of the queue of this delay class, and is the difference between the head sequence number 401 and the tail sequence number 402.

Next, the buffer control unit 204 shown in FIG.
The write operation and the read operation of the ATM cell into and from the cell buffer 201 will be described.

When an ATM cell is input, the cell buffer 201
Find an unused cell block in and write it to that block. When the ATM cell is written into the cell buffer 201, the ATM cell is connected to the end of the queue to which the ATM cell belongs, and the CAM 20
2 and the queue information in the memory 203 is updated.

The output of the ATM cell is periodically read to all output ports as a general rule of reading the shared buffer. Regarding reading to each output port, one of the delay classes to be read to the output port is selected according to the priority rule between the delay classes defined by the system, and the first cell is selected. Is read.

Here, the processing at the time of inputting an ATM cell will be described in detail.

The buffer control unit 204 performs a search in the CAM 202 using a data key for which “Valid 302 = invalid”. The address where “Valid 302 = invalid” indicates the cell address of a cell block that is empty in the cell buffer 201. At the same time, the output port, delay class,
Determine the discard class. Since this determination processing differs depending on the processing method of the routing information depending on each system, a detailed description is omitted here. In the memory 203, the output port number and the tail sequence number 402 of the area corresponding to the delay class are added by 1 to obtain a new sequence number. If the sequence number exceeds the maximum queue length allowed by the system, it is reset to "0". The queue length 403 is also incremented by one. Operationally, the queue length 403 is information that is added or subtracted one by one, and there is no situation in which the queue length 403 is incremented to 0 as in the sequence number. Next, for the address 301 obtained above in the CAM 202, “Valid 302 = valid”, “port 303 / priD 304 / priL3
05 = value determined above "and seq 306 = tail sequence number newly obtained above are written. At the same time, the corresponding tail sequence number 402 of the memory 203 is added to the new value (1 is added. ), And the corresponding queue length 403 in the memory 203 is set to a new value (1
Update). The ATM that has arrived
Writing of Cell to Cell Buffer 201 and CAM2
02 and the updating of the information in the memory 203 ends.

Next, details of the processing at the time of reading the ATM cell will be described.

Which output port a cell is to be read from is determined by
This processing depends on the system, and is defined periodically and semi-fixedly. Here, it is assumed that the system specifies to read a cell for a certain output port.

The queue length 4 of all delay classes in the area corresponding to the output port in the memory 203
From 03, it is determined which cell of the delay class should be read. Since this determination depends on the conditions of each system, a detailed description is omitted here. After the delay class is determined, the head sequence number 401 of the delay class is obtained. Next, the “Hea” thus obtained is
d sequence number, “output port number”, and “delay class” are set to seq306, port303, and priD30.
4 and “Valid 302 = valid”, and the CAM 202 is searched using this data key. The address 301 obtained as a result of the search is stored in the cell buffer 20.
This is the cell address where the cell to be read from 1 is stored. The cell buffer 201 is determined by the cell address.
From the cell. At the same time, the information in the CAM 202 and the memory 203 is updated in order to update the information of the queue to which the read cell belongs. In the CAM 202, the read cell address is set as the address 301 and “Vali
d302 = invalid ". In the memory 203,
One is added to the value of the head sequence number 401 of the delay class of the output port used for reading. The head sequence number 401 is reset to "0" when it exceeds the maximum queue length allowed for the system. Queue length 40
3 is updated by subtracting 1 from it. Operationally, the queue length 403 is always “0” or more and “the maximum queue length allowed in the system”.
It is as follows. Thus, the reading process is completed.

[0017]

The problems of the prior art described above are that when an error occurs in the CAM 202, which is information for managing the queue in the cell buffer 201, and the information in the memory 203, the entity of the queue and the management information Therefore, it is not possible to avoid obstacles caused by the differences. The failure accompanying this error will be described below.

FIG. 5 is a table showing the types of failures caused by errors in the information in the CAM 202 and the memory 203 shown in FIG. FIG. 6 is a diagram showing a phenomenon corresponding to each of the faults shown in FIG. 5, and is shown in association with the item numbers in FIG.

Among the faults shown in FIG. 5, the fault No. 6 disappears due to only a temporary cell loss, but the faults No. 1 to 5 are faults unless the inconsistency between the management information and the entity is removed. Will remain forever.

FIG. 7 is a table showing which of the respective failures shown in FIG. 5 when an error occurs in each of the parameters shown in FIG. 3 and FIG. FIG. 7 shows a case where the validity signal 302 remains “valid” and does not change from the item number 3 onward.

When an error occurs in a complex manner (with a plurality of parameters), the condition is governed by the condition having the higher priority. The priority of each item number in FIG. 7 is, in order of “high → low”, item numbers 1 and 2 (exclusion event) → 3 → 4 → 6, 7,
8 and 9.

Conventionally, such a problem occurs because there is no means for detecting and recovering a mismatch between the substance of the queue in the cell buffer 101 and the management information in the CAM 202 and the memory 203.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a shared buffer type switch using a CAM capable of detecting and recovering a mismatch between an entity of a queue in a cell buffer and management information in a CAM and a memory. The purpose of the present invention is to provide a monitoring method.

[0024]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a data key (content key) in a CAM.
In the search function "t) → address", two types of search result information can be output to the outside. One is a multiple address detection signal and the other is an address non-detection signal. The unit has a duplicate data key FIFO that holds a plurality of address detection signals and a data key at that time, and the output of the FIFO is processed by a recovery processing unit that recovers from a failure. The output of this table is also processed by the recovery processing unit that recovers the failure.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment to which a monitoring method of a shared buffer type switch using a CAM according to the present invention is applied.

The physical address of the CAM 102 matches the cell address of the cell buffer 101. CAM10
2 holds information on the cell block in the cell buffer 101. The memory 103 includes a cell buffer 101
Is a memory or a register that holds information on queues that exist in the server. The buffer control unit 104 uses the information in the CAM 102 and the memory 103 to write and read ATM cells to and from the cell buffer 101. In the present embodiment, a queue monitoring unit 105 described later is newly provided.

The data format in the CAM 102 is
As in the CAM 202 shown in FIG. 2, the configuration is as shown in FIG. Also, the information included in the memory 103 is as shown in FIG. 4 similarly to the memory 203 shown in FIG.
Here, detailed description is omitted. .

FIG. 8 is a diagram showing input / output signals of the CAM 102 shown in FIG.

The CAM 102 stores “data (content
In t) → address ”search, a new search result different from the conventional one is output. As shown in FIG. 8, the CAM 102 performs mode control of performing a normal memory operation or a search function. In the case of a search function, it receives an address signal 501 and outputs a data signal 503. As a result of the search, if there are a plurality of corresponding addresses, a multiple address detection signal 504 is provided.
And outputs an address non-detection signal 505 when there is no corresponding address.

FIG. 9 is an internal block diagram of the queue monitoring unit 105 shown in FIG.

As shown in FIG. 9, the queue monitoring unit 105 includes a duplicate data key FIFO 602 and a recovery processing unit 60.
3, the abnormal queue monitoring table 604, and the recovery processing unit 605
And a processing control unit 6 for scheduling the processing.
01.

When a plurality of addresses are candidates for the data key to be searched, the CAM 102 outputs the first address found during the search, and
The queue monitoring unit 105 is notified of a multiple address detection signal 504 for notifying that a plurality of addresses are referenced. Upon receiving this notification, the queue monitor 105
From the interface at 102, the data key is also obtained at the same time as this notification. This data key is stored in the duplicate data key FIFO 602 shown in FIG.

The faults of item numbers 2 to 5 out of the faults shown in FIG. 5 can be detected by the multiple address detection signal 504. By eliminating the duplication of the data queue detected by the multiple address detection signal 504, it is possible to recover the failures of the item numbers 2 to 5. This restoration process is performed in the restoration processing unit 603 shown in FIG. 9 using the idle time in the switch process, and a flowchart thereof is shown in FIG. In the recovery processing by the recovery processing unit 603, the CAM 102 is searched based on the data key in the duplicate data key FIFO, and all the obtained cell blocks are changed to empty cell blocks.

Of the faults shown in FIG. 5, the fault No. 1 is
By searching the CAM 102 based on the abnormal queue type table 604 and changing all the obtained cell blocks to the empty cell blocks, the failure of the item No. 1 can be recovered. The abnormal queue type table 60
4 will be described later. This restoration processing is performed in the restoration processing unit 605 shown in FIG. 9 using the idle time in the switch processing, and a flowchart thereof is shown in FIG.

Next, the operation of this embodiment will be described with reference to the drawings.

Referring to FIG. 8, CAM 102 receives a mode switch 502 for switching between a normal RAM operation and a search operation using a data key. In the ordinary switch processing, as described in the section of the related art, the search operation and the RAM operation are a paired process.
In the search result, an address including the data key is returned. The interface at which this address is returned is not shown in FIG. 8, but it depends on the individual CAM device, and is not the focus of the present invention. As a search result, a multiple address detection signal 504 is transmitted when a plurality of addresses have a data key, and an address non-detection signal 505 is transmitted when there is no address including a data key.

As described with reference to FIG. 5, the appearance of all the faults depends on item No. 1, item Nos. 2 to 5, and item No. 6 in FIG.
And three types.

In the case of the failure of item No. 6, the existing queue is lost and the cell loss is correspondingly lost. However, the lost cell block in the cell buffer 101 becomes an empty cell block. The cell buffer 101 is used in the future and becomes a normal buffer state after cell loss due to tooth loss. The queue entity in the cell buffer 101 and the CAM 10
2 and the queue information managed by the memory 103 are also eliminated. Therefore, in the case of the failure of item No. 6, the recovery from the failure is automatically performed.

On the other hand, the fault of item No. 1 in FIG.
The failure 5 causes a permanent failure, so it is necessary to actively recover it.

The phenomenon caused by the item numbers 2 to 5 in FIG. 5 is that a plurality of queues having the same ID exist. Also, this phenomenon is caused by the multiple address detection signal 50.
4 is detected. Therefore, the data key to be searched when the multiple address detection signal 504 is transmitted is registered in the duplicate data key FIFO 602. For each data key registered in the duplicate data key FIFO 602, a plurality of IDs in the cell buffer 101 may be eliminated. Therefore, as shown in FIG. 10, the recovery processing unit 603
A data key is obtained from the FO 602 (F-1), and the CAM 102 is searched again using the obtained data key (F-2), and a cell block which seems to be abnormal is changed to an empty cell block (F-3). This processing is performed by using the duplicate data key FIFO 60
2 is repeatedly performed while the data key exists (F-
4). As a result, the queue in which the abnormality has occurred can be normally repaired.

A method for coping with the failure corresponding to the item 1 in FIG. 5 will be described below with reference to FIG.

The “block not belonging to any queue” shown in the column of the content of item No. 1 in FIG.
This is a case where the value is not used in the switch in iD304, seq306, and the like. For example, pri
D304 is 3 bits (priD304 value = 0-7) and the number of delay priority classes used in the system is 4 (priD304).
In the case of D304 value = 0 to 3), the remaining 4 classes are priD3
04, but should not be present as a queue. Therefore, the detection of the failure of item No. 1 in FIG. 5 is performed for all combinations that should not exist (Valid 302 =
Valid, port303 = XX, priD304 = YY
) Is used as a data key to perform a search in the CAM 102. If an address including the data key exists, all empty cell blocks (Valid
302 = invalid). In the abnormal queue type table 604, all the data keys of the above-described abnormal queue type examples are registered, and the data keys are subjected to the Round-Robin equation one by one. Therefore, as shown in FIG.
5 obtains a data key from the abnormal queue type table 604 (P-1), searches the CAM 102 with the obtained data key (P-2), and changes the cell block obtained by the search to an empty cell block (P-2). P-3). As a result, the queue in which the abnormality has occurred can be normally repaired.

The processing in the recovery processing units 603 and 605 uses the CAM 102 and the memory 103, which are resources used in normal switch processing, and must be performed during a time when the switch processing is idle. The processing control unit 601 illustrated in FIG. 9 detects this idle time, and one of the recovery processing units 603 and 605 lacks activation. Since both processes cannot be performed at once, the process control unit 601 sets the recovery processing unit 60 in accordance with a predetermined condition.
Scheduling of the process start of 3 and 605 is also performed.
The simplest scheduling is the FI for duplicate data keys
As long as there is a registered data key in the FO 602, the restoration processing unit 603 and the restoration processing unit 605 alternately
Performs processing according to the d-Robin expression,
If there is no registered data key in the FO 602, only the processing of the recovery processing unit 605 is performed. Note that the basis of the unit of each process described here is a search for one data key and blank cell blocking.

[0045]

The first effect according to the present invention is that when a plurality of cell blocks having the same ID exist in a certain queue, which is the obstacle of item Nos. 2 to 5 in FIG.
Can be eliminated and the cell can be returned to a normal queue. As a result, the cell loss characteristic can be improved to a normal value, and data interruption in abnormal operation of a permanent queue can be avoided.

The reason is that, in the CAM function, a function to notify when a plurality of addresses in a search by a data key is applicable,
O, a function of searching the CAM again using the data key registered in the FIFO, detecting a duplicate address, and performing a recovery process of changing to an empty cell block, and a process of performing the recovery process. In the idle time of the normal switch process.

The second effect of the present invention is that item 1 in FIG.
In the case where the queue of the type that should not exist at all is created in the cell buffer, which is the obstacle, the queue can be resolved and replaced with an empty cell block. As a result, the cell loss characteristics can be improved to a normal value.

The reason is that a queue type that should not exist in operation but is generated due to a circuit error or the like is registered in a table in the form of a data key, and a value registered in this table is used as a data key. This is because it has a function of performing a recovery process for changing the address obtained by the search to an empty cell block, and a function of performing this recovery process during the idle time of the normal switch process.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment to which a monitoring method of a shared buffer type switch using a CAM according to the present invention is applied.

FIG. 2 is a block diagram of a conventional example of a shared buffer type switch using a CAM.

FIG. 3 is a diagram showing a data format in a CAM shown in FIG. 2;

FIG. 4 is a diagram illustrating information included in a memory illustrated in FIG. 2;

FIG. 5 is a table showing types of failures caused by errors in information in a CAM and a memory shown in FIG. 2;

FIG. 6 is a diagram illustrating a phenomenon corresponding to each of the faults illustrated in FIG. 5;

FIG. 7 is a table showing which of the failures shown in FIG. 5 when an error occurs in each of the parameters shown in FIGS. 3 and 4;

FIG. 8 is a diagram showing input / output signals of the CAM shown in FIG.

FIG. 9 is an internal block diagram of a queue monitoring unit shown in FIG. 1;

FIG. 10 is a diagram showing a flowchart of a restoration process by a restoration processing unit 603.

FIG. 11 is a diagram illustrating a flowchart of a restoration process by a restoration processing unit 605.

[Explanation of symbols]

 Reference Signs List 101 Cell buffer 102 CAM 103 Memory 104 Buffer control unit 105 Queue monitoring unit

Claims (5)

(57) [Claims] 1. A cell buffer of a cell block in a shared buffer.
The physical address corresponding to the address
Stores information about ATM cells to be stored in the lock
CAM, which is an associative memory that manages
If there is more than one registration with data,
The middle part of the queue in the shared buffer has been destroyed
It is assumed that only multiple registrations corresponding to the destroyed area are available
By converting to the shared
So that it can be reused within
Cell switch without losing the unbroken queue of
A monitoring method for a shared buffer type switch using a CAM, characterized by continuing the above operation . 2. The cell buffer of a cell block in a shared buffer.
The physical address corresponding to the address
Stores information about ATM cells to be stored in the lock
CAM, which is an associative memory for
Register the queue type that should be in the table in the form of a data key
The value registered in the table is used as a data key.
Search for the CAM, and if registered, the corresponding C
A cell in the shared buffer corresponding to the physical address of the AM.
Cells written to the local address are generated due to errors
Is a part of the abnormal queue type
Address area to an empty cell block.
To enable reuse in the shared buffer.
A monitoring method for a shared buffer type switch using a CAM. 3. A cell buffer into which ATM cells arriving at a plurality of ports are multiplexed and inputted and written, a buffer controller for managing writing / reading of cells in the cell buffer as a QOS class queue, A CAM that is managed by the buffer control unit and manages the address of a QOS class queue in the cell buffer; a memory that manages a register necessary for managing the address of a QOS class queue in the cell buffer; And a queue monitoring unit for monitoring whether the queue management is normal and performing recovery when the queue management is abnormal. 4. When the CAM searches for an address from a data key, the CAM has a plurality of address detection signal output means for outputting a plurality of address detection signals when a plurality of addresses have the data key used for the search, The queue monitoring unit includes a first restoration processing unit that receives the multiple address detection signal and changes a plurality of addresses obtained by a search when the CAM outputs the multiple address detection signal to an empty cell block. A shared buffer type switch using a CAM according to claim 3, characterized in that: 5. A queue monitoring unit according to claim 1, wherein said queue monitoring unit registers a queue type that is supposed to be non-existent in operation in the form of a data key, and uses a value registered in said table as a data key.
5. The shared buffer type switch using a CAM according to claim 3, further comprising: a second recovery processing unit that searches for M and changes an address obtained by the search to an empty cell block.