JP2942738B2 - Data decryption IC - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data decoding IC.
MPEG (Moving Picture C)
Odging Experts Group) 1, MP
EG2, MPEG4, or an equivalent H.264. 261
The present invention relates to a data decoding IC that performs a decoding process on image data and audio data encoded in accordance with a standard represented by a standard.

[0002]

2. Description of the Related Art Conventionally, as a data integration IC having a high degree of integration, an MPEG decoder used for reproducing moving images and the like has been known. This is being applied to a player (reproducing apparatus) using a CD-ROM as a recording medium.
A data stream encoded in accordance with the MPEG standard is recorded on the CD-ROM in advance, and the MPEG decoder reads the data stream from the CD-ROM when performing reproduction on such a CD-ROM. At the same time as reading, the MPEG decoder decodes the read data stream to restore video and audio.

[0003] While MPEG relates to general-purpose data compression that does not specify a recording medium, CD-ROM is a specific medium that is affected by scratches and dirt.
Data recorded in the D-ROM has been subjected to specific processing such as addition of redundant data and spatial distribution. For this reason, MPEG decoders usually have 8 bytes, whereas general-purpose processors such as personal computers use bytes or multiples of bytes as units.
While a data stream in units of bits or 16 bits is handled, data read from a CD-ROM is handled in a bit stream of a column in units of 1 bit.

Therefore, generally, a functional block diagram of a CD-ROM player is shown in FIG.
CD-R between the M reading circuit and the MPEG decoder
Matching is achieved with an OM decoder interposed. That is, a CD-D made of a digital signal processor or the like that reads recorded data from the CD-ROM 10 and performs a restoration process corresponding to a specific process and outputs a bit stream.
SP20 and a CD-ROM decoder 30 for converting the bit stream into a data stream of a plurality of bits in parallel
Then, the data stream is input, and a predetermined decoding process is performed on the data stream to restore a video signal and an audio signal, which are sent to the CRT 60 and the speaker 70, respectively.

[0005] The MPEG decoder 40 uses the "latest M
Although it is described in publications such as "PEG textbooks", it has the following functions. That is, it has a buffer 41 composed of a first-in first-out FIFO or the like to buffer the data stream input timing.
1 (DMU) which receives the data stream via
X) 42 to separate the data stream into audio data and video data for each variable length code, and to store them separately in ring buffers 81 and 82. An audio decoder 71 for inputting audio data from the ring buffer 81 and restoring an audio signal is provided. The audio decoder 71 transmits the audio signal to the speaker 70 and decodes a video with the next video decoder. .

The video decoder of the MPEG decoder 40 receives video data from the ring buffer 82, restores the video signal, and sends the video signal to the CRT 60 in units of variable-length code from the ring buffer 82 by Huffman coding or other entropy coding. While having a variable length decoding unit 51 for inputting data to perform a reversible decoding process,
The subsequent inverse quantization unit 52 and inverse DC
After performing an irreversible decoding process by a T (Inverse Discrete Cosine Transform) unit 53, and performing a motion compensation process corresponding to each picture type by the compensating unit 54, the I picture 83
, A P picture 84, a B picture 85, and a display image 86. Further, a video output unit 61 is also provided so that a display image 86 is sent to the CRT 60 and displayed. Note that I picture 8
3 is an image that can be decoded by itself, P picture 84 is an image that can be decoded by referring to I picture 83 in addition to the data, and B picture 85 is an image that can be decoded in addition to the data. I picture 83 and P picture 8
4 is an image that can be decoded by referring to both of them.

[0007] A CD-ROM player having such a function is used for the above-mentioned CD-ROM player when realizing hardware.
-The DSP 20, the CD-ROM decoder 30, the MPEG decoder 40, and the controller 90 described later are integrated on separate ICs, respectively, and then mounted on a single substrate or a plurality of substrates. FIG. 4 is a circuit block diagram of the circuit, and the same reference numerals are given to circuit blocks having the corresponding functions in FIG. The IC of the CD-ROM decoder 30 includes:
In addition to an error code correction (ECC) circuit that could not be integrated on the CD-DSP 20, a bit stream A from the CD-DSP 20 is converted into an 8-bit or 16-bit data stream B, and the buffer 41 of the MPEG decoder 40 is converted. Serial-to-parallel conversion (S / P conversion)
Circuit is also provided.

[0008] The IC of the MPEG decoder 40 includes a system decoder including a buffer 41 and a separation unit 42, a variable length decoding unit 51, an inverse quantization unit 52, an inverse DCT unit 53, a motion compensation unit 54, and a video output unit 61. A video decoder including
The audio decoder 71 is roughly classified. The ring buffers 81 and 82 and the pictures 83, 84 and 8
5. Further, the display image 86 is allocated to the memory 80.

The system decoder section of the MPEG decoder 40 includes a timing control circuit 44 for causing the audio synchronization adjustment circuit 43 to perform synchronization adjustment and the like of the audio decoder 71 based on the timing information extracted from the data stream by the separation section 42. Timing control circuit 4
And a video synchronization circuit 45 that performs synchronization adjustment and the like of the variable length decoding unit 51 and the like in accordance with the control of (4). In addition, a host interface 46 for a controller 90 which can be regarded as a host computer when viewed from the MPEG decoder 40 is also provided. The host interface 46 has a number of registers with addresses, and the parameters sent from the controller 90 are set in the registers of the designated address. The parameters set in the registers retain their set values until reset or overwritten, and are sent to internal circuits such as a video decoder and an audio decoder as control signals or signals equivalent thereto. This allows
The MPEG decoder 40 is provided with parameter holding means for holding parameters including decoding conditions for decoding processing.

The video decoder section of the MPEG decoder 40 includes a video / audio ring buffer control circuit for performing control for matching access to the ring buffers 81 and 82 by the separation section 42, the variable length decoding section 51 and the audio decoder 71. 55 and each picture 83, 84, 85
An MC bank processing circuit 56 for processing the access to the motion compensator 54 by the bank switching method.
The memory 8 is designed to avoid contention and the like caused by the audio ring buffer control circuit 55 and the MC bank processing circuit 56.
A bus arbiter 57 for controlling access to the arbiter 0; a video / frame synchronization adjusting circuit 58 for performing synchronization control such that decoding processing by the variable length decoding unit 51 and the motion compensation unit 54 is performed at a timing synchronized for each frame; A line memory read unit 62 for reading the display image 86 and sending it to the video output unit 61 while avoiding competition with the MC bank processing circuit 56 and the like via the 57 is provided. Further, the variable length decoding unit 51 of the video decoder unit
Is provided with an error detection circuit 59, and the input data contains an unexpected code or the input data is broken so that error correction based on redundant bits cannot be performed.
When it is detected that an undecodable error exists in the input data, a significant error detection signal E is sent to the motion compensator 54 to skip the picture generation / image update based on the data. As a result, the MPEG decoder 40 is provided with a detecting means for detecting an error accompanying the variable length decoding as a part of the decoding circuit.

The controller 90 has a microprocessor system and is programmable. In addition to a DSP control unit 91 for controlling the operation state of the CD-DSP 20 by processing of a predetermined program, the controller 90 also performs processing of a predetermined program. MPEG sending parameters to host interface 46 of MPEG decoder 40
A control unit 92 is also provided. The MPEG control unit 92 controls the CD
Prior to reading from the CD-ROM 10 by the DSP 20, parameters necessary for initialization of the MPEG decoder 40 are set, and the CD-R by the CD-DSP 20
If the reading from the OM 10 is not performed, the parameters are set as needed. When sending the parameters, the register address C and the parameter value data D in the host interface 46 are output as a pair. It has become.

As described above, in the conventional data decoding IC,
In addition to a multi-bit data stream to be decoded, a large number of parameters that determine processing conditions and the like are also input.
The number of connection terminals to the outside of C is provided in a number corresponding to the number of bits.

[0013]

However, recent ICs
In order to reduce the circuit mounting scale and downsize the device based on the improvement of the integration degree and the development progress of the device such as a CD-ROM player, at least the S / P conversion circuit of the CD-ROM decoder is provided by an MPEG decoder. Take in the IC,
It has been demanded that the individual mounting of the CD-ROM decoder IC becomes unnecessary. And then, MP
It is expected that a size reduction for the EG decoder IC will also be required.

However, when the CD-ROM decoder is simply incorporated in the MPEG decoder IC (see FIG. 5), the mounting scale is not reduced even if the degree of integration of the IC is improved. By directly inputting the bit stream instead of the data stream, the number of IC pins and the like for the bit stream is reduced, but a large number of pins provided corresponding to each bit of the register address C and the data D for inputting the parameter are provided. This is because IC pins and the like remain, which hinder miniaturization of the IC package.

Therefore, it is an object to reduce the number of external connection terminals such as IC pins without impairing functions relating to data decoding processing including parameter setting. The present invention has been made to solve such a problem, and has as its object to realize a small-sized data decoding IC with a reduced number of external connection terminals.

[0016]

Means for Solving the Problems First to fourth solving means invented to solve such problems are as follows.
The configuration and operation and effect will be described below.

[First Solution] The data decoding IC of the first solution (as described in claim 1 at the time of filing the application)
A decoding circuit that performs a decoding process on a data stream, a detection unit that is provided as a part of the decoding circuit or that is separately provided and that detects an error associated with the decoding process, and holds a parameter including a decoding condition for the decoding process. A data decoding IC provided with a parameter holding means for receiving data from the outside and a switching circuit for switching a destination of the data to one of the decoding circuit and the parameter holding means; The destination of the input data is selected accordingly (so that the input data is sent to the parameter holding means when an undecodable error is detected, and otherwise the input data is sent to the decoding circuit). Selecting means for controlling the switching circuit (based on this selection).

The data decoding I of the first solving means as described above.
In C, it is assumed that the data stream is normally encoded before being sent to the present IC, and the parameters are used in an environment in which the parameters are not coded or are differently encoded before being sent to the present IC.

When data is input from outside,
If the data is a correctly encoded data stream, the data is sent by a switching circuit to a decoding circuit, where it is decoded. Thus, in this case, the decoding process is properly performed. On the other hand, when the data from the outside is a parameter, the data is not correctly encoded, so that it is detected by the detecting means, and the switching circuit is controlled by the selecting means according to the detection result so as to change the transmission destination. As a result, external input data is
It is sent to the parameter holding means. As a result, also in this case, the parameters are set appropriately. In this way, conventional functions are maintained without any loss.

In addition, since the data stream and the parameter are input to the same switching circuit, the input line or the input terminal of the switching circuit is shared by the data stream and the parameter. External connection terminals such as pins are also shared. As a result, the number of external connection terminals is reduced by the amount shared.

Therefore, the number of external connection terminals such as IC pins can be reduced without impairing functions relating to data decoding processing including parameter setting. Therefore, according to the present invention, a small-sized data decoding IC can be realized with a reduced number of external connection terminals.

[Second Solution] The data decoding IC of the second solution (as described in claim 2 at the beginning of the application)
In the data decoding IC according to the first solving means, the switching circuit has a single input line or input terminal.

The data decoding I of such a second solution means
In the case of C, input data sent as a bit stream from the outside is appropriately divided into a data stream and parameters by a switching circuit or the like and sent to a decoding circuit or parameter holding means. This minimizes the number of pins for inputting data streams and parameters to one.
You can do it with a book. Therefore, according to the present invention, it is possible to realize a small-sized data decoding IC with the least number of external connection terminals.

[Third Solution] The data decoding IC of the third solution (as described in claim 3 at the beginning of the application)
A data decoding IC according to the first and second solving means, wherein the decoding circuit is an MPEG decoder, and the detecting means detects a code error in a variable length decoding unit of the decoder. It is characterized by being.

The data decoding I of the third solving means as described above.
In C, the code error detection necessary for selecting and sorting the data stream and the parameters is performed by the internal circuit of the variable length decoding unit, so that the existing circuit can be used without adding a new detection circuit. You can use it. In addition, when the data stream is really noisy, it is temporarily switched to the parameter processing due to the error of the variable length code. However, since the parameter is incompatible, the switching state etc. is returned so that the data stream decoding processing is promptly performed. In the MPEG decoder, when an error of a variable length code is detected, the subsequent motion compensator or the like skips the picture generation processing or the like during the operation. There is no. As a result, the existing detection circuit is shared without inconvenience, so that the scale of the additional circuit can be suppressed accordingly. Therefore, according to the present invention, a smaller data decoding IC can be realized by reducing the number of external connection terminals and suppressing the scale of an additional circuit for that purpose without inconvenience.

[Fourth Solution] A data decoding IC according to a fourth solution (as described in claim 4 at the beginning of the application)
A data decoding IC according to any one of the first to third solving means, wherein a CD-ROM decoder is incorporated so as to be interposed between the switching circuit and the decoding circuit. is there.

The data decoding I of the fourth solving means as described above.
C has a built-in CD-ROM decoder, which contributes to downsizing of a mounted CD-ROM player. Moreover, by combining with a general CD-DSP that reads recorded data from a CD-ROM and outputs it as a bit stream as a subsequent circuit that inputs the bit stream, a large-scale circuit or a special circuit is not interposed. It is also possible to easily construct a CD-ROM player system. Thus, a compact and inexpensive CD-ROM player can be realized.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The data decoding IC of the present invention achieved by such a solution is used together with a controller as follows to constitute a desired system. When setting the parameters in the data decoding IC, the controller transmits the parameters to the transmission line of the data stream when the data stream is not transmitted to the IC or when the data stream does not need to be transmitted. Also, when sending parameters, headers and dummy data that do not conform to the original encoding are preceded.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific configuration of a CD-ROM player as one embodiment of the data decoding IC of the present invention is as follows.
The description will be made with reference to the circuit block of FIG. The difference between the player shown in FIG. 1 and the one shown in FIG. 4 in the conventional example is that the CD-ROM decoder 330 is integrated immediately before the buffer 41 and the switching circuit and the decoding circuit are similar to the player shown in FIG. In addition to being built in so as to be interposed between the circuit and the circuit, parameters set in each register of the host interface 46 by the controller are input to the MPEG decoder IC via the signal line of the bit stream A. This is the point that is to be done.

Specifically, the CD-DSP 20 and the MPEG
A selector 401 is inserted in the line of the bit stream A between the decoder ICs 400, and the controller 900 sends parameters via the selector 401 instead of sending the parameters directly to the MPEG decoder IC 400.
The G decoder IC 400 is provided with a serial / parallel conversion circuit 403 in addition to a switch circuit 402 as a switching circuit and a mode selection circuit 404 as selection means. Note that the same components as those in the related art are denoted by the same reference numerals and are not illustrated, so that repeated description will be omitted, and the following description will focus on the differences.

The controller 900 includes an MPEG control unit 9
2 is replaced by the MPEG control unit 920, and the universal asynchronous receiver transmitter (UAR
T) 921 is different from the controller 90 in that a T) 921 is added. The UART 921 is a general-purpose parallel-serial conversion circuit. Here, a transmitter is used, and the UART 921 converts a parameter into a start-stop synchronous type so that serial transmission is possible and outputs the converted parameter.

The MPEG control section 920 outputs the parameters to the UA instead of directly outputting the parameters to the MPEG decoder IC 400.
The output is sent to the RT 921 and sent indirectly, and the control signal is sent to the selector 401. Also,
By monitoring the operation state of the DSP control unit 91, it is detected whether or not the bit stream A is output from the CD-DSP 20, and only when the data stream A is not output, the parameter transmission via the UART 921 is performed. I do. At this time, the control state of the selector 401 is also switched. Further, at the time of sending the parameters, a break signal having a sufficient number of bits for error detection by the error detection circuit 59 is output, and then valid parameters are sent. As a result, the controller 900 precedes dummy data that does not conform to the original encoding when sending parameters. At the end of the parameter transmission, a predetermined end code is transmitted.

The selector 401 is a two-input one-output selector, and each input and output is of one bit. The bit stream A from the CD-DSP 20 is received as one input, the output of the UART 921 is received as the other input, and one of the inputs is output to the MPEG decoder IC 400 under the control of the MPEG control unit 920. The output line is connected to one IC pin of the MPEG decoder IC 400, that is, an external connection terminal. As a result, the selector 401 also sends parameters to the sending line of the data stream.

The switch circuit 402 is a one-input two-output switch circuit, and each input and output is one bit. Its input terminal is connected to an IC pin to which the output of the selector 401 is connected, that is, an external connection terminal.
The input terminal of the ROM decoder 330 is connected to the input terminal, and the other output terminal is connected to a serial / parallel conversion circuit 403 provided before the host interface 46. As a result, the switch circuit 402 has a single input terminal and a single input line, inputs data from the outside, and sends the data to the CD-ROM decoder 330 and the variable-length decoding unit 51 or the like (decoding circuit). And switch to one of the registers (parameter holding means) of the host interface 46.

The serial / parallel conversion circuit 403 has a UA
This circuit is substantially equivalent to the RT receiver, and performs serial-parallel conversion for returning data serially transmitted in an asynchronous system to parallel data. The serial-to-parallel conversion circuit 403 receives the other output of the switch circuit 402, inputs parameters, and returns to the original data format. Further, the serial / parallel conversion circuit 403 stores the parameters in the register address C and the data D
Are sent to the host interface 46, and when a predetermined end code is received at the end of the parameter, a mode change trigger signal is sent to the mode selection circuit 404.

The mode selection circuit 404 includes an error detection circuit 5
9 and a mode change trigger signal from the serial / parallel conversion circuit 403, and sends a control signal to the switch circuit 402 to switch the output destination of the switch circuit 402. Immediately after initialization or in a steady state, the data stream decoding mode is selected and the output destination of the switch circuit 402 is a CD-ROM.
Control is performed on the decoder 330 side. Then, when the error detection signal E becomes significant, the parameter setting mode is selected, and the switch circuit 402 is controlled such that the output of the switch circuit 402 is to the serial / parallel conversion circuit 403 side.

Further, when a mode change trigger is received from the serial / parallel conversion circuit 403 in the parameter setting mode, the data stream decoding mode is selected again.
The output of the switch circuit 402 is the CD-ROM decoder 3
The switch circuit 402 is controlled so as to be on the 30 side. As a result, the mode selection circuit 404 sends the input data to the switch circuit 402 as the destination of the input data of the switch circuit 402 according to the error detection signal E which is the detection result of the error detection circuit 59 as the detection means.
The switch circuit 402 is controlled by selecting either the D-ROM decoder 330 or the serial / parallel conversion circuit 403. Then, when an undecodable error is detected, the input data of the switch circuit 402 is sent to the parameter holding means. Otherwise, the input data is sent to the decoding circuit.

The usage and operation of the data decoding IC of this embodiment will be described.

When the power of the CD-ROM player is turned on, the controller 900 is reset after hardware reset.
Performs a predetermined initial setting for each circuit under the control.
For the MPEG decoder IC 400, predetermined parameters are set in the respective registers of the host interface 46 as follows. That is, the MPEG control unit 920
Controls the selector 401 so that the output of the UART 921 is selected as the input of the selector 401, and causes the UART 921 to transmit a break signal of a predetermined length.

Then, the break signal is supplied to the selector 401,
The switch circuit 402, the CD-ROM decoder 330, the buffer 41, the separation unit 42, and the video / audio
The data is sent to the variable length decoding unit 51 via the ring buffer control circuit 55 in order. In the variable-length decoding unit 51, the error detection circuit 59 detects the break signal as a kind of code error, and makes the error detection signal E significant. Then, in response to this, the parameter selection mode is selected in the mode selection circuit 404, and the output destination of the switch circuit 402 is the CD-R
From the OM decoder 330 to the serial / parallel conversion circuit 40
Switched to 3.

When the transmission of the break signal is completed, the MPEG
The control unit 920 sends a series of parameters to the UART 921. Then, these parameters are sequentially
After being converted into serial data by the ART 921, the data is transmitted to the serial / parallel conversion circuit 403 via the selector 401 and the switch circuit 402, where it is inversely converted into a register address C and data D, and further converted into a register of the corresponding address of the host interface 46. The corresponding data is set one after another. Thus, the parameters are sequentially written to each register of the host interface 46 via the signal path of the bit stream A.

When a series of parameter settings are completed, the MPE
The G control unit 920 sends a predetermined end code to the UART 921
Send to Then, as with the parameters,
After being converted into serial data by the UART 921, the data is transmitted to the serial / parallel conversion circuit 403 via the selector 401 and the switch circuit 402. However, when the end code is detected there, the host interface 46
Instead, a mode change trigger is sent to the mode selection circuit 404. Then, the mode selection circuit 40 receiving this
4, the data stream decoding mode is selected and the output destination of the switch circuit 402 is the serial / parallel conversion circuit 4.
03 to the CD-ROM decoder 330. Further, the MPEG control unit 920 controls the selector 401
To return to the state where the output of the CD-DSP 20, that is, the bit stream A is selected as the input of the selector 401. Thus, the MPEG decoder IC
The parameter setting for 400 is completed, and the apparatus is brought into a state where the apparatus can be operated in a steady state.

In this state, when the CD-ROM 10 is set in a reading section (not shown) and a reproduction start operation is performed, the recording data read from the CD-ROM 10
The bit stream A is converted into a bit stream A by the D-DSP 20, and the bit stream A is sent to the switch circuit 402 via the selector 401. The data stream input to the MPEG decoder IC 400 via one IC pin in this manner includes a CD-R in the MPEG decoder IC 400.
The decoding process described in the conventional example is performed by the OM decoder 330 and the circuits after the buffer 41. Thus, the video and the sound are reproduced and output from the CRT 60 and the speaker 70.

When noise exceeding the correction capability of the CD-ROM decoder 330 is applied to the signal line of the bit stream A between the CD-DSP 20 and the MPEG decoder IC 400, the following occurs. In this case, the variable length code is changed to an incorrect code by noise, and this is detected by the error detection circuit 59. Then, the error detection signal E becomes significant,
In response to this, the motion compensation unit 54 stops updating the display image 86 until appropriate image data serving as the next reference, for example, a new I picture is obtained. In this way, by temporarily stopping the movement / change of the image, the image disturbed by the noise is prevented from being displayed.

On the other hand, when the error detection signal E is made significant,
The output destination of the switch circuit 402 is also changed to the serial / parallel conversion circuit 403 side by the mode change of the mode selection circuit 404 receiving this. In this case, however, the data received by the serial / parallel conversion circuit 403 is not a break signal, and the start / stop is performed. Since the data does not conform to the synchronous data format, a mode change trigger is immediately transmitted from the serial / parallel conversion circuit 403 to the mode selection circuit 404, and the transmission destination of the switch circuit 402 is set to the CD-ROM decoder 33.
It is quickly returned to the 0 side. Thus, while the motion / change of the video is stopped by the motion compensation unit 54,
The bit stream A is again transmitted to the CD-ROM decoder 330.
And the data is sent to the decoding circuit after the buffer 41, so that the reproduction process is continued without any trouble.

FIG. 2 is a block diagram showing a CD-ROM player according to a second embodiment of the data decoding IC of the present invention. This is different from the above-described first embodiment in that the selector 401 is replaced by a wired OR connection unit 405. Since the control of the selector 401 becomes unnecessary, the MPEG control unit 920
2. Make it in time. Then, the output of UART 921 and C
An open-collector type driver is adopted for the output of the D-DSP 20, and their output lines are connected to one and then to the corresponding pin of the MPEG decoder IC 400. In this case, it is only necessary to provide an appropriate pull-up resistor instead of the selector 401, so that the simplification of the circuit is further advanced.

In each of the above examples, the MPEG control unit 9
UART is used as a general-purpose parallel / serial conversion means interposed between the host interface 46 and the host interface 46,
This can be any device that can perform serial transfer and has a required transmission speed, such as USB or IE.
It is also possible to use EE1394 equivalents.

[0048]

As is apparent from the above description, in the data decoding IC according to the first solution of the present invention, the external connection terminals for inputting data streams and parameters are shared without impairing the functions. With this arrangement, there is an advantageous effect that a small-sized data decoding IC can be realized with a reduced number of external connection terminals.

In the data decoding IC according to the second solving means of the present invention, the data stream and the parameter can be received as a bit stream.
There is an advantageous effect that a small-sized data decoding IC can be realized with the minimum number of external connection terminals.

Further, in the data decoding IC according to the third solution of the present invention, the existing detection circuit is shared without inconvenience in practical use, so that the number of external connection terminals is reduced and additional data is added. There is an advantageous effect that a smaller data decoding IC can be realized by suppressing the circuit scale.

Further, in the data decoding IC according to the fourth solution of the present invention, a compact and inexpensive CD-RO can be used because a general CD-DSP can be easily used.
There is an advantageous effect that the M player can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a first embodiment of a data decoding IC according to the present invention.

FIG. 2 is a circuit block diagram of a data decoding IC according to a second embodiment of the present invention;

FIG. 3 is a functional block diagram of a general MPEG decoder.

FIG. 4 is a block diagram of a conventional MPEG decoder IC.

FIG. 5 is an expected configuration diagram when a CD-ROM decoder is also integrated.

[Explanation of symbols]

Reference Signs List 10 CD-ROM (compact disk, recording medium) 20 CD-DSP (CD digital signal processor) 30 CD-ROM decoder (CD-ROM decoding unit) 40 MPEG decoder 41 Buffer (FIFO, data stream buffer) 42 Separation unit (DMUX) , Audio / video separation unit) 43 audio synchronization adjustment circuit 44 timing control circuit 45 video synchronization circuit 46 host interface (HI / F) 51 variable length decoding unit (VLD) 52 inverse quantization unit (Q-1) 53 inverse DCT unit (DCT-1, inverse discrete cosine transform) 54 Motion compensation unit (MC) 55 Video / audio ring buffer control circuit 56 MC bank processing circuit (image memory bank processing) 57 Bus arbiter 58 Video / frame synchronization adjustment circuit 59 Error Detection times Road 60 CRT (video display unit) 61 video output unit (VOUT) 62 line memory read unit (display image readout circuit) 70 speaker (sound output unit) 71 audio decoder 80 memory 81 ring buffer (audio variable length data buffer) 82 Ring buffer (video variable length data buffer) 83 I picture (restored image) 84 P picture (restored image) 85 B picture (restored image) 86 Display image (restored image, reproduced video) 90 Controller (CPU, microprocessor) 91 DSP Control unit 92 MPEG control unit 300 MPEG decoder IC (data decoding IC) 330 CD-ROM decoder (CD-ROM decoding unit) 400 MPEG decoder IC (data decoding IC) 401 selector 402 switch circuit (switching circuit) 403 serial 405 Mode selection circuit (selection means) 405 Wired OR connection section 900 Controller (CPU, microprocessor) 920 MPEG control section 921 UART (parallel-serial conversion, general-purpose parallel-serial conversion means) A Bit stream B data stream C register address D data (parameter) E error detection signal

Claims (4)

(57) [Claims] 1. A decoding circuit for performing a decoding process on a data stream, a detecting means provided as a part of or separately from the decoding circuit for detecting an error accompanying the decoding process, and a decoding condition for the decoding process. A switching circuit for externally inputting data and switching the destination to one of the decoding circuit and the parameter holding means in a data decoding IC provided with parameter holding means for holding the included parameters; Selecting means for selecting a transmission destination of the input data in accordance with a detection result of the means and controlling the switching circuit. 2. The data decoding IC according to claim 1, wherein said switching circuit has a single input line or input terminal. 3. The decoding circuit is an MPEG decoder,
3. The data decoding IC according to claim 1, wherein the detection means is a circuit for detecting a code error in the variable length decoding unit. 4. A data decoding IC according to claim 1, further comprising a built-in CD-ROM decoder interposed between said switching circuit and said decoding circuit. .